Chip surface defect detection method, device and storage medium

Abstract

The present application relates to the technical field of chip defect detection, and in particular to a chip surface defect detection method, device and storage medium, the method comprising: obtaining a detection area image including a target chip; matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image; determining multiple detection points on the detection area image according to the binding rectangle; continuously judging whether the first difference between the gray value corresponding to each detection point and the standard gray value is greater than a first difference threshold, and determining the detection point whose first difference is greater than the first difference threshold as an offset point; determining the offset score of each offset point; judging whether the total offset score of the offset points formed by continuous series connection reaches the edge collapse score, and if there is a series connection The total offset score of the offset points reaches the edge collapse score, it is determined that the target chip has edge collapse. The present application can achieve the beneficial effect of improving the efficiency of chip surface defect detection.

Description

Technical Field

[0001] The present application relates to the technical field of chip defect detection, and in particular to a chip surface defect detection method, device and storage medium. Background Art

[0002] During the physical processing of wafer cutting, grinding or polishing, if the external force applied is too large or uneven, it may cause chip edge collapse, which will damage the circuit in the edge area of ​​the wafer, affect the performance of the entire chip, and even cause the entire chip to fail. Therefore, the detection of chip edge collapse is an indispensable part of the chip production process. It plays an important role in ensuring the accuracy of semiconductor manufacturing, improving product yield, preventing pollution, optimizing production processes, and equipment maintenance.

[0003] The invention patent with publication number CN116109572A discloses a method, device and electronic equipment for detecting slight defects on the edge of a workpiece. The method obtains the image information of the edge of the workpiece to be detected (i.e., the chip to be detected) and extracts the contour. The angle information of each contour point in the extracted contour is then determined. Based on the angle information, it is determined whether there is a defect at the corresponding position of the workpiece to be detected. In the existing related technology, the target contour points that have been determined can be connected to detect slender edge collapse defects.

[0004] In the existing solution, it is necessary to obtain all the contour information of the edge of the chip to be detected before further defect detection of the chip can be performed. In general, in industrial applications, please refer to Figure 1 , Figure 1 This is a typical schematic diagram of the field of view of chip surface defect detection. The entire large box is the detection area, and each small box is the field of view of the image acquisition device (camera). Each camera field of view has about 10-20 chips to be detected. The camera moves in sequence to obtain images of multiple camera fields of view and perform chip detection. If all contour point information is obtained for each chip to be detected first, and then the presence of slender edge collapse defects is determined based on the connection of contour points, the impact on the detection efficiency of the entire detection process is difficult to ignore. Based on this, how to further optimize the chip surface defect detection method to improve chip detection efficiency is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of this application is to provide a chip surface defect detection method, device and storage medium, which can achieve the beneficial effect of improving the efficiency of chip surface defect detection.

[0006] The first aspect of the present application provides a chip surface defect detection method, comprising:

[0007] Acquiring an image of the detection area including the target chip;

[0008] matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image;

[0009] Determine a plurality of detection points on the detection area image according to the binding rectangle;

[0010] Continuously detecting the detection points, including determining whether a first difference between a grayscale value corresponding to each of the detection points and a standard grayscale value is greater than a first difference threshold, and determining the detection points whose first difference is greater than the first difference threshold as offset points, wherein the standard grayscale value is a grayscale value of a pixel corresponding to each of the detection points in a binding rectangle of the chip image template;

[0011] Determining the offset score value of each of the offset points, including judging whether the first difference value of each of the offset points is greater than a second difference threshold, and determining that the offset score value corresponding to the offset point whose first difference value is not greater than the second difference threshold value is a first score value, the offset score value corresponding to the offset point whose first difference value is greater than the second difference threshold value is a second score value, and the first score value is less than the second score value;

[0012] Determine whether the total offset score of the continuous series of offset points in the offset points reaches the edge collapse score. If the total offset score of the series of offset points reaches the edge collapse score, it is determined that the target chip has edge collapse. The total offset score is the sum of the offset score values ​​corresponding to all offset points in each series of the series of offset points.

[0013] Optionally, the step of matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image includes:

[0014] According to the chip image template, image matching is performed on the detection area image to obtain binding rectangles corresponding to one or more target chips;

[0015] According to the binding rectangle of each of the target chips, a target chip image of each of the target chips in the detection area image is determined.

[0016] Optionally, the step of performing image matching on the detection area image according to the chip image template includes:

[0017] Constructing a pyramid image based on the detection area image, including using the original image of the detection area image as the bottom layer of the pyramid image, and obtaining the pyramid image with a gradually decreasing resolution from the bottom layer to the upper layer through continuous downsampling;

[0018] Performing normalization calculation on each layer of the pyramid image to obtain a normalization index corresponding to each layer of the image;

[0019] According to the normalized index corresponding to each layer of the image, a binding rectangle of each target chip is matched in the detection area image.

[0020] Optionally, the step of determining a plurality of detection points on the detection area image according to the binding rectangle includes:

[0021] According to the rotation angle of the chip image template, the rotation angle of each target chip image is adjusted so that the rotation angle of each target chip image is consistent with the rotation angle of the chip image template.

[0022] Optionally, after the step of determining whether the total offset score of the offset points formed by continuous series connection has reached the edge collapse score, the method further includes:

[0023] If there is no series offset point whose total offset score reaches the edge collapse score, determining whether a second difference between each pixel point in the target chip image and a pixel point at a corresponding position in the chip image template is greater than a third difference threshold;

[0024] Marking a plurality of pixel points that are in an adjacent relationship and whose corresponding second difference values ​​are greater than the third difference threshold as a bad pixel point group;

[0025] Determine whether the number of pixels in the bad pixel group exceeds a bad pixel threshold;

[0026] If the number of pixels in the bad pixel group exceeds the bad pixel threshold, a corresponding area of ​​the pixel group on the target chip is determined to be a bad pixel.

[0027] Optionally, after the step of determining that a corresponding area of ​​the pixel group on the target chip is a bad pixel if the pixels in the bad pixel group exceed the bad pixel threshold, the step further includes:

[0028] According to the number of pixels corresponding to the bad pixel, adjusting the laser parameters for laser burning the corresponding position of the bad pixel to obtain the corresponding laser irradiation mode;

[0029] The laser irradiation mode is adopted to perform laser burning on the corresponding position of the bad spot.

[0030] Optionally, the step of matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image includes:

[0031] Extracting target features of the chip image template;

[0032] According to the target features, positioning and matching are performed in the detection area image to determine the binding rectangles corresponding to one or more target chips.

[0033] A second aspect of the present application provides a chip surface defect detection device, comprising:

[0034] An image acquisition module, which acquires an image of the detection area including the target chip;

[0035] a rectangle matching module, matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image;

[0036] A detection point determination module, which determines a plurality of detection points on the detection area image according to the binding rectangle;

[0037] An offset point judgment module is used to continuously detect the detection points, including judging whether a first difference between a grayscale value corresponding to each detection point and a standard grayscale value is greater than a first difference threshold, and determining that the detection point whose first difference is greater than the first difference threshold is an offset point, wherein the standard grayscale value is a grayscale value of a pixel corresponding to each detection point in a binding rectangle of the chip image template;

[0038] an offset score determination module, configured to determine an offset score value of each of the offset points, including determining whether the first difference value of each of the offset points is greater than a second difference threshold, and determining that an offset score value corresponding to an offset point whose first difference value is not greater than the second difference threshold is a first score value, an offset score value corresponding to an offset point whose first difference value is greater than the second difference threshold is a second score value, and the first score value is less than the second score value;

[0039] The chipping determination module determines whether the total offset score of the consecutively connected offset points in the offset points reaches the chipping score. If the total offset score of the consecutively connected offset points reaches the chipping score, it is determined that the target chip has chipping. The total offset score is the sum of the offset score values ​​corresponding to all the offset points in each series of the consecutively connected offset points.

[0040] Optionally, the rectangle matching module further includes:

[0041] An image matching submodule, used to perform image matching on the detection area image according to the chip image template to obtain a binding rectangle corresponding to one or more target chips;

[0042] The image extraction submodule is used to determine the target chip image of each target chip in the detection area image according to the binding rectangle of each target chip.

[0043] The image matching submodule also includes:

[0044] A pyramid construction unit, configured to construct a pyramid image based on the detection area image, including taking the original image of the detection area image as the bottom layer of the pyramid image, and obtaining the pyramid image with a gradually decreasing resolution from the bottom layer to the upper layer through continuous downsampling;

[0045] A normalization unit, used for performing normalization calculation on each layer of the pyramid image to obtain a normalization index corresponding to each layer of the image;

[0046] A rectangle matching unit is used to match the binding rectangle of each target chip in the detection area image according to the normalized index corresponding to each layer of the image.

[0047] A third aspect of the present application provides a storage medium storing a computer program that can be loaded by a processor and execute the above-mentioned chip surface defect detection method.

[0048] In summary, the beneficial effects of this application are:

[0049] An inspection area image including the target chip is obtained, and a binding rectangle of a standard chip image template used as a detection standard, i.e., a standard binding rectangle, is determined. An image matching algorithm (in this embodiment, the image matching algorithm used is a pyramid grayscale value matching) can be used to frame the images corresponding to one or more target chips in the inspection area image, and a binding rectangle of the corresponding target chip image is obtained. According to the binding rectangle of the target chip image and the standard rectangle, a plurality of detection points are set in the inspection area image.

[0050] Then, multiple detection points are continuously detected to determine whether each detection point is an offset point, and further the offset score corresponding to each offset point is determined according to the offset degree of each offset point (i.e., determining whether the first difference of the offset point is greater than the second difference threshold). In forming a continuous series of offset points, once the sum of the corresponding translation scores reaches the preset edge collapse score, it is determined that the target chip has edge collapse, and there is no need to obtain the grayscale information corresponding to all the detection points on the target chip, thereby improving the detection efficiency of a single chip with edge collapse, and further improving the efficiency of batch detection of chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a typical schematic diagram of the field of view for chip surface defect detection;

[0052] Figure 2 It is a schematic diagram of the process of the chip surface defect detection method provided in the embodiment of the present application;

[0053] Figure 3 is a schematic diagram of executing step S1 in the chip surface defect detection method provided in an embodiment of the present application;

[0054] Figure 4 It is a schematic diagram of the chip surface defect detection process provided by the embodiment of the present application;

[0055] Figure 5 is a schematic diagram of the edge analysis process provided by an embodiment of the present application;

[0056] Figure 6 It is a schematic diagram of the process of bad pixel processing provided by an embodiment of the present application;

[0057] Figure 7 is a schematic diagram of executing step S2 in the chip surface defect detection method provided in an embodiment of the present application;

[0058] Figure 8 is a schematic diagram of executing step S3 in the chip surface defect detection method provided in an embodiment of the present application;

[0059] Fig. 9 It is a flow chart of the steps included in step S4 of the chip surface defect detection method provided in an embodiment of the present application;

[0060] Fig.10 is a schematic diagram of executing step S4 in the chip surface defect detection method provided in an embodiment of the present application;

[0061] Fig.11 A schematic flow chart of the steps included in step S5 of the chip surface defect detection method provided in an embodiment of the present application;

[0062] Fig.12 is a schematic diagram of executing step S6 in the chip surface defect detection method provided in an embodiment of the present application;

[0063] Fig.13 It is a virtual structural diagram of a chip surface defect detection device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] The following examples will help those skilled in the art to further understand the effects of the present application, but are not intended to limit the present application in any form. It should be noted that, for those of ordinary skill in the art, several modifications and improvements may be made without departing from the concept of the present application. These all fall within the scope of protection of the present application.

[0065] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0066] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0067] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0068] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0069] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0070] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0071] In order to make the purpose, technical solutions and advantages of the present application clearer, the chip surface defect detection method of the present application is explained below from the perspective of a chip surface defect detection device. The chip surface defect detection device can be an electronic device, such as a mobile phone terminal, a computer terminal and other devices.

[0072] The present application is further described in detail below in conjunction with the accompanying drawings.

[0073] Reference Figure 2 , Figure 2 : is a flow chart of a chip surface defect detection method provided in an embodiment of the present application, the method comprises the following steps, the steps comprising:

[0074] S1: Acquire an image of the detection area including the target chip;

[0075] S2: matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image;

[0076] S3: determining a plurality of detection points on the detection area image according to the binding rectangle;

[0077] S4: Continuously detecting the detection points, including determining whether a first difference between a grayscale value corresponding to each detection point and a standard grayscale value is greater than a first difference threshold, and determining the detection point whose first difference is greater than the first difference threshold as an offset point, wherein the standard grayscale value is a grayscale value of a pixel corresponding to each detection point in a binding rectangle of the chip image template;

[0078] S5: Determine the offset score value of each offset point, including judging whether the first difference value of each offset point is greater than a second difference threshold value, and determining that the offset score value corresponding to the offset point whose first difference value is not greater than the second difference threshold value is a first score value, the offset score value corresponding to the offset point whose first difference value is greater than the second difference threshold value is a second score value, and the first score value is less than the second score value;

[0079] S6: Determine whether the total offset score of the offset points formed in series in the offset points reaches the edge collapse score. If the total offset score of the offset points in series reaches the edge collapse score, it is determined that the target chip has edge collapse. The total offset score is the sum of the offset score values ​​corresponding to all the offset points in each series of the offset points in series.

[0080] The following is a detailed description of each step:

[0081] In step S1, an image of a detection area including a target chip is acquired.

[0082] For details, please refer to Figure 3, Figure 3 It is a schematic diagram of the execution of step S1 in the chip surface defect detection method provided in an embodiment of the present application. The image of the detection area is obtained by the relevant image acquisition device. The image in the field of view can be obtained by the relevant image acquisition device (hereinafter referred to as the camera). The outer frame is the overall image of the detection area, including multiple camera fields of view (refer to the small box in the figure). Multiple chips to be detected can be placed in each camera field of view. Normally, 10-20 chips are placed in each camera field of view. In this embodiment, the camera moves in sequence according to a preset detection order to detect each camera field of view one by one.

[0083] More specifically, before acquiring an image of the detection area including the target chip, the device can be calibrated to avoid deviations in the acquired results. It mainly involves hardware calibration, calibrating the x-axis and y-axis of the image position and the axis relationship, and using the three-point calibration method for the z-axis of the height relationship. The three-point calibration method is a method for ensuring that the device is at the correct distance and accurate precision when scanning the wafer surface. The distance between the device and the wafer surface is adjusted to obtain the best image acquisition effect and analysis accuracy, ensuring that the device maintains proper focus and imaging quality throughout the scanning process, thereby avoiding image blur or distortion caused by height differences. During the calibration process, the platform plane is considered to be flat, but due to differences in equipment installation, the height varies at different positions, so matching adjustments are required.

[0084] More specifically, as an example, the method provided in this application can be applied to a host computer, and the relevant detection process can refer to Figure 4 , Figure 4 A schematic diagram of the chip surface defect detection process provided in an embodiment of the present application, before being turned on, the host computer enters a standby state after power-on and initialization. In the standby state, relevant personnel can control the entry into the detection process, first controlling the target chip to be detected to move to align with the relevant device, and then taking pictures through image acquisition devices such as cameras to obtain an image of the detection area including one or more target chips, and performing edge analysis and / or bad pixel area analysis based on the image of the detection area obtained by the camera.

[0085] On the one hand, edge analysis is used to analyze whether there are defects such as slight edge collapse, slight burrs, etc. on the edge of the chip, and to determine whether the detected target chip has edge collapse based on the acquired defect image, that is, edge collapse detection. The implementation process of edge collapse detection in an embodiment proposed in this application can refer to Figure 5 , Figure 5It is a flow chart of edge analysis provided by the embodiment of the present application. After acquiring the image of the detection area through the relevant image acquisition device (a camera in this embodiment), first determine the coordinates of the binding rectangle corresponding to the target chip in the acquired image, then generate an inspection line based on the coordinates, and determine whether there is a continuous offset part based on the inspection line to determine whether the edge is broken. After the determination is completed, the edge detection of the target chip is terminated. For the specific determination method of the broken edge, refer to the following steps.

[0086] On the other hand, for bad pixel area analysis based on the acquired target chip image, please refer to Figure 6 , Figure 6 This is a schematic diagram of the bad pixel processing process provided by the embodiment of the present application, wherein the bad pixel position is first marked according to the position of each pixel in the acquired target chip image by the following bad pixel analysis method, and then the corresponding laser is controlled to move to the marked bad pixel position for laser burning. In addition, the image is used to determine whether the bad pixel position is burned black to determine whether all bad pixels have been processed. If the processing is completed, the bad pixel processing process is terminated, otherwise the laser is controlled to move to the next bad pixel for laser burning until all bad pixels are processed.

[0087] In step S2, a binding rectangle of the target chip in the detection area image is matched according to a chip image template corresponding to the target chip in the detection area image.

[0088] For details, please refer to Figure 7 , Figure 7 It is a schematic diagram of the execution of step S2 in the chip surface defect detection method provided in an embodiment of the present application, including an exemplary chip image template, for any camera field of view in the detection area, and a binding rectangle of multiple target chips framed by dotted lines in the detection area corresponding to the chip image template. The chip image template is a standard chip image that meets the relevant standards, that is, a normal chip. In this embodiment, one or more target chips are matched in the detection area image according to the image of the normal chip, and the information of the target chip in the detection area image is recorded with a bound rectangle.

[0089] The binding rectangle is not an actual rectangle. The binding rectangle is used to record the image information of the target chip in the detection area image. The binding rectangle records at least the following information: the pixel value and coordinates of each pixel of the target chip in the detection area image, and the edge pixels of the target chip. That is, the binding rectangle not only records the pixel value and coordinates of each pixel, but also records which pixels belong to the edge of the target chip. For example, if the shape of the target chip is a rectangle, the binding rectangle not only records the pixel values ​​and coordinates of all pixels of the target chip in the first image, but also records the edge of the target chip, that is, the pixels corresponding to the four sides of the rectangle.

[0090] In this embodiment, based on the template image, an image matching algorithm is used to frame the images corresponding to one or more target chips in the detection area image, that is, to obtain the following binding rectangle, and then the detection area image can be extracted based on the obtained binding rectangle to obtain the image of each target chip, that is, one or more target chip images. In the binding rectangle, the position, edge pixels and other information of each target chip in the detection area image are recorded to facilitate image extraction. The edge of the target chip image corresponds to the edge of the target chip, and the edge pixel points of the target chip image are used as detection points. As an example and not a limitation, the detection area image can be cropped based on the binding rectangle to obtain the target chip image, and the edge circle of pixels of the target chip image is used as the detection point, that is:

[0091] According to the chip image template, image matching is performed on the detection area image to obtain binding rectangles corresponding to one or more target chips;

[0092] According to the binding rectangle of each of the target chips, a target chip image of each of the target chips in the detection area image is determined.

[0093] Specifically, in this embodiment, the image matching algorithm used is pyramid gray value matching, which is an image processing technology mainly used in the field of image matching and data fusion. Its core idea is to represent and process images at different resolution levels (i.e., different levels of the pyramid). The application of pyramid gray value matching in this application is described in detail below:

[0094] Constructing a pyramid image based on the detection area image, including using the original image of the detection area image as the bottom layer of the pyramid image, and obtaining the pyramid image with a gradually decreasing resolution from the bottom layer to the upper layer through continuous downsampling;

[0095] Performing normalization calculation on each layer of the pyramid image to obtain a normalization index corresponding to each layer of the image;

[0096] According to the normalized index corresponding to each layer of the image, a binding rectangle of each target chip is matched in the detection area image.

[0097] Specifically, a Gaussian pyramid is first constructed. The Gaussian pyramid is a set of image sequences obtained by subjecting the original image to continuous Gaussian blurring and downsampling. Each layer of the image is obtained by Gaussian blurring the image of the next layer and then sampling it, so that the image size of each layer is the same, but the resolution gradually decreases. In this embodiment, an image acquisition-related device (such as a camera) is used as the bottom layer of the pyramid, and a series of images with gradually decreasing resolutions are generated through continuous downsampling operations to form the upper layer of the pyramid. Then, a normalized index is calculated for each layer of the constructed Gaussian pyramid. The normalized index can be an NCC (Normalized Cross-Correlation, which means normalized cross-correlation in Chinese) value. NCC is a statistical index used to measure the similarity between two images. The closer its value is to 1, the better the match. Then, based on the NCC values ​​obtained in each layer, the position information of the best matching point is determined. This position information is used to guide the matching of the corresponding position points of each point in each target chip in the original detection area image. Finally, based on the matched result, the binding rectangles of each target chip are drawn in the detection area image. These binding rectangles frame the positions of the target chips, and the images of each target chip can be extracted based on this position information.

[0098] More specifically, after the image of the detection area in the field of view is acquired by the relevant image acquisition device, there may be a situation where the angle of the target chip is inconsistent with the angle of the template chip in the template image. In order to ensure the accuracy of the detection point, the image angle adjustment step is required, which is specifically described below:

[0099] According to the rotation angle of the chip image template, the rotation angle of each target chip image is adjusted so that the rotation angle of each target chip image is consistent with the rotation angle of the chip image template.

[0100] Specifically, in the process of extracting the target chip image from the detection area image, there may be a situation where the angle of the target chip is inconsistent with the angle of the template chip in the template image. Figure 2 As shown, the actual placement of multiple target chips corresponds to different rotation angles, which will cause the angle of the extracted target chip image to be inconsistent with the angle of the chip image template. If not processed, the positions of the target chip and the template chip will not correspond. For example, the coordinate system is established with the lower left corner of the target chip image and the template chip image as the origin. With the same coordinates, the corresponding point in the template image is the vertex in the upper left corner of the template chip, but the corresponding point in the target chip image may be the midpoint on the left side of the target chip.

[0101] Therefore, in this embodiment, the binding rectangle also records the rotation angle of the target chip, that is, the rotation angle relative to the template chip. The target chip image is rotated to be consistent with the template image according to the rotation angle of the binding rectangle. After the angles are restored to be consistent, the same coordinates in the target chip image and the template chip image correspond to the same positions of the target chip and the template chip. For example, the origin (0,0) in the target chip image and the template chip image both correspond to the vertex of the lower left corner of the target chip and the template chip.

[0102] In one embodiment proposed in the present application, feature extraction may be used to remove other images that are irrelevant to one or more target chips that require surface defect detection. Feature extraction is specifically described below:

[0103] Extracting target features of the chip image template;

[0104] According to the target features, positioning matching is performed in the detection area image to determine a binding rectangle corresponding to each target chip in the chip image template.

[0105] Specifically, the target features of the chip image template are first extracted, and the binding rectangle corresponding to each target chip is determined in the detection area image based on the target features of the chip image template. For example, a convolutional neural network model can be built, the target features of the chip image template are extracted to train the convolutional neural network model, and a trained convolutional neural network model is obtained. Finally, the detection area image is input into the trained convolutional neural network model to obtain the binding rectangle corresponding to each target chip.

[0106] In step S3, a plurality of detection points are determined on the detection area image according to the binding rectangle.

[0107] Specifically, for each matched target chip, multiple detection points are determined on the detection area image according to the binding rectangle. The detection points are the pixel points at the edge of the target chip in the detection area image. Please refer to Figure 8 , Figure 8It is a schematic diagram of the execution of step S3 in the chip surface defect detection method provided in the embodiment of the present application. Detection points are set on the chip image template, and then the detection points set on the chip image template are matched to the edges of each framed binding rectangle. It should be understood that the figure is only an example and does not represent the actual distribution of the detection points. The position of the target chip and the edge of the target chip can be determined in the detection area image according to the binding rectangle. After the edge of the target chip is determined, the detection point is determined according to the preset selection rule. For example, all the pixel points on the edge of the target chip in the detection area image can be used as detection points, or some of the pixel points on the edge of the target chip in the detection area image can be used as detection points. It should be understood that the more detection points there are on the edge of the target chip, the higher the detection accuracy will be, but the detection speed will decrease. Therefore, the selection rule of the detection point can be determined according to the specific situation, and the present application does not limit this.

[0108] In step S4, the detection points are detected continuously.

[0109] Specifically, refer to Fig. 9 , Fig. 9 It is a flow chart of the steps included in step S4 of the chip surface defect detection method provided in the embodiment of the present application. Whether the detection point is abnormal is determined by comparing the gray value of the detection point with the standard gray value, that is, comparing the difference between the edge of the target chip and the edge of the template chip in the image to determine whether the edge of the target chip is abnormal. Specifically, the following steps are included:

[0110] In step S41, it is determined whether a first difference between the grayscale value corresponding to each detection point and a standard grayscale value is greater than a first difference threshold, wherein the standard grayscale value is a grayscale value of a pixel corresponding to each detection point in a binding rectangle of the chip image template;

[0111] In step S42, a detection point where the first difference is greater than the first difference threshold is determined as an offset point.

[0112] More specifically, please refer to Fig.10 , Fig.10It is a schematic diagram of the execution of step S4 in the chip surface defect detection method provided by the embodiment of the present application, including two groups of continuous detection points, namely, serial connection point 1 and serial connection point 2, wherein the black point is an offset point whose first difference is greater than the preset first difference threshold, and correspondingly, the white point is an unoffset point, i.e., a normal pixel point. In the present application, the detection points corresponding to the target chip image are based on a preset detection order, and the detection order can be adjusted according to the actual needs of relevant personnel, or can be preset in relevant equipment. For example, a detection point is located at the vertex of the upper left corner of the target chip, and the standard grayscale value corresponding to the detection point is the grayscale value of the vertex of the upper left corner of the template chip in the template image. If the first difference is greater than the first difference threshold, the detection point is determined as an offset point, i.e., the detection point is abnormal, and it is determined as an offset point, wherein the first difference can be obtained by subtracting the standard grayscale value from the grayscale value of the detection point, and then taking the absolute value. The first difference threshold is a preset value, which can be determined according to actual conditions, and the present application does not limit this.

[0113] In step S5, the offset score value of each offset point is determined, including judging whether the first difference value of each offset point is greater than the second difference threshold value, and determining that the offset score value corresponding to the offset point whose first difference value is not greater than the second difference threshold value is a first score value, the offset score value corresponding to the offset point whose first difference value is greater than the second difference threshold value is a second score value, and the first score value is less than the second score value.

[0114] Reference Fig.11 , Fig.11 : is a flow chart of the steps included in step S5 of the chip surface defect detection method provided in an embodiment of the present application, and step S5 specifically includes the following steps:

[0115] In step S51, it is determined whether the first difference of each of the offset points is greater than a second difference threshold;

[0116] In step S521, determining that the offset score value corresponding to the offset point where the first difference value is not greater than the second difference threshold value is a first score value;

[0117] In step S522, the offset score value corresponding to the offset point where the first difference value is greater than the second difference threshold is determined as a second score value, wherein the first score value is smaller than the second score value.

[0118] Specifically, after each detection point is determined as an offset point, the offset degree of the offset point will be further judged. In this embodiment, a second difference threshold is preset, and the second difference threshold is used as a boundary. If the first difference of the offset point is less than or equal to the second difference threshold, the offset degree of the offset point is determined to be relatively light; if the first difference of the offset point is greater than the second difference threshold, the offset degree of the offset point is determined to be relatively heavy, wherein the second difference threshold should be greater than the first difference threshold. It is worth noting that if there is a single detection point whose first difference far exceeds the second difference threshold (for example, more than twice), the offset score value corresponding to the offset point can be appropriately increased according to the actual situation.

[0119] In step S6, it is determined whether the total offset score of the continuous series of offset points in the offset points reaches the edge collapse score. If the total offset score of the series of offset points reaches the edge collapse score, it is determined that the target chip has edge collapse. The total offset score is the sum of the offset score values ​​corresponding to all offset points in each series of the series of offset points.

[0120] Specifically, for the detection of each target chip, after determining multiple detection points on the binding rectangle of the target chip, a certain detection point is used as a starting point for detection one by one. If the consecutive detection points are offset points, the above-mentioned serial offset points are formed.

[0121] More specifically, when the concatenated offset points are formed, the total offset score is calculated based on the offset score corresponding to each offset point in the concatenated offset points, for example: Fig.12 As shown, Fig.12 : is a schematic diagram of the execution of step S6 in the chip surface defect detection method provided by the embodiment of the present application. For the convenience of explanation, the offset point corresponding to the first score value is represented by gray, and the offset point corresponding to the second score value is represented by black. It is assumed that there is a series of offset points 1 consisting of 3 offset points of the first score value, a series of offset points 2 consisting of 2 offset points of the second score value, and a series of offset points 3 consisting of 2 offset points of the first score value and 1 offset point of the second score value. The preset edge collapse score is 4, the first score value is 1, and the second score value is 2. In this case, the total offset score of the series offset point 1 is 3, the total offset score of the series offset point 2 is 4, and the total offset score of the series offset point 3 is 4, that is, the target chip 2 and the target chip 3 have edge collapse. After determining that the corresponding target chip has edge collapse, stop the detection of subsequent detection points and the following bad point detection, and use laser irradiation to mark, so that the subsequent relevant personnel can pick out the edge collapse chip.

[0122] In one embodiment proposed in the present application, a counter can be set, and a certain detection point is used as the starting point, and all detection points are traversed in sequence from the starting point, wherein if the detection point is an offset point and the corresponding offset score value is 1, the counter is incremented by 1, and if the next detection point is also an offset point corresponding to the first offset score value, the counter is incremented by 1, and if an offset point corresponding to the second offset score value appears, the counter is incremented by 2, and the count is gradually accumulated. It is worth noting that if the next detection point is not an offset point, the count value of the counter is obtained, that is, the above-mentioned total offset score, and if the total offset score reaches the edge collapse score, it is determined that the chip sends an edge collapse and the detection is terminated; if the total offset score does not reach the edge collapse score, the next detection point is detected and the technical value of the counter is cleared until all detection points on the target chip image are detected.

[0123] Furthermore, for chips that have been confirmed to have no edge collapse after edge analysis (such as Fig.10 The target chip 1 shown in FIG. 1 ) can also be further analyzed for the bad pixel area of ​​the target chip and processed accordingly, as described in detail below:

[0124] If there is no series offset point whose total offset score reaches the edge collapse score, determining whether a second difference between each pixel point in the target chip image and a pixel point at a corresponding position in the chip image template is greater than a third difference threshold;

[0125] Marking a plurality of pixel points that are in an adjacent relationship and whose corresponding second difference values ​​are greater than the third difference threshold as a bad pixel point group;

[0126] Determine whether the number of pixels in the bad pixel group exceeds a bad pixel threshold;

[0127] If the number of pixels in the bad pixel group exceeds the bad pixel threshold, a corresponding area of ​​the pixel group on the target chip is determined to be a bad pixel.

[0128] Specifically, the overall difference between the target chip image and the chip image template is compared, that is, the target chip and the template chip images are compared as a whole, and whether there is a bad pixel in the target chip is determined based on the comparison result.

[0129] First, determine whether the second difference between each pixel in the target chip image and the pixel at the corresponding position in the chip image template is greater than the third difference threshold. For example, the grayscale value of each pixel in the target chip image can be subtracted from the grayscale value of the pixel at the corresponding position in the chip image template, and the absolute value of the difference can be taken to obtain the second difference, and then determine whether the second difference is greater than the third difference threshold.

[0130] Next, a plurality of pixels in the target chip image that are in an adjacent relationship and whose difference values ​​are greater than a third difference threshold are marked as a bad pixel group.

[0131] Finally, if the number of pixels in the bad pixel group is greater than the bad pixel threshold, the area on the target chip corresponding to the bad pixel group is determined as a bad pixel.

[0132] It can be understood that the bad pixel of the chip is manifested in the image as one or more groups of adjacent pixel points with abnormalities. Therefore, in this embodiment, it is first determined whether the second difference corresponding to each pixel point in the target chip image is greater than the third difference threshold. If it is greater than the third difference threshold, it is considered that the pixel point is abnormal, and the adjacent abnormal pixel points are marked as bad pixel groups; the presence of abnormalities in a small number of pixel points often does not mean that there are bad pixels on the chip. It may be due to detection errors, image equipment, etc. that a small number of pixel points are abnormal. Therefore, this application also determines the number of pixel groups in the bad pixel group. If the number is greater than the bad pixel threshold, the area on the target chip corresponding to the bad pixel group is determined as a bad pixel. Among them, the third difference threshold and the bad pixel threshold can be determined according to actual conditions, and this application does not limit this.

[0133] Furthermore, after the bad pixel is determined, the image area corresponding to the bad pixel position can be determined on the image, so as to control the relevant laser to perform laser burning on one or more bad pixels. The following is a specific description of this step:

[0134] According to the number of pixels corresponding to the bad pixel, adjusting the laser parameters for laser burning the corresponding position of the bad pixel to obtain the corresponding laser irradiation mode;

[0135] The laser irradiation mode is adopted to perform laser burning on the corresponding position of the bad spot.

[0136] Specifically, the more pixels there are in the bad pixel group, the larger the corresponding bad pixel area is, and a higher preset laser power, a longer preset irradiation time and a larger preset light spot can be used; the fewer pixels there are in the bad pixel group, the smaller the corresponding bad pixel area is, and a lower preset laser power, a shorter preset irradiation time and a smaller preset light spot can be used.

[0137] More specifically, when the area of ​​the bad pixel is large, a laser with a larger spot size can be used for pulses. However, this method is not applicable when the target chip spacing is small. The high temperature of the laser is likely to cause damage to the surrounding ICs. Therefore, the laser power, pulse time and spot size can be adjusted according to the target chip spacing to adapt to the bad pixel pulse requirements of products of various specifications. The laser adjustment can also be preset into the laser irradiation mode and adaptively called in actual use. Each laser irradiation module can correspond to different laser powers, irradiation times and spot sizes.

[0138] In the second aspect of the present application, a chip surface defect detection device is disclosed. Fig.13 , Fig.13 : is a virtual structural diagram of a chip surface defect detection device provided by the present application, and the chip surface defect detection device comprises:

[0139] An image acquisition module 100 acquires an image of a detection area including a target chip;

[0140] A rectangle matching module 200 matches a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image;

[0141] A detection point determination module 300, which determines a plurality of detection points on the detection area image according to the binding rectangle;

[0142] The offset point judgment module 400 continuously detects the detection points, including judging whether a first difference between a grayscale value corresponding to each detection point and a standard grayscale value is greater than a first difference threshold, and determining the detection point whose first difference is greater than the first difference threshold as an offset point, wherein the standard grayscale value is a grayscale value of a pixel corresponding to each detection point in a binding rectangle of the chip image template;

[0143] an offset score determination module 500, configured to determine an offset score value of each offset point, including determining whether the first difference value of each offset point is greater than a second difference threshold, and determining that an offset score value corresponding to an offset point whose first difference value is not greater than the second difference threshold is a first score value, an offset score value corresponding to an offset point whose first difference value is greater than the second difference threshold is a second score value, and the first score value is less than the second score value;

[0144] The chipping edge determination module 600 determines whether the total offset score of the consecutively connected offset points in the offset points reaches the chipping edge score. If the total offset score of the consecutively connected offset points reaches the chipping edge score, it is determined that the target chip has chipping edge. The total offset score is the sum of the offset score values ​​corresponding to all the offset points in each series of the consecutively connected offset points.

[0145] Furthermore, the rectangle matching module 200 further includes:

[0146] An image matching submodule, used to perform image matching on the detection area image according to the chip image template to obtain a binding rectangle corresponding to one or more target chips;

[0147] The image extraction submodule is used to determine the target chip image of each target chip in the detection area image according to the binding rectangle of each target chip.

[0148] The image matching submodule also includes:

[0149] A pyramid construction unit, configured to construct a pyramid image based on the detection area image, including taking the original image of the detection area image as the bottom layer of the pyramid image, and obtaining the pyramid image with a gradually decreasing resolution from the bottom layer to the upper layer through continuous downsampling;

[0150] A normalization unit, used for performing normalization calculation on each layer of the pyramid image to obtain a normalization index corresponding to each layer of the image;

[0151] A rectangle matching unit is used to match the binding rectangle of each target chip in the detection area image according to the normalized index corresponding to each layer of the image.

[0152] For the specific definition of the chip surface defect detection device, please refer to the definition of the chip surface defect detection method above, which will not be repeated here. Each module in the above-mentioned chip surface defect detection device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0153] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0154] The surface defect detection method of a chip provided in an embodiment of the present application can be applied to terminal devices such as electronic devices, computers, wearable devices, vehicle-mounted devices, tablet computers, laptop computers, netbooks, personal digital assistants (PDA), augmented reality (AR) / virtual reality (VR) devices, mobile phones, etc. The embodiment of the present application does not impose any restrictions on the specific type of terminal devices.

[0155] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in each embodiment of the above method can be implemented.

[0156] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in each embodiment of the above method when executing the computer program product.

[0157] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0158] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0159] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0160] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0161] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0162] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A chip surface defect detection method, characterized in that: The following steps are involved: S1, acquiring an image of a detection area including a target chip; S2, matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image; S3, determining a plurality of detection points on the detection area image according to the binding rectangle; S4, continuously detecting the detection points, including determining whether a first difference between a grayscale value corresponding to each detection point and a standard grayscale value is greater than a first difference threshold, and determining the detection point whose first difference is greater than the first difference threshold as an offset point, wherein the standard grayscale value is a grayscale value of a pixel corresponding to each detection point in a binding rectangle of the chip image template; S5, determining the offset score value of each offset point, including judging whether the first difference value of each offset point is greater than a second difference threshold value, and determining that the offset score value corresponding to the offset point whose first difference value is not greater than the second difference threshold value is a first score value, the offset score value corresponding to the offset point whose first difference value is greater than the second difference threshold value is a second score value, and the first score value is less than the second score value; S6, judging whether the total offset score of the offset points formed by the continuous series of offset points in the offset points reaches the edge collapse score, if the total offset score of the offset points formed by the series of offset points reaches the edge collapse score, then determining that the target chip has edge collapse, the total offset score is the sum of the offset score values ​​corresponding to all the offset points in each series of the offset points connected in series; After the step S6 of determining whether the total offset score of the offset points formed by the continuous series of offset points has reached the edge collapse score, for the chip confirmed to have no edge collapse after the edge analysis test, further bad pixel area analysis is performed on the target chip and corresponding processing is performed, including: If there is no series offset point whose total offset score reaches the edge collapse score, determining whether a second difference between each pixel point in the target chip image and a pixel point at a corresponding position in the chip image template is greater than a third difference threshold; Marking a plurality of pixel points that are in an adjacent relationship and whose corresponding second difference values ​​are greater than the third difference threshold as a bad pixel point group; Determine whether the number of pixels in the bad pixel group exceeds a bad pixel threshold; If the number of pixels in the bad pixel group exceeds the bad pixel threshold, a corresponding area of ​​the pixel group on the target chip is determined to be a bad pixel.

2. The chip surface defect detection method according to claim 1, characterized in that: The step S2 of matching the binding rectangle of the target chip in the detection area image according to the chip image template corresponding to the target chip in the detection area image comprises: According to the chip image template, image matching is performed on the detection area image to obtain binding rectangles corresponding to one or more target chips; According to the binding rectangle of each of the target chips, a target chip image of each of the target chips in the detection area image is determined.

3. The chip surface defect detection method according to claim 2, characterized in that: The step of performing image matching on the detection area image according to the chip image template comprises: Constructing a pyramid image based on the detection area image, including using the original image of the detection area image as the bottom layer of the pyramid image, and obtaining the pyramid image with a gradually decreasing resolution from the bottom layer to the upper layer through continuous downsampling; Performing normalization calculation on each layer of the pyramid image to obtain a normalization index corresponding to each layer of the image; According to the normalized index corresponding to each layer of the image, a binding rectangle of each target chip is matched in the detection area image.

4. The chip surface defect detection method according to claim 2, characterized in that: The step S3 of determining a plurality of detection points on the detection area image according to the binding rectangle comprises: According to the rotation angle of the chip image template, the rotation angle of each target chip image is adjusted so that the rotation angle of each target chip image is consistent with the rotation angle of the chip image template.

5. The chip surface defect detection method according to claim 1, characterized in that: After the step of determining that a corresponding area of ​​the pixel group on the target chip is a bad pixel if the pixels in the bad pixel group exceed the bad pixel threshold, the method further includes: According to the number of pixels corresponding to the bad pixel, adjusting the laser parameters for laser burning the corresponding position of the bad pixel to obtain the corresponding laser irradiation mode; The laser irradiation mode is adopted to perform laser burning on the corresponding position of the bad spot.

6. The chip surface defect detection method according to claim 1, characterized in that: The step S2 of matching the binding rectangle of the target chip in the detection area image according to the chip image template corresponding to the target chip in the detection area image comprises: Extracting target features of the chip image template; According to the target features, positioning and matching are performed in the detection area image to determine the binding rectangles corresponding to one or more target chips.

7. A chip surface defect detection device, characterized in that: The device is used to implement a chip surface defect detection method as claimed in claim 1, comprising: An image acquisition module, which acquires an image of the detection area including the target chip; a rectangle matching module, matching a binding rectangle of the target chip in the detection area image according to a chip image template corresponding to the target chip in the detection area image; A detection point determination module, which determines a plurality of detection points on the detection area image according to the binding rectangle; An offset point judgment module is used to continuously detect the detection points, including judging whether a first difference between a grayscale value corresponding to each detection point and a standard grayscale value is greater than a first difference threshold, and determining that the detection point whose first difference is greater than the first difference threshold is an offset point, wherein the standard grayscale value is a grayscale value of a pixel corresponding to each detection point in a binding rectangle of the chip image template; an offset score determination module, configured to determine an offset score value of each of the offset points, including determining whether the first difference value of each of the offset points is greater than a second difference threshold, and determining that an offset score value corresponding to an offset point whose first difference value is not greater than the second difference threshold is a first score value, an offset score value corresponding to an offset point whose first difference value is greater than the second difference threshold is a second score value, and the first score value is less than the second score value; The chipping determination module determines whether the total offset score of the consecutively connected offset points in the offset points reaches the chipping score. If the total offset score of the consecutively connected offset points reaches the chipping score, it is determined that the target chip has chipping. The total offset score is the sum of the offset score values ​​corresponding to all the offset points in each series of the consecutively connected offset points.

8. The chip surface defect detection device according to claim 7, characterized in that: The rectangular matching module also includes: An image matching submodule, used to perform image matching on the detection area image according to the chip image template to obtain a binding rectangle corresponding to one or more target chips; The image extraction submodule is used to determine the target chip image of each target chip in the detection area image according to the binding rectangle of each target chip. The image matching submodule also includes: A pyramid construction unit, configured to construct a pyramid image based on the detection area image, including taking the original image of the detection area image as the bottom layer of the pyramid image, and obtaining the pyramid image with a gradually decreasing resolution from the bottom layer to the upper layer through continuous downsampling; A normalization unit, used for performing normalization calculation on each layer of the pyramid image to obtain a normalization index corresponding to each layer of the image; A rectangle matching unit is used to match the binding rectangle of each target chip in the detection area image according to the normalized index corresponding to each layer of the image.

9. A storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute a chip surface defect detection method as claimed in any one of claims 1 to 6.

Images