Semiconductor device and method for manufacturing the same

Abstract

An embodiment of the present disclosure discloses a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device may include: providing a silicon carbide body, the silicon carbide body including a first surface and a second surface arranged opposite to the first surface; forming a gate trench extending from the first surface of the silicon carbide body into the silicon carbide body, the gate trench including a sidewall and a bottom; forming a body region and a source region, the body region and the source region contacting the sidewall and / or bottom of the gate trench, and the body region is located between the source region and the silicon carbide body; forming a shielding region extending into the silicon carbide body on both sides of the gate trench, the shielding region being spaced apart from the gate trench, and the bottom of the shielding region being closer to the second surface than the bottom of the gate trench.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Power devices play a vital role in power supply, power processing and other systems. Compared with silicon (Si) materials, wide bandgap semiconductors usually exhibit advantages such as high frequency, high power density, high breakdown voltage and strong radiation resistance due to their larger bandgap width. Among these wide bandgap semiconductors, silicon carbide (SiC) materials stand out for their high critical breakdown electric field, high thermal conductivity and high saturation electron drift velocity. Compared with the widely used silicon (Si) insulated gate bipolar transistor (IGBT), SiC metal-oxide-semiconductor field-effect transistor (MOSFET) exhibits lower switching losses and higher operating frequencies due to its unipolar conductivity and high saturation electron drift velocity.

[0003] In particular, trench gate SiC MOSFETs are valued for their improved electrical properties, including high cell density, low conduction loss, and excellent switching performance. However, trench gate technology is limited by current process levels and gate oxide layer reliability issues. Specifically, the electric field concentration at the bottom of the gate trench often leads to low long-term reliability of power devices. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure are intended to provide a semiconductor device and a method for manufacturing the same, which can solve the problem of low long-term reliability of power devices caused by electric field concentration at the bottom of the gate trench.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a silicon carbide body, the silicon carbide body comprising a first surface and a second surface disposed opposite to the first surface;

[0008] forming a gate trench extending from a first surface of the silicon carbide body into the silicon carbide body, the gate trench comprising sidewalls and a bottom;

[0009] forming a body region and a source region, wherein the body region and the source region are in contact with the sidewall and / or the bottom of the gate trench, and the body region is located between the source region and the silicon carbide body;

[0010] A shielding region extending into the silicon carbide body is formed on both sides of the gate trench, the shielding region is spaced apart from the gate trench, and the bottom of the shielding region is closer to the second surface than the bottom of the gate trench.

[0011] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0012] A silicon carbide body, the silicon carbide body comprising a first surface and a second surface arranged opposite to the first surface;

[0013] a gate trench extending from the first surface of the silicon carbide body into the silicon carbide body, the gate trench comprising a sidewall and a bottom;

[0014] A body region and a source region, contacting the sidewall and / or the bottom of the gate trench, and the body region is located between the source region and the silicon carbide body;

[0015] The shielding region is arranged at both sides of the gate trench and extends into the silicon carbide body, and the bottom of the shielding region is closer to the second surface than the bottom of the gate trench.

[0016] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same; by forming a shielding region extending from the source region to the silicon carbide body on both sides of the gate trench, and by configuring the bottom of the shielding region to be closer to the second surface than the bottom of the gate trench, the originally concentrated electric field can be dispersed to a wider area, and by optimizing the current path, the concentration of current in a specific area is reduced, thereby reducing the electric field concentration and improving the long-term reliability of the manufactured semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.

[0018] Figure 2 A schematic vertical cross-sectional view of a silicon carbide body provided in an embodiment of the present disclosure.

[0019] Figure 3 A schematic vertical cross-sectional view of a semiconductor device after a gate trench is formed according to an embodiment of the present disclosure.

[0020] Figure 4 A vertical cross-sectional schematic diagram of a semiconductor device after a body region and a source region are formed according to an embodiment of the present disclosure.

[0021] Figure 5 A vertical cross-sectional schematic diagram of a semiconductor device after a shielding region is formed according to an embodiment of the present disclosure.

[0022] Figure 6 A vertical cross-sectional schematic diagram of a semiconductor device in which a shielding region is formed in a first contact trench according to an embodiment of the present disclosure.

[0023] Figure 7 A vertical cross-sectional schematic diagram of a semiconductor device in which a shielding region is formed in a second contact trench according to an embodiment of the present disclosure.

[0024] Figure 8 A vertical cross-sectional schematic diagram of a semiconductor device in which first contact trenches are formed on both sides of a gate trench is provided according to an embodiment of the present disclosure.

[0025] Fig. 9 A vertical cross-sectional schematic diagram of a semiconductor device in which second contact trenches are formed on both sides of a gate trench is provided according to an embodiment of the present disclosure.

[0026] Fig.10 A vertical cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure, in which a first contact trench and a second contact trench are respectively formed on both sides of a gate trench.

[0027] Fig.11 A vertical cross-sectional schematic diagram of a semiconductor device including two gate trenches provided in an embodiment of the present disclosure.

[0028] Fig.12 A vertical cross-sectional schematic diagram of a semiconductor device after a source region is formed when two gate trenches are included according to an embodiment of the present disclosure.

[0029] Fig.13 A vertical cross-sectional schematic diagram of a semiconductor device after forming a source region and a body region when two gate trenches are included according to an embodiment of the present disclosure is provided.

[0030] Fig.14 A vertical cross-sectional schematic diagram of a semiconductor device including two gate trenches after a shielding region is formed according to an embodiment of the present disclosure.

[0031] Fig.15 A vertical cross-sectional schematic diagram of another semiconductor device after forming a source region when two gate trenches are included according to an embodiment of the present disclosure is provided.

[0032] Fig.16 A vertical cross-sectional schematic diagram of another semiconductor device after forming a source region and a body region when two gate trenches are included according to an embodiment of the present disclosure is provided.

[0033] Fig.17 A vertical cross-sectional schematic diagram of another semiconductor device including two gate trenches after a shielding region is formed according to an embodiment of the present disclosure.

[0034] Fig.18 A vertical cross-sectional schematic diagram of a semiconductor device after forming a gate dielectric is provided according to an embodiment of the present disclosure.

[0035] Fig.19 A vertical cross-sectional schematic diagram of a semiconductor device after a conductive gate electrode is formed according to an embodiment of the present disclosure.

[0036] Fig. 20 A vertical cross-sectional schematic diagram of a semiconductor device after etching and removing a gate dielectric provided in an embodiment of the present disclosure.

[0037] Fig.21 A schematic vertical cross-sectional view of a semiconductor device after a gate insulating layer is formed according to an embodiment of the present disclosure.

[0038] Fig. 22 A schematic vertical cross-sectional view of a semiconductor device after a source metal layer is formed according to an embodiment of the present disclosure.

[0039] Fig.23 A vertical cross-sectional schematic diagram of a semiconductor device provided with a substrate according to an embodiment of the present disclosure.

[0040] Fig.24 A vertical cross-sectional schematic diagram of a semiconductor device after a drain metal layer is formed according to an embodiment of the present disclosure.

[0041] Description of reference numerals:

[0042] 1. Silicon carbide body; 11. Gate trench; 111. First gate trench; 112. Second gate trench; 12. Body region; 13. Source region; 14. Shielding region; 151. First contact trench; 152. Second contact trench; 1A. First surface; 1B. Second surface; 2. Gate structure; 21. Gate dielectric; 22. Conductive gate electrode; 3. Gate insulation layer; 4. Source metal layer; 5. Silicon carbide substrate; 6. Drain metal layer.

[0043] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0044] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which specific embodiments in which silicon carbide devices can be practiced are shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used on other embodiments or used in combination with other embodiments to produce yet another embodiment. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. If not otherwise stated, corresponding elements in different drawings are represented by the same reference symbols.

[0045] The terms "having", "comprising", "including", and "comprising" and the like are open ended, and the terms indicate the presence of stated structures, elements, or features but do not exclude the presence of additional elements or features. The quantifiers and pronouns "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0046] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations. Two adjacent doping regions of the same conductivity type and having different dopant concentrations form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doping regions. At a unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa.

[0047] The main components of a layer or structure from a chemical composition or alloy are the elements whose atoms form the chemical composition or alloy. For example, nickel and silicon are the main components of a nickel silicide layer, and copper and aluminum are the main components of a copper-aluminum alloy.

[0048] The gate trench MOSFET is a newer device structure. Compared with the traditional planar MOSFET, the gate trench design changes the conductive channel from the horizontal direction to the vertical direction, effectively reducing the cell size, reducing the on-resistance, and eliminating the junction field-effect transistor (JFET) effect. However, trench gate technology is limited by the current process level and the reliability of the gate oxide layer. Specifically, the electric field concentration at the bottom of the gate trench causes the long-term reliability of semiconductor devices to be low.

[0049] The JFET effect refers to the phenomenon that in some MOSFET (metal-oxide-semiconductor field-effect transistor) structures, the conductive channel becomes narrower at high voltage due to the channel length modulation effect, thereby increasing the on-resistance. This phenomenon is particularly significant under high current or high voltage conditions, which will reduce the performance and efficiency of the device.

[0050] Based on this, the present disclosure first provides a method for manufacturing a semiconductor device. Figure 1 A flowchart of a method for manufacturing a semiconductor device is shown. The method for manufacturing a semiconductor device may include steps S110 to S140.

[0051] In step S110 , a silicon carbide body is provided, wherein the silicon carbide body includes a first surface and a second surface disposed opposite to the first surface.

[0052] In some of the disclosed examples, reference Figure 2 First, a silicon carbide body 1 may be provided. By way of example, the silicon carbide body 1 may be of the polytype 15R-SiC, 2H-SiC, 4H-SiC or 6H-SiC. In addition to the main components silicon and carbon, the silicon carbide body 1 may also include dopant atoms, such as nitrogen N, phosphorus P, beryllium Be, boron B, aluminum Al and / or gallium Ga. Further, the silicon carbide body 1 may include unwanted impurities, such as hydrogen and / or oxygen. The silicon carbide body 1 may include a first surface 1A at the front side and an opposite second surface 1B at the back side.

[0053] It should be noted that the conductivity type of the silicon carbide body 1 may be a first conductivity type, and the first conductivity type may be an n-type or a p-type. Here and below, the conductivity type of the silicon carbide body 1 is named as the first conductivity type.

[0054] It should be noted that the first conductivity type and the second conductivity type in the present disclosure are used to distinguish between n-type and p-type. When the first conductivity type is n-type, the second conductivity type is p-type. When the first conductivity type is p-type, the second conductivity type is n-type.

[0055] In step S120 , a gate trench extending from the first surface of the silicon carbide body into the silicon carbide body is formed, wherein the gate trench includes a sidewall and a bottom.

[0056] In an exemplary embodiment of the present disclosure, referring to Figure 3 A trench extending from the first surface 1A into the silicon carbide body 1 may be formed on the silicon carbide body 1 . A gate structure may be formed in the trench in a subsequent process. The trench is named a gate trench 11 to distinguish it from other trench structures.

[0057] Specifically, when forming the gate trench 11, a mask etching process can be used to etch the gate trench 11 on the silicon carbide body 1, and the formed gate trench 11 has sidewalls and a bottom. The specific position of the gate trench 11 can be customized based on user needs and will not be described in detail in this exemplary embodiment.

[0058] In step S130 , a body region and a source region are formed, wherein the body region and the source region are in contact with the sidewall and / or the bottom of the gate trench, and the body region is located between the source region and the silicon carbide body.

[0059] In some example embodiments of the present disclosure, reference is made to Figure 4 , a body region 12 and a source region 13 may be formed on the silicon carbide body 1, wherein the body region 12 may be first formed on the silicon carbide body 1, and then the source region 13 may be formed between the body region 12 and the first surface 1A. The body region 12 and the source region 13 are oppositely doped and form a pn junction. The conductivity type of the source region 13 is the first conductivity type, and the conductivity type of the body region 12 is the second conductivity type.

[0060] In some examples, the body region 12 is located between the source region 13 and the silicon carbide body 1 , and the body region 12 and the source region 13 are in contact with the sidewall and / or bottom of the gate trench 11 .

[0061] The body region 12 contacts the sidewall of the gate trench 11, the source region 13 contacts the sidewall of the gate trench 11, and the source region 13 is located between the body region 12 and the first surface 1A. The conductivity type of the body region 12 is the second conductivity type, and the conductivity type of the source region 13 is the first conductivity type.

[0062] Specifically, when the second conductivity type is p-type, a p-type body region mask may be firstly manufactured by using a photolithography process, and then p-type impurity aluminum may be implanted based on the p-type body region mask to form the p-type body region 12 .

[0063] In step S140 , shielding regions extending into the silicon carbide body are formed on both sides of the gate trench, the shielding regions are spaced apart from the gate trench, and the bottom of the shielding regions is closer to the second surface than the bottom of the gate trench.

[0064] In an exemplary embodiment of the present disclosure, referring to Figure 5 After the gate trench 11 is generated, a shielding region 14 extending into the silicon carbide body 1 can be formed on both sides of the gate trench 11, the shielding region 14 is spaced apart from the gate trench 11, and the bottom of the shielding region 14 is closer to the second surface 1B than the bottom of the gate trench 11, wherein the conductivity type of the shielding region 14 is the second conductivity type, and specifically, when the second conductivity type is p-type, a p-type body region mask plate can be firstly made by photolithography, and then p-type impurity aluminum is implanted based on the p-type body region mask plate to form a p-type shielding region 14. The doping concentration of the shielding region 14 is greater than the doping concentration of the body region 12.

[0065] The manufacturing method of the semiconductor device provided by the embodiment of the present disclosure can disperse the originally concentrated electric field to a wider area by forming a shielding area 14 extending into the silicon carbide body 1 on both sides of the gate trench 11, and based on the setting that the bottom of the shielding area 14 is closer to the second surface 1B than the bottom of the gate trench 11. By optimizing the current path, the concentration of current in a specific area is reduced, thereby reducing the electric field concentration and improving the long-term reliability of the manufactured semiconductor device.

[0066] In some examples, before forming the source region 13 and the body region 12, a contact trench extending from the first surface 1A to the silicon carbide body 1 can be formed on at least one side of the gate trench 11, and the shielding region 14 can extend from the bottom of the contact trench to the silicon carbide body 1. The formation of the contact trench can reduce the difficulty in forming the shielding region 14. Specifically, the contact trench can make the bottom of the shielding region 14 easier to be closer to the second surface 1B than the bottom of the gate trench 11.

[0067] Specifically, the contact groove may include a first contact groove 151 and a second contact groove 152, wherein when the contact groove is the first contact groove 151, refer to Figure 6 After forming the first contact trench 151, a body region 12 and a source region 13 may be formed at the bottom of the contact trench, and the shielding region 14 may extend from the source region 13 and penetrate the body region 12 into the silicon carbide body 1. Figure 7 When the contact trench is the second contact trench 152 , the source region 13 and the body region 12 are not formed at the bottom of the second contact trench 152 , and the shielding region 14 extends directly from the bottom of the second contact trench 152 into the silicon carbide body 1 .

[0068] Optional, see Figure 8 , contact trenches may be provided on both sides of the gate trench 11, and both may be first gate trenches 111, referring to Fig. 9, the grooves on both sides may also be second contact grooves 152, referring to Fig.10 The grooves on both sides may also be the first contact groove 151 and the second contact groove 152 respectively, which is not specifically limited in this example.

[0069] In some examples, the number of gate trenches 11 can be multiple, such as two, three, four, etc. When the number of the above-mentioned gate trenches 11 is multiple, a first contact trench 151 can be set between the above-mentioned two adjacent gate trenches 11, and a shielding area 14 can be formed in the first contact trench 151. The adjacent gate trenches 11 share a shielding area 14 in the first contact trench 151.

[0070] In some examples, when multiple second contact grooves 152 are included, the distances between the bottoms of the multiple second contact grooves 152 and the second surface 1B may not be completely the same. For example, if three second contact grooves 152 are included, the distances between the bottoms of two of the contact grooves and the second surface 1B may be the same, but the distance between the bottom of the remaining second contact groove 152 and the second surface 1B may be different from the other two. Alternatively, the distances between the bottoms of the three second contact grooves 152 and the second surface 1B are all different.

[0071] The following is a detailed description assuming that the number of the gate trenches 11 is two, the number of the first contact trench 151 is one, and the number of the second contact trenches 152 is two.

[0072] Reference Fig.11 The first contact trench 151 is arranged between the two gate trenches 11. The two gate trenches 11 may include a first gate trench 111 and a second gate trench 112. The first contact trench 151 shortens the adjacent side walls of the two gate trenches 11 so that the first contact trench 151 only includes the bottom but not the side walls. That is, the first contact trench 151 makes the above-mentioned first gate trench 111 and the second gate trench 112 connected through the first contact trench 151.

[0073] The distance between the bottom of the second contact trench 152 adjacent to the first gate trench 111 and the second surface 1B is smaller than the distance between the bottom of the second contact trench 152 adjacent to the second gate trench 112 and the second surface 1B.

[0074] In this example, the first gate trench 111, the second gate trench 112, and the second contact trench 152 adjacent to the second gate trench 112 have the same depth and can be formed in one process. The first contact trench 151 and the second contact trench 152 adjacent to the first gate trench 111 can have the same depth and can be formed in one process.

[0075] After forming the gate trench 11 and the contact trench, the body region 12 and the source region 13 may be formed. Specifically, the source region 13 may be formed first, and the source region 13 may be formed at the first surface 1A and the bottom of the first contact trench 151 .

[0076] In the first example, refer to Fig.12 , the source region 13 at the bottom of the first contact trench 151 can be only disposed at the bottom of the first contact trench 151, and then the body region 12 is formed. After the body region 12 is formed, refer to Fig.13 , the body region 12 is located between the source region 13 and the silicon carbide body 1 .

[0077] In this example, after forming the body region 12 and the source region 13, referring to Fig.14 , a shielding region 14 can be formed, wherein the shielding region 14 can be divided into three parts, wherein the first partial shielding region 14 includes a shielding region 14 extending from the source region 13 formed from the first surface 1A adjacent to the first gate trench 111 to the silicon carbide body 1, and a shielding region 14 extending from the second contact trench 152 adjacent to the first gate trench 111 to the silicon carbide body 1.

[0078] The second partial shielding region 14 includes the body region 12 formed from the source region 13 in the first contact trench 151 through the bottom of the first contact trench 151 and extending into the shielding region 14 in the silicon carbide body 1 .

[0079] The third partial shielding region 14 includes a shielding region 14 extending from the source region 13 formed from the first surface 1A adjacent to the second gate trench 112 to the silicon carbide body 1 , and a shielding region 14 extending from the bottom of the second contact trench 152 adjacent to the second gate trench 112 to the silicon carbide body 1 .

[0080] In the second example, refer to Fig.15 The source region 13 at the bottom of the first contact trench 151 can extend from the bottom of the first contact trench 151 to the silicon carbide body 1 and at least partially cover the bottom of the first gate trench 111. Optionally, it can also at least cover the bottom of the second gate trench 112 (not shown). Then, the body region 12 is formed. Fig.16 After the body region 12 is formed, the body region 12 also extends into the silicon carbide body 1 and contacts the bottom of the first gate trench 111 .

[0081] When the source region 13 covers the bottom of the second gate trench 112 , the body region 12 also contacts the bottom of the second gate trench 112 .

[0082] In this example, after forming the body region 12 and the source region 13, referring to Fig.17, a shielding region 14 can be formed, wherein the shielding region 14 can be divided into three parts, wherein the first partial shielding region 14 includes a shielding region 14 extending from the source region 13 formed from the first surface 1A adjacent to the first gate trench 111 to the silicon carbide body 1, and a shielding region 14 extending from the second contact trench 152 adjacent to the first gate trench 111 to the silicon carbide body 1.

[0083] The second partial shielding region 14 includes the shielding region 14 starting from the source region 13 in the first contact trench 151 , penetrating the body region 12 in the first contact trench 151 , and extending into the silicon carbide body 1 .

[0084] The third partial shielding region 14 includes a shielding region 14 extending from the source region 13 formed from the first surface 1A adjacent to the second gate trench 112 to the silicon carbide body 1 , and a shielding region 14 extending from the bottom of the second contact trench 152 adjacent to the second gate trench 112 to the silicon carbide body 1 .

[0085] It should be noted that the first partial shielding area 14 and the third partial shielding area 14 are formed by a single process. Fig.14 and 17 As shown, the formed first partial shielding area 14 and the third partial shielding area 14 will include a stepped structure. At the same time, the depth of the second contact groove 152 adjacent to the second gate groove 112 is relatively large. Therefore, the third partial shielding area 14 will also form a stepped structure with the first partial shielding area 14 and the second partial shielding area 14. The shielding area 14 with a stepped structure can achieve charge balance and reduce electric field concentration by adjusting the charge distribution. The stepped shielding area 14 reduces the electric field gradient by increasing the path length of the electric field, thereby reducing the possibility of electric field concentration.

[0086] It should be noted that the specific position and specific depth of the shielding area 14 can also be customized based on user needs, which will not be described in detail in this example implementation.

[0087] In some examples, after forming the shielding region 14, a gate structure 2 can be formed in the above-mentioned gate trench 11, and the gate structure 2 can include a conductive gate electrode 22 of a first conductive type and a gate dielectric 21 at least between the body region 12 and the conductive gate electrode 22, and the conductive gate electrode 22 is used to wrap the conductive gate electrode 22 (such as a polysilicon gate), and the gate dielectric 21 contacts the sidewall of the gate trench 11.

[0088] It should be noted that when forming the shielding region 14 , high temperature ion implantation of p-type impurities, such as B, Al elements, etc., may be used to form the shielding region 14 .

[0089] Specifically, refer to Fig.18 After the shielding region 14 is formed, a gate dielectric 21 may be formed, and the gate dielectric 21 may be grown on the bottom of the first contact trench 151, the first surface 1A, the sidewall and bottom of the second contact trench 152, and the sidewall and bottom of the gate trench 11. The gate dielectric 21 may be made of a gate oxide such as silicon dioxide.

[0090] It should be noted that after the formation of the above-mentioned shielding area 14 is completed, that is, after the ion implantation is completed, carbon film sputtering can be performed, and then annealing is performed at 1700~1800℃ for 5~30min, and then the carbon film is removed, and the sacrificial oxide layer is grown and removed to obtain a high-quality SiC surface, and finally the gate dielectric 21 is grown by a high-temperature oxidation process.

[0091] After the gate dielectric 21 is formed, refer to Fig.19 , a conductive gate electrode 22 can be formed by dry etching. The conductive gate electrode 22 is formed in the above-mentioned gate trench 11 and is at least partially covered by the above-mentioned gate dielectric 21, so that the above-mentioned conductive gate electrode 22 does not contact the source region 13, the body region 12 and the silicon carbide body 1.

[0092] After forming the conductive gate electrode 22, refer to Fig. 20 The gate dielectric 21 of the second contact groove 152 can be etched away, and the gate dielectric 21 of the first plane can be etched away to at least expose a portion of the source region 13. Similarly, the gate dielectric 21 in the first contact groove 151 can be etched away to at least expose a portion of the source region 13 to form an ohmic contact with the subsequently generated source metal layer 4.

[0093] After the etching and removal of the gate dielectric 21 is completed, refer to Fig.21 , a gate insulating layer 3 can be formed, and the gate insulating layer 3 covers the gate structure 2 to prevent an electrical short circuit between the conductive gate electrode 22 and the source metal layer 4 after the source metal layer 4 is generated. The gate insulating layer 3 can be formed by chemical vapor deposition, and the specific formation method is not repeated in this example.

[0094] After forming the gate insulating layer 3, refer to Fig. 22 The source metal layer 4 can be deposited on the bottom of the first contact trench 151, the bottom and sidewall of the second contact trench 152, the first surface 1A, and the side of the gate insulating layer 3 away from the gate structure 2 by metal deposition. Ohmic contacts are formed between the source region 13 and the shielding region 14 and the source metal layer 4.

[0095] In some examples, reference Figure 1 and Fig.23Before providing the silicon carbide body 1, a silicon carbide substrate 5 may be provided first. The conductivity type of the silicon carbide substrate 5 is the same as that of the silicon carbide body 1, but the doping concentration of the silicon carbide substrate 5 is higher than that of the silicon carbide body 1. The silicon carbide body 1 is formed on one side of the silicon carbide substrate 5, that is, the second surface 1B of the silicon carbide body 1 is in contact with the silicon carbide substrate 5.

[0096] It should be noted that when the silicon carbide body 1 is formed, the silicon carbide body 1 is formed on the silicon carbide substrate 5 by depositing a silicon carbide epitaxial layer.

[0097] After the source metal layer 4 is formed, refer to Fig.24 A drain metal layer 6 may be formed on a side of the silicon carbide substrate 5 away from the silicon carbide body 1 in the aforementioned example to form a MOS tube.

[0098] The manufacturing method of the semiconductor device provided by the embodiment of the present disclosure, on the one hand, by forming a shielding area 14 on both sides of the gate groove 11, and designing the bottom of the shielding area 14 to be closer to the second surface 1B of the silicon carbide body 1, the originally concentrated electric field can be dispersed to a wider area. This design helps to reduce the problem of electric field concentration at the bottom of the gate groove 11, thereby improving the long-term reliability of the semiconductor device. On the other hand, through the design of the shielding area 14, the flow path of the current can be optimized, the concentration of the current in a specific area can be reduced, and the risk of electric field concentration can be further reduced. Due to the reduction of electric field concentration and the optimization of the current path, the overall performance of the semiconductor device is improved, including but not limited to the reduction of switching losses and the increase of operating frequency. On the other hand, by extending the source region 13 and the body region 12 at the bottom of the first contact groove 151 to the bottom of the first gate groove 111, the channel density can be increased, the conduction pad can be further reduced, and the conduction loss can be reduced.

[0099] Furthermore, the present disclosure also provides a semiconductor device, referring to Figure 1 and Figure 5 The semiconductor device may include a silicon carbide body 1, a gate trench 11, a body region 12, a source region 13 and a shielding region 14, wherein the silicon carbide body 1 includes a first surface 1A and a second surface 1B arranged opposite to the first surface 1A; the gate trench 11 extends from the first surface 1A of the silicon carbide body 1 into the silicon carbide body 1, and the gate trench 11 includes a sidewall and a bottom; the body region 12 and the source region 13 are in contact with the sidewall and / or the bottom of the gate trench 11, and the body region 12 is located between the source region 13 and the silicon carbide body 1; the shielding region 14 is arranged on both sides of the gate trench 11, extending into the silicon carbide body 1, and the bottom of the shielding region 14 is closer to the second surface 1B than the bottom of the gate trench 11.

[0100] In some examples, reference Figures 6 to 10 The semiconductor device further includes a contact trench, which is disposed on at least one side of the gate trench 11 and extends from the first surface 1A into the silicon carbide body 1 .

[0101] In some examples, reference Figures 6 to 10 , the contact groove is the first contact groove 151 or the second contact groove 152;

[0102] When the contact trench is the first contact trench 151, the shielding region 14 extends from the source region 13 at the bottom of the first contact trench 151 into the silicon carbide body 1;

[0103] When the contact trench is the second contact trench 152 , the shielding region 14 extends from the bottom of the second contact trench 152 into the silicon carbide body 1 .

[0104] In some examples, reference Figures 6 to 10 When the contact trench is the first contact trench 151 , the body region 12 extends from the bottom of the first contact trench 151 to the silicon carbide body 1 and covers a portion of the bottom of the gate trench 11 , and the body region 12 contacts the bottom of the gate trench 11 .

[0105] In some examples, reference Figures 11 to 17 , the number of the gate trenches 11 is at least two;

[0106] One first contact trench 151 is disposed between two adjacent gate trenches 11 .

[0107] In some examples, reference Figures 11 to 17 When the number of the second contact grooves 152 is at least two, the distances between the bottoms of the plurality of second contact grooves 152 and the second surface 1B are not completely the same.

[0108] It should be noted that the specific details of each part of the above-mentioned semiconductor device have been described in detail when describing the manufacturing method of the semiconductor device, and therefore, they will not be repeated here.

[0109] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the inventions claimed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not claimed in the present disclosure.

[0111] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A silicon carbide body (1) is provided, wherein the silicon carbide body (1) comprises a first surface (1A) and a second surface (1B) arranged opposite to the first surface (1A); Forming a gate trench (11) extending from a first surface (1A) of a silicon carbide body (1) into the silicon carbide body (1), wherein the gate trench (11) comprises a sidewall and a bottom; forming a body region (12) and a source region (13), wherein the body region (12) and the source region (13) are in contact with the sidewalls and / or the bottom of the gate trench (11), and the body region (12) is located between the source region (13) and the silicon carbide body (1); A shielding region (14) extending into the silicon carbide body (1) is formed on both sides of the gate trench (11), the shielding region (14) being spaced apart from the gate trench (11), and the bottom of the shielding region (14) being closer to the second surface (1B) than the bottom of the gate trench (11); forming a contact groove extending from the first surface (1A) into the silicon carbide body (1) on at least one side of the gate groove (11); The shielding region (14) extends from the bottom of the contact groove into the silicon carbide body (1); Wherein, the contact groove is a first contact groove (151) or a second contact groove (152); When the contact trench is a first contact trench (151), the shielding region (14) extends from a source region (13) at the bottom of the first contact trench (151) into the silicon carbide body (1); When the contact trench is a second contact trench (152), the shielding region (14) extends from the bottom of the second contact trench (152) and the source region (13) of the first surface (1A) into the silicon carbide body (1) to form a stepped shielding region (14).

2. The method according to claim 1, characterized in that When the contact trench is a first contact trench (151), forming the body region (12) and the source region (13) comprises: A body region (12) and a source region (13) are formed at the bottom of the first contact trench (151), the body region (12) extending from the bottom of the first contact trench (151) to the silicon carbide body (1) and covering a portion of the bottom of the gate trench (11), the body region (12) being in contact with the bottom of the gate trench (11).

3. The method according to claim 1, characterized in that The number of the gate trenches (11) is at least two, and the contact trench extending from the first surface (1A) to the silicon carbide body (1) is formed on at least one side of the gate trench (11), comprising: A first contact trench (151) is formed between adjacent gate trenches (11).

4. The method according to claim 1, characterized in that: When the number of the formed second contact grooves (152) is at least two, the distances between the bottoms of the plurality of second contact grooves (152) and the second surface (1B) are not completely the same.

5. A semiconductor device, characterized in that: include: A silicon carbide body (1), the silicon carbide body (1) comprising a first surface (1A) and a second surface (1B) arranged opposite to the first surface (1A); A gate trench (11) extending from a first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1), the gate trench (11) comprising a side wall and a bottom; A body region (12) and a source region (13) contacting the sidewalls and / or the bottom of the gate trench (11), and the body region (12) is located between the source region (13) and the silicon carbide body (1); A shielding region (14) is arranged on both sides of the gate trench (11), extending into the silicon carbide body (1), and the bottom of the shielding region (14) is closer to the second surface (1B) than the bottom of the gate trench (11); A contact trench, provided on at least one side of the gate trench (11), extending from the first surface (1A) into the silicon carbide body (1); Wherein, the contact groove is a first contact groove (151) or a second contact groove (152); When the contact trench is a first contact trench (151), the shielding region (14) extends from a source region (13) at the bottom of the first contact trench (151) into the silicon carbide body (1); When the contact trench is a second contact trench (152), the shielding region (14) extends from the bottom of the second contact trench (152) and the source region (13) of the first surface (1A) into the silicon carbide body (1) to form a stepped shielding region (14).

6. The semiconductor device according to claim 5, characterized in that When the contact trench is a first contact trench (151), the body region (12) extends from the bottom of the first contact trench (151) into the silicon carbide body (1) and covers a portion of the bottom of the gate trench (11), and the body region (12) is in contact with the bottom of the gate trench (11).

7. The semiconductor device according to claim 5, characterized in that The number of the gate trenches (11) is at least two; A first contact groove (151) is provided between two adjacent gate grooves (11).

8. The semiconductor device according to claim 6, characterized in that When the number of the second contact grooves (152) is at least two, the distances between the bottoms of the plurality of second contact grooves (152) and the second surface (1B) are not completely the same.

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