Image caching system, image caching method, image caching architecture and vehicle

Abstract

The present application provides an image caching system, an image caching method, an image caching architecture and a vehicle, wherein a first cache, a cache pipeline switch and a second cache, the input end of the cache pipeline switch is connected to the first cache, the output end of the cache pipeline switch is connected to the input end of the second cache, the input ends of the first cache and the second cache are both suitable for connecting to an input interface, the output ends of the first cache, the second cache and the cache pipeline switch are all suitable for connecting to an output interface, and the cache pipeline switch is suitable for controlling the on and off of the first cache and the second cache according to the current cache capacity of the input interface and the synchronous cache capacity of the output interface. The present application guarantees the user's video or image viewing experience.

Description

Technical Field

[0001] The present application relates to the field of vehicle technology, and in particular to an image caching system, an image caching method, an image caching architecture and a vehicle. Background Art

[0002] With technological innovation, the current automotive industry is rapidly developing in the direction of "electrification", "intelligence" and "networking". The application of on-board cameras in smart car intelligent driving has been widely popularized, and technological updates are being implemented in a diversified way. Specifically, the sensors on the car not only have their own main functions, but also integrate with each other in smart driving applications to make smart driving safer and more efficient. Among them, the surround camera splicing solution achieves the ultimate effect of splicing the front, back, left and right cameras into one picture, bringing users an excellent driving experience.

[0003] However, the current surround-view camera stitching solution has very high requirements for the camera stitching MIPI (Mobile Industry Processor Interface) accuracy. Otherwise, the images or videos presented to the user will have display abnormalities, such as the mosaic phenomenon of the stitched image or video, which reduces the user's video or image viewing experience. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide an image caching system, an image caching method, an image caching architecture and a vehicle to solve the problem that the images or videos presented to the user in the current solution have display anomalies, affecting the user's video or image viewing experience. The specific technical solution is as follows:

[0005] An embodiment of the present application provides an image cache system, including a first cache, a cache pipe switch, and a second cache, wherein an input end of the cache pipe switch is connected to the first cache, an output end of the cache pipe switch is connected to an input end of the second cache, the input ends of the first cache and the second cache are both suitable for connection to an input interface, the output ends of the first cache, the second cache, and the cache pipe switch are both suitable for connection to an output interface, and the cache pipe switch is suitable for controlling the on-off of the first cache and the second cache by controlling the on-off of the cache pipe switch according to a current cache capacity of the input interface and a synchronous cache capacity of the output interface.

[0006] The embodiment of the present application also discloses an image caching method, which is applicable to the above-mentioned image caching system, and the method includes:

[0007] According to the size of the current cache capacity and the synchronous cache capacity, image caching is performed by controlling the on and off of the cache pipeline switch to control the on and off of the first buffer and the second buffer; the current cache capacity is the cache amount of the image frame received by the current input interface; the synchronous cache capacity is the cache capacity of the buffer required to splice the image frames into a panoramic image.

[0008] The embodiment of the present application also discloses an image cache architecture, including a camera and the image cache system as described above, wherein the image cache system is connected to the camera.

[0009] An embodiment of the present application also discloses an image caching method, which is applicable to the above-mentioned image caching architecture, and the method includes: controlling the opening and closing of the system-level chip to cache pictures according to the size of the current cache capacity and the synchronous cache capacity; the current cache capacity is the cache capacity received by the current input interface; the synchronous cache capacity is the cache capacity required for the output interface to output images or videos.

[0010] The embodiment of the present application also discloses an electronic device, characterized in that it includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus;

[0011] Memory, used to store computer programs;

[0012] The processor is used to implement the above method steps when executing the program stored in the memory.

[0013] The embodiment of the present application further discloses a computer-readable storage medium on which a computer program is stored, wherein the program implements the above method when executed by a processor.

[0014] The embodiment of the present application also discloses a computer program product including instructions, which, when executed on a computer, enables the computer to execute the above method.

[0015] An embodiment of the present application also discloses a vehicle, including the image caching system as described above, or executing the image caching method as described above, or including the image caching architecture as described above, executing the image caching method as described above.

[0016] Compared with the related art, the embodiments of the present application have at least the following advantages:

[0017] In an embodiment of the present application, the image cache system includes a first cache, a cache pipeline switch, and a second cache, the input end of the cache pipeline switch is connected to the first cache, the output end of the cache pipeline switch is connected to the input end of the second cache, the input ends of the first cache and the second cache are suitable for connecting to the input interface, the output ends of the first cache, the second cache, and the cache pipeline switch are suitable for connecting to the output interface, and the cache pipeline switch is suitable for controlling the on-off of the first cache and the second cache according to the current cache capacity of the input interface and the synchronous cache capacity of the output interface. The cache pipeline switch of the embodiment of the present application can control the on-off of the first cache and the second cache according to the current cache capacity of the input interface and the synchronous cache capacity of the output interface, thereby adjusting the cache for storing the image information of the input interface, so as to avoid the size of the image information cached in the cache exceeding the capacity of the cache, and then the output interface can normally output the video information and / or image information and present it to the user, ensuring the user's video or image viewing experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0019] Figure 1 A normal fusion execution block diagram for stitching surround view camera videos of a car;

[0020] Figure 2 It is a fusion execution block diagram of a car's surround view camera video splicing flower screen;

[0021] Figure 3 A schematic diagram of the structure of an image cache system provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of the structure of another image caching system provided in an embodiment of the present application;

[0023] Figure 5 A fusion execution block diagram of a surround view camera video stitching provided in an embodiment of the present application;

[0024] Figure 6 A flowchart of a video stitching implementation scheme of a surround view camera of the present application and a video stitching implementation scheme of a surround view camera of an existing solution provided in an embodiment of the present application;

[0025] Figure 7 A method for triggering camera synchronization behavior provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0027] In specific implementations, the screen noise phenomenon usually manifests itself as irregular color stripes, spots, flickering, distortion and other visual interference on the display, resulting in the image or video being unable to be displayed normally on the display, affecting the user's viewing experience.

[0028] Reference Figure 1 It is a normal fusion execution block diagram of the surround view camera video stitching of a car. The image frames collected by the four cameras (surround view cameras) in front, behind, left and right of the car are stitched together through the video IC (Integrated Circuit) to obtain a panoramic picture or panoramic video (or directly output the image frames without stitching). If the data synchronization difference between the cameras is small and the buffer of the video IC can handle it, then the normal panoramic picture or panoramic video can be displayed on the car's on-board display.

[0029] Reference Figure 2 , is a fusion execution block diagram of the video splicing of the surround view camera of the car. The image frames collected by the four cameras in front, behind, left and right of the car are spliced ​​together through the video IC to obtain a panoramic picture or panoramic video. If the data between the cameras is not synchronized or inconsistent, it will cause abnormal video IC splicing or car display splicing, which will lead to the phenomenon of the panoramic picture or panoramic video screen being distorted. For example, Figure 2 In "Front View 1" and "Front View 2", the front and rear frames are misaligned.

[0030] In the specific implementation, the MIPI image frame header is a synchronization signal that marks the start of transmission of a frame of image. This synchronization signal is used to inform the receiving end (such as a video IC or a car display) that a new frame of image is about to start transmission. FSYNC (Frame Synchronization) is used to indicate the start of a frame of image. The FSYNC (IN) / FSYNC signal is the frame synchronization signal received by the receiving end. The VSYNC (Vertical Synchronization) signal is used to indicate the start of a new frame of image. Ideally, the MIPI image frame header and FSYNC signal are synchronized, that is, when the sensor in the camera generates the MIPI image frame header and FSYNC signal, when the MIPI image frame header output by the sensor in the camera reaches the receiving end, the receiving end should receive the FSYNC signal at the same time, so that the receiving end can accurately know when to start receiving a new frame of image.

[0031] However, there is a designed line deviation between the MIPI image frame header output by the sensor in the camera and the FSYNC signal received by the receiver, that is, the time deviation between the FSYNC signal output by the sensor in the camera and the FSYNC signal actually reaching the receiver. The deviation is measured in rows (H), where a row refers to a row of pixels in the image. The area in the FSYNC signal where the sensor in the camera does not respond to or align with the FSYNC signal is called the dead zone. Usually, the dead zone of the FSYNC signal is ±2H. The internal VSYNC (vertical synchronization) signal is within the dead zone of the FSYNC signal, and the sensor in the camera will not align with the FSYNC signal. Therefore, in theory, the maximum deviation from the FSYNC signal output by the sensor in the camera to the MIPI image frame header is ±2H, that is, 4H.

[0032] The SRAM (Static Random Access Memory) of the video IC has 256Kbit. If the SRAM has no gaps (unallocated or unused areas in the memory address space), its cache capacity can reach 8.3 lines (lines, that is, H represents a row of pixel data in the video image). Due to the FIFO (First Input First Output) mechanism of the video IC, only half of the buffer (linebuffer) in the SRAM can be used to ensure that the data is not overwritten, that is, each line buffer of the video IC can cache 8.3 / 2=4.15 lines. For example, for image frames with a line width of 1920*2=3840 input to the video IC (such as image frames of a 2M camera), each line buffer of the video IC can cache a maximum of 4.15 / 2=2.07 lines; for image frames with a line width of 980*2=3840 input to the video IC (such as image frames of a 1M camera), each line buffer of the video IC can cache a maximum of 4.15 / 1=4.15 lines; for image frames with a line width of 3840*2=7680 input to the video IC (such as image frames of a 4M camera), each line buffer of the video IC can cache a maximum of 4.15 / 4=1.04 lines.

[0033] In summary, if you want to ensure that the DLINK end (car display) displays panoramic video or panoramic images normally, the maximum cached image frame of each line buffer of the video IC needs to be controlled within 2 lines. However, the maximum MIPI deviation of the sensor output in the camera is 4H> the buffer cache of the video IC 2H, so the panoramic video or panoramic image will appear to be distorted, for example Figure 2 In "Front View 1" and "Front View 2", the front and rear frames are misaligned, resulting in a distorted screen.

[0034] In order to solve the problem of flowery screen in the display of spliced ​​panoramic images or panoramic videos in the overall architecture of the existing surround view camera video splicing solution, because the maximum deviation of the MIPI image frame header output by the sensor in the camera is 4H, which is greater than the buffer cache 2H of the video IC, this application provides a new chip cache architecture solution, which solves the problems of the existing solution through a new video chip cache architecture design and a dynamic adjustment method of the frame synchronization frequency without changing the overall architecture of the existing surround view camera. At least the following beneficial effects can be achieved: 1. Without adding the cost of the cache, the cache capacity can be doubled by dynamically arranging and combining the cache; 2. By adding a frame synchronization method, the cache capacity requirement for image frame splicing is reduced, achieving a doubling effect.

[0035] Reference Figure 3 , is a schematic diagram of the structure of an image cache system provided in an embodiment of the present application, such as Figure 3 As shown, the image cache system may include a first cache, a cache pipe switch and a second cache, the input end of the cache pipe switch is connected to the first cache, the output end of the cache pipe switch is connected to the input end of the second cache, the input ends of the first cache and the second cache are both suitable for connecting to an input interface, the output ends of the first cache, the second cache and the cache pipe switch are all suitable for connecting to an output interface, and the cache pipe switch is suitable for controlling the on and off of the first cache and the second cache according to the current cache capacity of the input interface and the synchronous cache capacity of the output interface.

[0036] Specifically, the input interface can receive image frames (image information) captured by an external camera, and the output interface can output image frames or obtain panoramic images based on image frame splicing. The current cache capacity is the cache amount of the image frames received by the current input interface, and the synchronization cache capacity is the cache capacity of the buffer required to splice the image frames into a panoramic image. In simple terms, the synchronization cache capacity can be the cache capacity of the buffer required to normally splice the image frames into a panoramic image without a screen distortion phenomenon. In actual applications, if the current cache capacity is less than the synchronization cache capacity, it means that the size of the image information cached in the buffer exceeds the capacity of the buffer. If a panoramic image is obtained based on image frame splicing at this time, the panoramic image is prone to abnormalities such as screen distortion. If the current cache capacity is greater than or equal to the synchronization cache capacity, it means that the image information cached in the buffer does not exceed the capacity of the buffer, and there is no need to adjust the cache capacity of the buffer at this time.

[0037] Therefore, a cache pipeline switch is provided in the embodiment of the present application. Based on the cache pipeline switch, the on and off of the first buffer and the second buffer can be controlled, so that it can be selected whether to use the first buffer to cache image frames, or to use the first buffer and the second buffer to cache image frames together, thereby avoiding the size of the image information cached in the buffer exceeding the capacity of the buffer, and then the output interface can normally output the video information and / or image information and present it to the user.

[0038] In one embodiment of the present application, referring to Figure 4 The image cache system may further include a communication module, the communication module is connected to the input interface and the cache pipeline switch, the communication module and the input interface are both suitable for receiving image information, the communication module is suitable for inputting picture monitoring information and / or outputting channel control information, and the output interface is suitable for outputting video information and / or image information.

[0039] Specifically, the communication module and the input interface can receive image information, such as image information (such as image frames) around the vehicle captured by a camera, wherein the camera can be one, or usually multiple, and transmits the image frames to a buffer (a first buffer, or a first buffer and a second buffer) for caching. The communication module can determine the input picture monitoring information and / or the output channel control information based on the image frames, so that the image frames can be processed and transmitted normally. The output interface can output video information and / or image information, and finally output it to the display to present it to the user, wherein the video information and / or image information can be a panoramic video or panoramic image obtained after splicing the image frames, or it can be the original video or image frame.

[0040] Specifically, the camera connected to the input interface and the communication module may include a total of four cameras, namely, cameras for right view, front view, left view, and rear view, respectively. The image frames (PIPEX, PIPEY, PIPEZ, PIPEU) of each view angle collected by these cameras can be transmitted to the communication module and the input interface through the input interface (I / O) respectively. Among them, the buffers (buffer channels) corresponding to the right view, front view, left view, and rear view cameras may include 8 BUFFER buffer channels, namely, BUFFER right (BUFFER right'), BUFFER front (BUFFER front'), BUFFER left (BUFFER left'), and BUFFER rear (BUFFER rear'), among which, BUFFER right', BUFFER front', BUFFER left', and BUFFER rear' are used as backup copy buffer channels for the second output in the relevant scheme.

[0041] The buffer can be divided into a first buffer and a second buffer. The first buffer can be the buffer corresponding to the pipeline BUFFER A, that is, the four BUFFER cache channels of BUFFER right, BUFFER front, BUFFER left, and BUFFER back. The second buffer is the four BUFFER cache channels of BUFFER right', BUFFER front', BUFFER left', and BUFFER back'. In the image cache system, the buffer corresponding to the pipeline BUFFER A is used by default to cache image frames. In an example of the present application, there are multiple first buffers and second buffers, and the number of the first buffers and the second buffers is the same.

[0042] The cache pipeline switch (PIPE pipeline switch) can select the buffer used to cache the image information of the camera through the input interface. For example, you can select 4 BUFFER cache channels (pipeline BUFFER A) including BUFFER right, BUFFER front, BUFFER left, and BUFFER back, or you can select 8 BUFFER cache channels (pipeline BUFFER B) including BUFFER right', BUFFER front', BUFFER left', BUFFER back', BUFFER right', BUFFER front', BUFFER left', and BUFFER back', that is, pipeline BUFFER B selects all buffers. The cache pipeline switch is connected to the communication module, so that the cache pipeline switch can be controlled by the communication module, so that the buffer for image information can be selected according to the needs. Pipeline BUFFER A is usually used by default to cache image information.

[0043] In an example of the present application, the output interface includes a splicing unit, which is disposed between the buffer and the output interface. Specifically, in an embodiment of the present application, the output interface may include a splicing unit, which may also be referred to as an aggregator, which may obtain cached image frames from the buffer, splice the cached image frames in the buffer into a panoramic video or a panoramic image, and then output the panoramic video or the panoramic image to the outside through the output interface.

[0044] In one example of the present application, the stitching unit is side by side. Specifically, in the embodiment of the present application, the stitching unit may be side by side. Specifically, side by side is a unit with a video processing technology that can stitch two or more videos or images into one video or image, such as a panoramic video or panoramic image, so as to be viewed on a device that supports 3D display. Therefore, through the side by side stitching unit of the embodiment of the present application, image frames can be stitched into a panoramic image, so that the user can experience a stereoscopic visual effect, and side by side is a standardized image or video processing method, so it can be applicable to various types of vehicles or equipment.

[0045] In one example of the present application, the output interface includes a serial interface, and the input end of the serial interface is connected to the splicing unit. For example, the output interface can be a CSI (Camera Serial Interface) interface, and the serial interface requires fewer wires and connectors, so that the image cache system of the embodiment of the present application will not be too complicated.

[0046] In an example of the present application, the output interface further includes an interface protocol interface, and the input end of the interface protocol interface is connected to the output end of the serial interface. For example, the interface protocol interface can be a D-PHY protocol output interface, and of course it can also be other interface protocols, so that the image cache system of the embodiment of the present application can be compatible with a variety of different interface protocols, thereby improving the compatibility and flexibility of the image cache system.

[0047] In one embodiment of the present application, referring to Figure 5 The splicing unit may include an aggregator, a controller / serial interface (CSI controller) and a physical layer device / D-PHY protocol output interface (D-PHY / C-PHY device) connected in sequence. The splicing unit is connected to the buffer to obtain the image information stored in the buffer for splicing to obtain a panoramic image. The signal is processed by the CSI controller and the D-PHY / C-PHY device, and finally the D-PHY / C-PHY device can be output to an external display, so that a panoramic image including right view, front view, left view and rear view can be displayed on the display.

[0048] In one embodiment of the present application, the image cache system also includes a signal transmission channel selector, and the signal transmission channel selector is connected to the input interface. Specifically, the signal transmission channel selector can be used to select image frames that are allowed to be input into the image cache system. For example, assuming that there are right-view, front-view, left-view, and rear-view cameras, through the signal transmission channel selector, the image frames collected by the right-view, front-view, left-view, and rear-view cameras can be selected to be input into the image cache system, or the image frames collected by some cameras can be selected to be input into the image cache system, so that the video or image that is actually needed to be viewed can be selected according to user needs, thereby improving the user's video or image viewing experience. Among them, the transmission channel selector can be built into the image cache system, or it can be external to the image cache system, and the embodiments of the present invention do not need to be limited to this.

[0049] In an embodiment of the present application, the cache pipeline switch can control the on and off of the first buffer and the second buffer according to the current cache capacity of the input interface and the synchronous cache capacity of the output interface, thereby adjusting the buffer used to store the image information of the input interface, thereby avoiding the size of the image information cached in the buffer exceeding the capacity of the buffer, and then the output interface can normally output the video information and / or image information and present it to the user, ensuring the user's video or image viewing experience.

[0050] The present application also provides a flowchart of a method for image caching, which is applicable to the above-mentioned image caching system. The method may include the following steps:

[0051] According to the size of the current cache capacity and the synchronous cache capacity, image caching is performed by controlling the on and off of the cache pipeline switch to control the on and off of the first buffer and the second buffer; the current cache capacity is the cache amount of the image frame received by the current input interface; the synchronous cache capacity is the cache capacity of the buffer required to splice the image frames into a panoramic image.

[0052] In a specific implementation, it is assumed that the BUFFER in the image cache system is a 256Kbit SRAM. According to the above, when the image cache system receives different image frames, the cache capacity corresponding to the BUFFER is different. For example, for an image frame with a line width of 1920*2=3840 input to the image cache system (such as an image frame of a 2M camera), the cache capacity of each BUFFER of the image cache system is 4.15 / 2=2.07H; for an image frame with a line width of 980*2=3840 input to the image cache system (such as an image frame of a 1M camera), the cache capacity of each line buffer of the image cache system is 4.15 / 1=4.15H; for an image frame with a line width of 3840*2=7680 input to the image cache system (such as an image frame of a 4M camera), the cache capacity of each BUFFER of the image cache system is 4.15 / 4=1.04H. It should be noted that since each camera can correspond to two cache channels respectively, for example, the cache channels corresponding to the right-view camera can include BUFFER right and BUFFER right'. Therefore, for the image frame of 1920*2=3840, when the cache channel of the right-view camera is selected as BUFFER right, its cache capacity is 2.07H, when the cache channel of the right-view camera is selected as BUFFER right and BUFFER right', the cache capacity of the image cache system for each camera is increased by 2 times, that is, at this time the cache capacity of the image cache system can reach 4.15H through the merging of two cache channels.

[0053] Therefore, in an embodiment of the present application, the communication module can determine the current cache capacity based on the BUFFER currently used to cache image frames, and simultaneously monitor the size of the image frames captured by the camera, and determine the synchronization cache capacity (the synchronization cache capacity can also be referred to as cache capacity / BUFFER capacity) based on the size of the image frame and the camera's own design deviation. The synchronization cache capacity is the cache capacity of the BUFFER required to normally splice the image frames into a panoramic image without a screen distortion phenomenon. For example, the inherent design deviation (MIPI deviation) of the sensor in the camera is ±2H. Specifically, the inherent design deviation of the camera is the deviation between the image frame header (MIPI image frame header) and the frame synchronization signal (FSYNC signal) for the image frame output by the camera's processing interface (MIPI). The maximum MIPI deviation output by the sensor in the camera can be determined based on the inherent design deviation of the sensor in the camera and the size of the image frame. For an image frame of 1920*2=3840, the maximum MIPI deviation output by the sensor in the camera can be 4H, and the maximum MIPI deviation of 4H can be used as the synchronization cache capacity.

[0054] In an embodiment of the present application, after determining the current cache capacity and the synchronous cache capacity, an adjustment strategy can be determined based on the current cache capacity and the synchronous cache capacity to control the opening or closing of the cache pipeline switch according to the adjustment strategy to adjust the buffer used to store image frames, so that the adjusted current cache capacity can meet the synchronous cache capacity, thereby ensuring that the panoramic image does not have a screen distortion phenomenon.

[0055] In a specific example, referring to Figure 5 The external right-view, front-view, left-view, and rear-view cameras are connected to the image cache system through the input interface. The cache pipeline switch of the image cache system can select the corresponding pipeline BUFFER to cache the image frames transmitted by the camera through the I / O (input interface). The communication module dynamically monitors the size of the camera's image frame to make a decision. For example, assuming that pipeline BUFFER A is used to cache image frames, if the communication module detects that the current cache capacity is less than the synchronization cache capacity, the adjustment strategy can be to merge pipeline BUFFER A and pipeline BUFFER B to cache image frames. The merger increases the cache capacity of the image cache system by 2 times, and then enters the aggregator for image frame splicing, and the signal is processed by the CSI controller and D-PHY / C-PHY device, and finally output to the external display, so that the normally spliced ​​panoramic image can be displayed on the display.

[0056] In an embodiment of the present application, the current cache capacity can be adjusted to adjust the synchronous cache capacity by adjusting the number of caches used to store image frames in the image cache system to avoid a screen distortion phenomenon in the panoramic image displayed on the display, so that the image cache system of the present application can process image frames with higher clarity, such as image frames captured by a 4M camera.

[0057] In an embodiment of the present application, the image caching is performed by controlling the on / off of the cache pipeline switch to control the on / off of the first cache and the second cache according to the size of the current cache capacity and the synchronous cache capacity, including:

[0058] When the current cache capacity is greater than or equal to the synchronous cache capacity, the first cache and the second cache are disconnected by controlling the on and off of the cache pipeline switch, so as to cache the image frame through the first cache.

[0059] The method of controlling the disconnection of the first buffer and the second buffer by controlling the on and off of the cache pipeline switch includes:

[0060] The cache pipeline switch is turned off to disconnect the first cache from the second cache. Specifically, a cache pipeline switch is provided between the first cache and the second cache, and the first cache is connected to the input interface and the output interface. Therefore, when the cache pipeline switch is turned off, the first cache is disconnected from the second cache, and the image frame can only be cached through the first cache and transmitted to the output interface.

[0061] In an embodiment of the present application, the current cache capacity is obtained from the image monitoring information obtained by the communication module.

[0062] Reference Figure 5 The first buffer may be the buffer corresponding to pipeline BUFFER A, namely, BUFFER right, BUFFER front, BUFFER left, and BUFFER back, and the second buffer may be BUFFER right', BUFFER front', BUFFER left', and BUFFER back'. In the image cache system, the buffer corresponding to pipeline BUFFER A is used by default to cache image frames.

[0063] Reference Figure 6 , is a flow chart of a video stitching implementation scheme of a surround view camera of the present application scheme and a video stitching implementation scheme of a surround view camera of an existing scheme provided in an embodiment of the present application, specifically:

[0064] Reference Figure 6 Flowchart in Scheme A (existing scheme):

[0065] The SRAM of existing video ICs is only 256Kbit, such as Figure 2 As shown, the cache channels of the right-view, front-view, left-view, and rear-view cameras correspond to eight BUFFER cache channels, namely, BUFFER right (BUFFER right'), BUFFER front (BUFFER front'), BUFFER left (BUFFER left'), and BUFFER rear (BUFFER rear'); among them, the four BUFFER cache channels, namely, BUFFER right', BUFFER front', BUFFER left', and BUFFER rear', are cache channels used as backup copies of the second output.

[0066] The existing video chip cache architecture is based on Figure 2As shown, the "communication module" of the video IC (image cache system) of this application is not included. If the line width of the input video IC is 1920*2=3840 (2M camera), it can be seen from the above that the current cache capacity of each BUFFER of the video IC is 4.15 / 2=2.07H, then the maximum MIPI deviation (synchronous cache capacity) output by the sensor in the camera is 4H>the current cache capacity of the video IC 2H, which exceeds the cache capacity of the existing video IC 2Hx2M, so the spliced ​​panoramic image will appear flowery screen problem.

[0067] Reference Figure 6 Flowchart Scheme B (this application scheme):

[0068] The SRAM of the video IC in this application is only 256Kbit. Figure 4 As shown, the cache channels of the right-view, front-view, left-view, and rear-view cameras correspond to eight BUFFER cache channels, namely, BUFFER right (BUFFER right'), BUFFER front (BUFFER front'), BUFFER left (BUFFER left'), and BUFFER rear (BUFFER rear'); among them, the four BUFFER cache channels, namely, BUFFER right', BUFFER front', BUFFER left', and BUFFER rear', are cache channels used as backup copies of the second output.

[0069] The video chip cache architecture scheme of this application is achieved by Figure 5 The "communication module" shown checks the image frame size of the surround view camera. If the line width of the image frame input to the video IC is 960*2=1920 (1M camera), it can be seen from the above that the cache capacity of each BUFFER of the video IC (current cache capacity) is 8.3 / 2=4.15H. Then the maximum MIPI deviation (synchronous cache capacity) output by the sensor in the camera is 4H≤the current cache capacity of the video IC 4H. In this application, the cache capacity of the video IC (image cache system) is within 4Hx1M, so there will be no problem of mosaic display of the panoramic image. Then the video IC can continue to choose to cache the image frame through the buffer corresponding to the pipeline BUFFER A.

[0070] In an embodiment of the present application, the image caching is performed by controlling the on / off of the cache pipeline switch to control the on / off of the first cache and the second cache according to the size of the current cache capacity and the synchronous cache capacity, and further includes:

[0071] In the case where the current cache capacity is smaller than the synchronous cache capacity, the connection between the first cache and the second cache is controlled by controlling the on-off of the cache pipeline switch, and the image frame is cached by the first cache and the second cache.

[0072] The method of controlling the connection between the first buffer and the second buffer by controlling the on and off of the cache pipeline switch includes:

[0073] The cache pipeline switch is turned on to connect the first cache to the second cache. Specifically, a cache pipeline switch is provided between the first cache and the second cache, and the first cache is connected to the input interface and the output interface. Therefore, when the cache pipeline switch is turned on, the first cache is connected to the second cache, and the image frame can be cached through the first cache and the second cache, and the image frame can be transmitted to the output interface.

[0074] Reference Figure 6 Flowchart Scheme D (this application scheme):

[0075] For example, the video chip cache architecture scheme of the present application is as follows: Figure 5 The "communication module" shown checks the image frame size of the surround camera. If the line width of the image frame input to the video IC is 1920*2=3840 (2M camera), it can be seen from the above that the current cache capacity of each BUFFER of the video IC is 4.15 / 2=2.07H, then the maximum MIPI deviation (synchronous cache capacity) output by the sensor in the camera is 4H> the current cache capacity of the video IC 2H, which is beyond the cache capacity of the video IC of this application 2Hx2M, so there will be a problem of mosaic display of the spliced ​​panoramic image. Therefore, the video IC of this application increases the buffer capacity (current cache capacity) of the video IC of this application by 2 times by splicing the BUFFER right + BUFFER right' cache channels of each camera. Then the new buffer capacity of the video IC of this application is 4Hx2M, so there will be no problem of mosaic display. At this time, the video IC can select the buffer corresponding to the pipeline BUFFER B to cache the image frame.

[0076] In summary, the new chip cache architecture solution of "communication module" and "VSYNC check" in the video IC of the present application solves the screen flickering problem of the existing solution through a new video chip cache architecture design and a dynamic adjustment method of the frame synchronization frequency without changing the existing video IC's SRAM of only 256Kbit. The existing video IC can only process 1M cameras, while the present application can increase the cache capacity of the camera's image frame size by 4 times based on the existing video IC's SRAM of only 256Kbit; and adjust the maximum IPI deviation of the M output by the Sensor in the camera to 2H≤the buffer cache of the video IC of the present application within 2Hx4M to avoid the screen flickering phenomenon.

[0077] The embodiment of the present application also discloses an image cache architecture, including a camera and the above-mentioned image cache system, wherein the image cache system is connected to the camera.

[0078] In one embodiment of the present application, there are multiple cameras, and the multiple cameras are cameras facing different directions for collecting images at different angles. For example, the cameras may be four cameras on the vehicle facing different directions, namely, cameras for right view, front view, left view, and rear view, respectively. The cameras for right view, front view, left view, and rear view can collect image frames at different directions and angles, and the field of view of the collected image frames can reach 360 degrees.

[0079] In one embodiment of the present application, the number of cameras corresponds to the number of the first buffer and the second buffer. For example, assuming there are right-view, front-view, left-view, and rear-view cameras, there may be buffers (cache channels) corresponding to the right-view, front-view, left-view, and rear-view cameras, and these buffers may specifically include 8 BUFFER cache channels, namely, BUFFER right (BUFFER right'), BUFFER front (BUFFER front'), BUFFER left (BUFFER left'), and BUFFER rear (BUFFER rear'), among which, BUFFER right', BUFFER front', BUFFER left', and BUFFER rear' are used as backup cache channels for copying the second output in the relevant scheme.

[0080] In one embodiment of the present application, the image cache architecture further includes a system-level chip, which is connected to the communication module and the camera. Specifically, the communication module can be connected to a system-level chip (SOC), and the system-level chip is connected to the camera.

[0081] In one embodiment of the present application, the image cache architecture further includes a display, and the display is connected to the output interface. The display may be a vehicle-mounted display, through which the image or video output by the output interface can be received, so that the user can watch the panoramic image or panoramic video spliced ​​by the splicing unit based on the image frames captured by the right view, front view, left view, and rear view cameras, or can also watch the image frames captured by the right view, front view, left view, and rear view cameras.

[0082] The embodiment of the present application further discloses an image caching method, which is applicable to the above-mentioned image caching architecture, and the method comprises:

[0083] According to the size of the current cache capacity and the synchronous cache capacity, the system-level chip is turned on and off to perform image caching; the current cache capacity is the cache capacity received by the current input interface; the synchronous cache capacity is the cache capacity required for the output interface to output images or videos.

[0084] In a specific implementation, the synchronous cache capacity is determined based on the size of the image frame and the camera's own design deviation, and the camera's own design deviation is the deviation between the MIPI image frame header and the FSYNC signal for the image frame output by the camera's processing interface (MIPI). Therefore, in the embodiment of the present application, when the cache capacity of the cache of the current image cache system is insufficient, the external synchronization mode can be forcibly started. The external SOC (system-on-chip) can be turned on and off to select whether the frequency of the FSYNC signal output by the sensor in the camera needs to be adjusted through the SOC. When the SOC is turned on, the SOC can be used to forcibly change the MIPI deviation of the sensor output in the camera, thereby changing the maximum MIPI deviation of the sensor output in the camera, that is, the synchronous cache capacity. This can prevent the size of the image frame cached in the cache from exceeding the current cache capacity of the cache. In this way, the screen distortion phenomenon can be avoided when the image frames in the cache are spliced ​​and displayed on the display, thereby ensuring the user's video viewing experience.

[0085] For example, refer to Figure 5 The external SOC can start the camera VSYNC (Vertical Synchronization) check mechanism, monitor the VSYNC frequency of the external right-view, front-view, left-view, and rear-view cameras in real time, and forcibly start the external synchronization mode. The SOC adjusts the frequency of the FSYNC signal output by the sensor in the camera, and can force the maximum MIPI deviation (synchronization cache capacity) output by the sensor in the camera to be pulled back to a maximum of 2H, which can reduce the current cache capacity requirement of the buffer required for image frame stitching.

[0086] In an embodiment of the present application, you can choose to adjust the current cache capacity by adjusting the number of buffers used to store image frames in the image cache system, or adjust the synchronization cache capacity by adjusting the frequency of the frame synchronization signal output by the camera, or adjust the current cache capacity by adjusting the number of buffers used to store image frames in the image cache system and adjust the synchronization cache capacity by adjusting the frequency of the frame synchronization signal output by the camera, so as to avoid the phenomenon of screen distortion in the panoramic image displayed on the display, especially when the synchronization cache capacity is much larger than the current cache capacity, you can choose to adjust the number of buffers used to store image frames in the image cache system to adjust the current cache capacity and adjust the synchronization cache capacity by adjusting the frequency of the frame synchronization signal output by the camera, so that the image cache system of the present application can process image frames with higher clarity, such as image frames captured by a 4M camera.

[0087] In one embodiment of the present application, according to the size of the current cache capacity and the synchronous cache capacity, controlling the opening and closing of the system-level chip includes:

[0088] When the current cache capacity is greater than or equal to the synchronization cache capacity, the system-on-chip is shut down.

[0089] In a specific implementation, if the current cache capacity is greater than or equal to the synchronization cache capacity, it means that the image information cached in the cache does not exceed the capacity of the cache. At this time, there is no need to adjust the cache capacity of the buffer. For example, the default first buffer can continue to be maintained to cache image frames.

[0090] In one embodiment of the present application, according to the size of the current cache capacity and the synchronous cache capacity, controlling the opening and closing of the system-level chip includes:

[0091] When the current buffer capacity is smaller than the synchronization buffer capacity, the system-level chip is turned on to adjust the frequency of the frame synchronization signal output by the camera.

[0092] In a specific implementation, if the current cache capacity is smaller than the synchronization cache capacity, it means that the size of the image information cached in the cache exceeds the capacity of the cache. If a panoramic image is obtained based on image frame stitching at this time, the panoramic image is prone to abnormalities such as screen distortion. Therefore, the frequency of the frame synchronization signal output by the camera can be adjusted through the SOC so that the current cache capacity is greater than or equal to the synchronization cache capacity.

[0093] For example, refer to Figure 6 Flowchart Scheme C (this application scheme):

[0094] Exemplarily, the video chip cache architecture scheme of the present application is as follows: Figure 4The "communication module" shown checks the image frame size of the surround camera. If the line width of the image frame input to the video IC is 1920*2=3840 (2M camera), it can be seen from the above that the current cache capacity of each BUFFER of the video IC is 4.15 / 2=2.07H, then the maximum MIPI deviation (synchronous cache capacity) output by the sensor in the camera is 4H>the current cache capacity of the video IC is 2H, which is beyond the cache capacity of the video IC in this application 2Hx2M, so there will be a problem of mosaic panoramic image display screen, so the video IC in this application will start the camera VSYNC check mechanism and force the external synchronization mode (by adjusting the frequency of the SOC FSYNC), which can force the maximum MIPI deviation of the sensor output in the camera to be pulled back to 2H, so that the maximum MIPI deviation of the sensor output in the camera is 2H≤the current cache capacity of the video IC 2H, which is within the current cache capacity of the video IC in this application 2Hx2M, so there will be no display screen problem. Of course, at this time, the video IC can continue to select the buffer corresponding to the pipeline BUFFER A to cache the image frame.

[0095] Reference Figure 7 , which is a schematic diagram of a triggering method of a camera synchronization behavior (including internal synchronization and external synchronization) provided in an embodiment of the present application. The default is to use internal synchronization, which consumes less system resources. When the VSYNC check mechanism detects that the VSYNC signal is 30Hz (Hertz), internal synchronization is used. When the VSYNC check mechanism detects that the VSYNC signal is not 30Hz, external synchronization is used.

[0096] In one embodiment of the present application, when the current buffer capacity is less than the synchronization buffer capacity, the system-level chip is turned on to adjust the frequency of the frame synchronization signal output by the camera, including:

[0097] When the current cache capacity is less than the synchronization cache capacity, the system-level chip is turned on to adjust the frequency of the frame synchronization signal output by the camera; and the connection between the first buffer and the second buffer is controlled to cache the image frame through the first buffer and the second buffer.

[0098] In a specific implementation, if the current cache capacity is smaller than the synchronization cache capacity, it means that the size of the image information cached in the cache exceeds the capacity of the cache. If a panoramic image is obtained based on image frame stitching at this time, the panoramic image is prone to abnormalities such as screen distortion. Therefore, the frequency of the frame synchronization signal output by the camera can be adjusted through the SOC so that the current cache capacity is greater than or equal to the synchronization cache capacity. At the same time, the cache pipeline switch can be controlled to connect so that the first buffer and the second buffer are connected, so that the image frames can be cached together through the first buffer and the second buffer.

[0099] Reference Figure 6 Flowchart Scheme E (this application scheme):

[0100] For example, the video chip cache architecture scheme of the present application is as follows: Figure 5 The "communication module" shown in the figure checks the image frame size of the surround view camera. If the line width of the image frame input to the video IC is 3840*2=7680 (4M camera), it can be seen from the above that the current cache capacity of each BUFFER of the video IC is 2.07 / 2=1.04H, then the maximum MIPI deviation (synchronous cache capacity) output by the sensor in the camera is 4H> the current cache capacity of the video IC 1H. In this application, the cache capacity of the video IC is beyond 1Hx4M, so the spliced ​​panoramic image will appear. The screen is distorted. Therefore, the video IC in this application will select pipeline BUFFER B to cache the image frame (such as Figure 5 As shown), by splicing BUFFER right + BUFFER right' cache path, the buffer capacity (synchronous cache capacity) of the video IC of the present application is increased by 2 times; the buffer capacity of the video IC of the present application is 2Hx4M, but the maximum deviation of the MIPI output of the Sensor in the camera is 4H> the buffer cache of the video IC 2H, which is beyond the buffer capacity of the video IC of the present application 2Hx4M.

[0101] Therefore, the video IC of the present application will also start the camera VSYNC check mechanism and forcibly start the external synchronization mode (by adjusting the frequency of the SOC's FSYNC), which can forcibly pull the maximum MIPI deviation of the sensor output in the camera back to 2H. In this way, the maximum MIPI deviation of the sensor output in the camera is 2H≤2H, the current cache capacity of the video IC. Within the current cache capacity of 2Hx2M of the video IC of the present application, there will be no display screen problem. At this time, the video IC can select the buffer corresponding to the pipeline BUFFER B to cache the image frame.

[0102] In summary, the new chip cache architecture solution of "communication module" and "VSYNC check" in the video IC of the present application solves the screen flickering problem of the existing solution through a new video chip cache architecture design and a dynamic adjustment method of the frame synchronization frequency without changing the existing video IC's SRAM of only 256Kbit. The existing video IC can only process 1M cameras, while the present application can increase the cache capacity of the camera's image frame size by 4 times based on the existing video IC's SRAM of only 256Kbit; and adjust the maximum IPI deviation of the M output by the Sensor in the camera to 2H≤the buffer cache of the video IC of the present application within 2Hx4M to avoid the screen flickering phenomenon.

[0103] The embodiment of the present application also discloses an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0104] Memory, used to store computer programs;

[0105] The processor is used to implement the above method steps when executing the program stored in the memory.

[0106] The embodiment of the present application also discloses a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the above method are implemented.

[0107] The embodiment of the present application also discloses a computer program product including instructions, which, when executed on a computer, enables the computer to execute the steps of the above method.

[0108] An embodiment of the present application also discloses a vehicle, including the above-mentioned image caching system, or executing the steps of the above-mentioned image caching method, or including the above-mentioned image caching architecture, executing the steps of the above-mentioned image caching method.

[0109] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0110] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0111] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0112] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. An image caching system, characterized in that: The device comprises a first buffer, a buffer pipe switch, a second buffer and a system-level chip, wherein the input end of the buffer pipe switch is connected to the first buffer, the output end of the buffer pipe switch is connected to the input end of the second buffer, the input ends of the first buffer and the second buffer are both suitable for connecting to an input interface, the output ends of the first buffer, the second buffer and the buffer pipe switch are both suitable for connecting to an output interface, and the buffer pipe switch is suitable for controlling the on and off of the first buffer and the second buffer; The cache pipeline switch controls the on and off of the first cache and the second cache according to the current cache capacity of the input interface and the synchronous cache capacity of the output interface, and / or the system-level chip adjusts the frequency of the frame synchronization signal output by the camera according to the current cache capacity of the input interface and the synchronous cache capacity of the output interface; the synchronous cache capacity is determined by the size of the image frame and the design deviation of the camera; the design deviation is the deviation between the synchronization signal output by the camera and the frame synchronization signal.

2. The image caching system according to claim 1, characterized in that: There are multiple first buffers and multiple second buffers.

3. The image caching system according to claim 2, characterized in that: The number of the first buffers is the same as the number of the second buffers.

4. The image caching system according to claim 2, characterized in that: It also includes a communication module, which is connected to the cache pipeline switch. The communication module and the input interface are both suitable for receiving image information. The communication module is suitable for inputting picture monitoring information and / or outputting channel control information.

5. The image cache system according to any one of claims 1 to 4, characterized in that: The output interface includes a splicing unit, and the splicing unit is arranged between the buffer and the output interface.

6. The image caching system according to claim 5, characterized in that: The splicing unit is side by side.

7. The image cache system according to any one of claims 1 to 4, characterized in that: The output interface comprises a serial interface, and an input end of the serial interface is connected to the splicing unit.

8. The image caching system according to claim 7, characterized in that: The output interface also includes an interface protocol interface, and the input end of the interface protocol interface is connected to the output end of the serial interface.

9. The image caching system according to claim 8, characterized in that: The interface protocol interface is the D-PHY protocol.

10. The image cache system according to claim 8, characterized in that: It also includes a signal transmission channel selector, which is connected to the input interface.

11. An image caching method, characterized in that: Applicable to the image caching system according to any one of claims 1 to 10, the method comprising: According to the size of the current cache capacity and the synchronous cache capacity, the image cache is performed by controlling the on and off of the cache pipeline switch to control the on and off of the first cache and the second cache; the current cache capacity is the cache capacity of the image frame received by the current input interface; the synchronous cache capacity is the cache capacity of the cache required for splicing the image frames into a panoramic image; and / or, According to the current cache capacity and the synchronization cache capacity, the frequency of the frame synchronization signal output by the camera is adjusted to perform image caching; the synchronization cache capacity is determined by the size of the image frame and the design deviation of the camera; the design deviation is the deviation between the synchronization signal output by the camera and the frame synchronization signal.

12. The method according to claim 11, characterized in that According to the current cache capacity and the synchronous cache capacity, the cache pipeline switch is controlled to be on and off so as to control the on and off of the first cache and the second cache, so as to cache the picture, including: When the current cache capacity is greater than or equal to the synchronous cache capacity, the first cache and the second cache are disconnected by controlling the on and off of the cache pipeline switch, so as to cache the image frame through the first cache.

13. The method according to claim 12, characterized in that Controlling the disconnection of the first cache and the second cache by controlling the on and off of the cache pipeline switch includes: The cache pipeline switch is turned off to disconnect the first cache from the second cache.

14. The method according to claim 12, characterized in that The method of performing image caching by controlling the on-off of the cache pipeline switch to control the on-off of the first cache and the second cache according to the current cache capacity and the synchronous cache capacity, further includes: In the case where the current cache capacity is smaller than the synchronous cache capacity, the connection between the first cache and the second cache is controlled by controlling the on-off of the cache pipeline switch, and the image frame is cached by the first cache and the second cache.

15. The method according to claim 14, characterized in that Controlling the connection between the first buffer and the second buffer by controlling the on and off of the cache pipeline switch includes: The cache pipeline switch is turned on to connect the first cache to the second cache.

16. The method according to any one of claims 11 to 15, characterized in that: The current cache capacity is obtained from the image monitoring information obtained by the communication module.

17. An image cache architecture, characterized in that: It comprises a camera and an image caching system as described in any one of claims 1 to 10, wherein the image caching system is connected to the camera; according to the size of the current cache capacity and the synchronous cache capacity, the opening and closing of the system-level chip is controlled, and / or the connection between the first cache and the second cache is controlled to perform image caching.

18. The image cache architecture according to claim 17, characterized in that: There are multiple cameras.

19. The image cache architecture according to claim 18, characterized in that: The multiple cameras are cameras facing different directions and used to collect images from different angles.

20. The image cache architecture according to claim 18, characterized in that: The number of cameras corresponds to the number of the first buffer and the second buffer.

21. The image cache architecture according to claim 18, characterized in that: The image cache architecture also includes a system-level chip, and the system-level chip is connected to the communication module and the camera.

22. The image cache architecture according to claim 18, characterized in that: The image cache architecture also includes a display connected to the output interface.

23. An image caching method, characterized in that: Applicable to the image cache architecture according to any one of claims 17 to 22, the method comprising: According to the size of the current cache capacity and the synchronous cache capacity, the opening and closing of the system-level chip is controlled, and / or the connection between the first cache and the second cache is controlled to perform image caching; the current cache capacity is the cache capacity received by the current input interface; the synchronous cache capacity is the cache capacity required for the output interface to output images or videos.

24. The method according to claim 23, characterized in that Control the opening and closing of the system-level chip according to the current cache capacity and the synchronous cache capacity, including: When the current buffer capacity is smaller than the synchronization buffer capacity, the system-level chip is turned on to adjust the frequency of the frame synchronization signal output by the camera.

25. The method according to claim 23, characterized in that Control the opening and closing of the system-level chip according to the current cache capacity and the synchronous cache capacity, including: When the current cache capacity is greater than or equal to the synchronization cache capacity, the system-on-chip is shut down.

26. The method according to claim 24, characterized in that When the current buffer capacity is less than the synchronization buffer capacity, the system-level chip is turned on to adjust the frequency of the frame synchronization signal output by the camera, including: When the current cache capacity is less than the synchronization cache capacity, the system-level chip is turned on to adjust the frequency of the frame synchronization signal output by the camera; and the connection between the first buffer and the second buffer is controlled to cache image frames through the first buffer and the second buffer.

27. The method according to claim 23, characterized in that The synchronization cache capacity is determined by the size of the image frame and the design deviation of the camera; the design deviation of the camera itself is the deviation between the image frame header and the frame synchronization signal for the image frame output by the processing interface of the camera.

28. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing the method steps described in any one of claims 11 to 16 or any one of claims 23 to 27 when executing a program stored in a memory.

29. A computer program product comprising instructions, which, when executed on a computer, causes the computer to perform the method of any one of claims 11 to 16, or any one of claims 23 to 27.

30. A vehicle, comprising an image caching system as claimed in any one of claims 1 to 10, or executing an image caching method as claimed in any one of claims 11 to 16, or comprising an image caching architecture as claimed in any one of claims 17 to 22, or executing an image caching method as claimed in any one of claims 23 to 27.

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