Real-time monitoring and debugging method, device and electronic equipment for RISC-V chip

Abstract

The present application provides a real-time monitoring and debugging method, device and electronic device for a RISC‑V chip, and relates to the field of chip design and debugging. In the method, the ebreakm bit of the debug mode control and status register is initialized, and it is determined whether the ebreakm bit is modified. If it is modified to the debug bit, the ebreak instruction is executed; the pause bit of the RISC‑V chip is read, and when entering the debug state, the cause bit of the debug module status register and the debug mode control and status register is modified; when the value in the debug module status register indicates a pause, it is determined whether the value of the cause bit is a debug state; when the value of the cause bit indicates a debug state, the debug information in the RISC‑V chip is directly obtained and displayed. The debug information can be directly read, the structure is simple, and the development and debugging efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip design and debugging technology, and specifically to a real-time monitoring and debugging method, device and electronic equipment for a RISC-V chip. Background Art

[0002] In the RISC-V architecture, when an embedded program needs to perform an I / O operation, it usually triggers an exception through a specific software instruction and enters the debug mode. After receiving this exception, the debugger uses the semihosting debugging technology to parse and process the corresponding semihosting request, and then returns the result to the embedded program. Embedded programs are allowed to use the services of the debugger, such as printouts or file operations, but this usually requires the program to send data in a specific protocol format. Since data needs to be sent in a specific protocol format, when data is transmitted, the debugger further reads the data of the debug information memory address, and semihosting technology needs to be used to parse the transmitted data, which has a more complex structure. Summary of the invention

[0003] The present application provides a real-time monitoring and debugging method, device and electronic device for a RISC-V chip, which can directly read debugging information, has a simple structure and improves development and debugging efficiency.

[0004] The technical solution of the embodiment of the present application is as follows:

[0005] In a first aspect, an embodiment of the present application provides a real-time monitoring and debugging method for a RISC-V chip, which is applied to a debugging device, wherein the debugging device is connected to the RISC-V chip, and the method comprises:

[0006] Initialize the ebreakm bit of the debug mode control and status register, determine whether the ebreakm bit is modified, and execute the ebreak instruction if it is modified to the debug bit;

[0007] Read the pause bit of the RISC-V chip, and when entering the debug state, modify the cause bit of the debug module status register and the debug mode control and status register;

[0008] In the case where the value in the debug module status register indicates a pause, determining whether the value of the cause bit is a debug state;

[0009] When the value of the cause bit indicates a debugging state, the debugging information in the RISC-V chip is directly obtained and displayed.

[0010] In the above technical scheme, the real-time monitoring and debugging method of the RISC-V chip is applied to a debugging device, and the debugging device is connected to the RISC-V chip to debug the RISC-V chip. First, the ebreakm bit of the debug mode control and status register is initialized, and the ebreakm bit is initialized to perform subsequent data storage, and it is judged whether the ebreakm bit is modified, so as to judge whether to execute the interrupt instruction. In the case of modification to the debug bit, the ebreak instruction is executed, and the program is interrupted by the ebreak instruction; the pause bit of the RISC-V chip is read, which is conducive to judging whether the ebreak instruction indicates to enter the debug state. In the case of entering the debug state, the cause bit of the debug module status register and the debug mode control and status register is modified; in the case where the value in the debug module status register indicates a pause, it is judged whether the value of the cause bit is a debug state; in the case where the value of the cause bit indicates a debug state, the debugging information in the RISC-V chip is directly obtained and displayed, and the above judgment is performed to determine that the program is paused to enter the debug state, and the debugging information is directly obtained without parsing, and the structure is simple, which improves the development and debugging efficiency.

[0011] In some embodiments of the present application, after directly acquiring the debugging information in the RISC-V chip and displaying it, the method further includes:

[0012] The value of the program counter is updated according to the address of the next instruction of the ebreak instruction, and the updated value of the program counter points to the execution program.

[0013] In the above technical solution, the value of the program counter is updated according to the address of the next instruction of the ebreak instruction to obtain the updated value of the program counter, and the updated value of the program counter points to the program statement to be executed. By changing the value of the program counter, it can be ensured that the program continues to be executed smoothly after the debugging state.

[0014] In some embodiments of the present application, the initializing the ebreakm bit of the debug mode control and status register includes:

[0015] If the ebreakm bit does not exist, create the ebreakm bit to store the value corresponding to the read ebreakm bit;

[0016] When the ebreakm bit exists, the value corresponding to the read ebreakm bit is directly stored.

[0017] In the above technical solution, if the ebreakm bit does not exist, it means that there is no storage bit capable of storing the interrupt indication value on the debugging device side, and the ebreakm bit is created to store the value corresponding to the read ebreakm bit for subsequent judgment on whether to execute the interrupt instruction. If the ebreakm bit exists, it means that there is a storage bit capable of storing the interrupt indication value on the debugging device side, and the value corresponding to the read ebreakm bit is directly stored, and subsequent judgment on whether to execute the interrupt instruction can be performed.

[0018] In some embodiments of the present application, after determining whether the value of the cause bit is in a debugging state, the method includes:

[0019] When the value of the cause bit indicates a non-debugging state, the value of the program counter is modified, and the step of reading the pause bit of the RISC-V chip is performed. When entering the debugging state, the cause bits of the debug module status register and the debug mode control and status register are modified.

[0020] In the above technical solution, when the value of the cause bit indicates a non-debugging state, the program is continued to be executed by modifying the value of the program counter, and while modifying the program counter, the step of reading the pause bit of the RISC-V chip is executed, and when entering the debugging state, the cause bit of the debug module status register and the debug mode control and status register is modified. By reading the pause bit of the RISC-V chip, it is monitored in real time whether the program execution is interrupted and enters the debugging state.

[0021] In some embodiments of the present application, the debug module status register includes an allhalted bit and an anyhalted bit;

[0022] The modifying the cause bit of the debug module status register and the debug mode control and status register comprises:

[0023] The value corresponding to the allhalted bit and the value corresponding to the anyhalted bit are both set to 1, and the corresponding allhalted bit and the anyhalted bit are written.

[0024] In the above technical solution, since the initial state of the allhalted bit and the anyhalted bit may not be 1, the corresponding bit value needs to be modified for program debugging. After the modification, the modified value is written into the corresponding allhalted bit and anyhalted bit, and when the value of the pause bit is read to indicate a pause, a subsequent state judgment is performed to ensure the debugging state.

[0025] In some embodiments of the present application, after modifying the debug module status register, the method includes:

[0026] When the value in the debug module status register indicates non-pause, the value of the program counter is modified, and the step of reading the pause bit of the RISC-V chip is performed. When entering the debug state, the cause bit of the debug module status register and the debug mode control and status register is modified.

[0027] In the above technical solution, when the value of the cause bit indicates a non-debugging state, that is, it means not entering the program debugging state, the value of the program counter is modified, and by modifying the value of the program counter, it is possible to jump to the program to be executed. While modifying the program counter, the step of reading the pause bit of the RISC-V chip is executed, and when entering the debugging state, the step of modifying the cause bit of the debug module status register and the debug mode control and status register is modified. By reading the pause bit of the RISC-V chip, it is possible to monitor in real time whether the program execution is interrupted and enter the debugging state.

[0028] In a second aspect, an embodiment of the present application provides a real-time monitoring and debugging device for a RISC-V chip, which is applied to a debugging device, the debugging device being connected to the RISC-V chip, and the device comprising:

[0029] An initialization judgment module is used to initialize the ebreakm bit of the debug mode control and status register, judge whether the ebreakm bit is modified, and execute the ebreak instruction when it is modified to the debug bit;

[0030] A data reading and configuration module, used to read the pause bit of the RISC-V chip, and to modify the cause bit of the debug module status register and the debug mode control and status register when entering the debug state;

[0031] A state determination module, configured to determine whether the value of the cause bit is a debugging state when the value in the debugging module state register indicates a pause;

[0032] The information acquisition and display module is used to directly acquire the debugging information in the RISC-V chip and display it when the value of the cause bit indicates a debugging state.

[0033] In some embodiments of the present application, the debugging device also includes a debugger, and the debugger is connected to the display device via one of Bluetooth, WiFi, and a network cable, and the display device is a mobile phone or a central control PC.

[0034] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor, a memory, a user interface, a communication bus and a network interface, wherein the processor, the memory, the user interface and the network interface are respectively connected to the communication bus, the memory is used to store instructions, the user interface and the network interface are used to communicate with other devices, and the processor is used to execute the instructions stored in the memory so that the electronic device executes any one of the methods provided in the first aspect.

[0035] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, and when the instructions are executed, any one of the methods provided in the first aspect is executed.

[0036] In summary, one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0037] 1. Due to the adoption of the ebreakm bit of the debug mode control and status register initialization, the ebreakm bit is initialized for subsequent data storage, and it is determined whether the ebreakm bit is modified, thereby determining whether to execute the interrupt instruction. When it is modified to the debug bit, the ebreak instruction is executed, and the program is interrupted by the ebreak instruction; reading the pause bit of the RISC-V chip is conducive to determining whether the ebreak instruction indicates to enter the debug state. When entering the debug state, the cause bit of the debug module status register and the debug mode control and status register is modified; when the value in the debug module status register indicates a pause, it is determined whether the value of the cause bit is a debug state; when the value of the cause bit indicates a debug state, the debug information in the RISC-V chip is directly obtained and displayed. Through the above judgment, it is determined that the program is paused to enter the debug state, and the debug information is directly obtained without parsing. The structure is simple, and the development and debugging efficiency is improved. Therefore, the problem that the semihosting technology needs to be used to parse the transmission data in the related technology, and the structure is relatively complex, is effectively solved.

[0038] 2. The debugging device can be configured with Bluetooth and network cable to output the debugging information to the display device, making it more flexible to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flowchart of a real-time monitoring and debugging method of a RISC-V chip provided by an embodiment of the present application;

[0040] Figure 2 This is a schematic diagram of the overall process of a real-time monitoring and debugging method for a RISC-V chip provided by an embodiment of the present application;

[0041] Figure 3 It is a structural diagram of a real-time monitoring and debugging device for a RISC-V chip provided by an embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of the overall connection structure of a real-time monitoring and debugging device for a RISC-V chip provided by an embodiment of the present application;

[0043] Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0045] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0046] In the description of the embodiments of the present application, the meaning of the term "multiple" refers to two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0047] First, the technical terms appearing in the embodiments of the present application are explained.

[0048] ebreak instruction: ebreak is used to explicitly request a debug interrupt and can be used as a debug point in software. When the processor encounters ebreak, it generates a debug exception or enters debug mode.

[0049] Debugger connection: When using ebreak for debugging, you need to use a debugging tool that supports RISC-V chips, such as GDB or OpenOCD.

[0050] Semihosting: Semihosting is a debugging technique that allows an embedded system to interact with a host operating system through a debugging connection, usually for the purpose of outputting debugging information. In a RISC-V environment, this usually requires the program to call specific "system calls" with the support of specific libraries to transfer data to the host. Follow a fixed format information structure: When debugging with GDB or OpenOCD, the implementation of Semihosting needs to follow a certain protocol to format data transfer. For example, for outputting strings, it may be necessary to construct a specific call sequence, which is usually handled automatically by the compiler or debug library.

[0051] The embodiment of the present application provides a real-time monitoring and debugging method, device, electronic device and readable storage medium of a RISC-V chip, and the real-time monitoring and debugging method of the RISC-V chip is applied to a debugging device, and the debugging device is connected to the RISC-V chip to debug the RISC-V chip. First, the ebreakm bit of the debug mode control and status register is initialized, and the ebreakm bit is initialized to perform subsequent data storage, and it is judged whether the ebreakm bit is modified, so as to judge whether to execute the interrupt instruction. In the case of modification to the debug bit, the ebreak instruction is executed, and the program is interrupted by the ebreak instruction; the pause bit of the RISC-V chip is read, which is conducive to judging whether the ebreak instruction indicates to enter the debug state, and in the case of entering the debug state, the cause bit of the debug module status register and the debug mode control and status register is modified; in the case of the value in the debug module status register indicating a pause, it is judged whether the value of the cause bit is a debug state; in the case of the value of the cause bit indicating a debug state, the debugging information in the RISC-V chip is directly obtained and displayed, and the above judgment is performed to determine that the program is paused to enter the debug state, and the debugging information is directly obtained without parsing, and the structure is simple, which improves the development and debugging efficiency.

[0052] It should be noted that the real-time monitoring and debugging method of the RISC-V chip is applied to the debugging of the RISC-V chip. For reading the debugging information, there is no need to parse the data through the semihosting debugging technology. The debugging content can be directly read and displayed, which simplifies the data reading process and can improve the development and debugging efficiency.

[0053] The technical solution provided in the embodiments of the present application is further described below in conjunction with the accompanying drawings.

[0054] Reference Figure 1 , Figure 1It is a flowchart of the real-time monitoring and debugging method of the RISC-V chip provided in the embodiment of the present application. The real-time monitoring and debugging method of the RISC-V chip is applied to the real-time monitoring and debugging device of the RISC-V chip in the debugging device, the debugging device is connected to the RISC-V chip, and the real-time monitoring and debugging method of the RISC-V chip is executed by the processor in the electronic device or the readable storage medium, and the real-time monitoring and debugging method of the RISC-V chip includes step S110, step S120, step S130 and step S140.

[0055] Step S110, initializing the ebreakm bit of the debug mode control and status register, determining whether the ebreakm bit is modified, and executing the ebreak instruction if it is modified to the debug bit.

[0056] In one embodiment, before initialization, the debugger connection, debugging tools and multiple registers stored are configured to ensure successful debugging. The debug mode control and status register includes multiple storage bits. The ebreakm bit of the debug mode control and status register is first initialized, which is used to store the corresponding value corresponding to the ebreakm bit with an address later, so as to determine whether to execute an interrupt instruction. After initializing the ebreakm bit, the location can be stored to determine whether the ebreakm bit is modified, that is, to determine whether the value stored in the ebreakm bit indicates the execution of an interrupt instruction. In the case of being modified to the debug bit, that is, the value in the ebreakm bit is 1 in the debug specification, indicating interrupt debugging, the ebreak instruction is executed to enter the debug state later.

[0057] In another embodiment, the ebreakm bit of the debug mode control and status register is initialized, including but not limited to: if the ebreakm bit does not exist, the ebreakm bit is created to store the value corresponding to the read ebreakm bit; if the ebreakm bit exists, the value corresponding to the read ebreakm bit is directly stored.

[0058] In some possible embodiments of the present application, when the ebreakm bit does not exist, it means that there is no storage bit capable of storing the indication interrupt value on the debugging device side, and the ebreakm bit is created to store the value corresponding to the read ebreakm bit, which is used for subsequent judgment on whether to execute the interrupt instruction. When the ebreakm bit exists, it means that there is a storage bit capable of storing the indication interrupt value on the debugging device side, and the value corresponding to the read ebreakm bit is directly stored, and subsequent judgment on whether to execute the interrupt instruction can be made. By initializing the ebreakm bit in the debugging mode control and status register, the initial condition for debugging is constructed.

[0059] Step S120, read the pause bit of the RISC-V chip, and when entering the debugging state, modify the cause bit of the debugging module status register and the debugging mode control and status register.

[0060] In one embodiment, according to the executed break instruction, the pause bit of the RISC-V chip, that is, the value of the break instruction, is read. When the value of the breadk instruction is 1, it indicates that the program has entered the debugging stage. When entering the debugging state, the cause bit of the debugging module status register and the debugging mode control and status register is modified through the preset debugging interface, and the value of the corresponding register is modified to determine whether to perform program interrupt debugging. It should be noted that the debugging module status register includes not only the ebreakm bit, but also the program pause flag bit, which is used to indicate that the program is paused to determine the entry into the debugging state. The preset debugging interface can be JTAG or SWD.

[0061] In one embodiment, the debug module status register includes an allhalted bit and an anyhalted bit, and modifying the cause bit of the debug module status register and the debug mode control and status register includes but is not limited to: setting the value corresponding to the allhalted bit and the value corresponding to the anyhalted bit to 1, and writing the corresponding allhalted bit and anyhalted bit.

[0062] In some possible embodiments of the present application, the debugging module status register is modified mainly to modify the values ​​in the allhalted bit and the anyhalted bit. When entering the debugging state mode, the value corresponding to the allhalted bit and the value corresponding to the anyhalted bit are both set to 1. Both of these two bits represent the pause bit, which is used to indicate that the program is suspended. Since the initial state of the allhalted bit and the anyhalted bit may not be 1, it is necessary to modify the corresponding bit value to debug the program. After the modification, the modified value is written into the corresponding allhalted bit and anyhalted bit. When the value of the pause bit is read to indicate a pause, a subsequent state judgment is performed to ensure that the debugging state is performed.

[0063] Step S130: When the value in the debug module status register indicates a pause, determine whether the value of the cause bit is a debug state.

[0064] In one embodiment, when the value in the debug module status register indicates a pause, that is, when the allhalted bit and the anyhalted bit are both read as 1, it is determined whether the value of the cause bit is a debug state, and the determination is made layer by layer to ensure that the debug state is entered so that the debug information can be subsequently read and displayed.

[0065] In one embodiment, after modifying the debug module status register, the real-time monitoring and debugging method of the RISC-V chip includes but is not limited to: when the value in the debug module status register indicates non-pause, modify the value of the program counter and execute the read of the pause bit of the RISC-V chip, and when entering the debug state, modify the debug module status register and the debug mode control and cause bit of the status register.

[0066] In some possible embodiments of the present application, the allhalted bit or the anyhalted bit is not 1, that is, one of the bits is not 1, which is a non-pause situation. When the value in the debug module status register indicates a non-pause, the program does not suspend execution and does not enter the debug state. In this case, the value of the program counter is modified, and the value of the program counter indicates the statement of the execution program. By modifying the value of the program counter, it is possible to jump to the program to be executed. While modifying the program counter, read the pause bit of the RISC-V chip, and when entering the debug state, modify the debug module status register and the debug mode control and status register. Cause bit step. By reading the pause bit of the RISC-V chip, monitor whether the program execution is interrupted in real time and enter the debug state.

[0067] Step S140, when the value of the cause bit indicates a debugging state, directly obtain the debugging information in the RISC-V chip and display it.

[0068] In one embodiment, the cause bit can be set to a variety of different values. When the cause bit is written as 1, it indicates that the program is interrupted and enters the debugging state. The value of the cause bit can also be other numerical values. When the value of the cause bit is other numerical values, it does not indicate that the program is interrupted and enters the debugging state. When the value of the cause bit indicates the debugging state, the debugging information in the RISC-V chip is directly obtained through the data reading interface, and there is no need to use semihosting to parse and obtain the content, and the structure is relatively simple. The read debugging information can also be displayed on a display device. The debugger is connected to the display device via one of Bluetooth, WiFi, and a network cable. The display device is a mobile phone or a central control PC.

[0069] In another embodiment, after determining whether the value of the cause bit is in a debugging state, the real-time monitoring and debugging method of the RISC-V chip includes but is not limited to: when the value of the cause bit indicates a non-debugging state, modifying the value of the program counter, and executing the read of the pause bit of the RISC-V chip, and when entering the debugging state, modifying the cause bit of the debugging module status register and the debugging mode control and status register.

[0070] In some possible embodiments of the present application, when the value of the cause bit indicates a non-debugging state, that is, when the program debugging state is not entered, the value of the program counter is modified, and the program to be executed can be jumped to by modifying the value of the program counter. While modifying the program counter, the step of reading the pause bit of the RISC-V chip is performed, and when entering the debugging state, the step of modifying the cause bit of the debug module status register and the debug mode control and status register is modified. By reading the pause bit of the RISC-V chip, whether the program execution is interrupted is monitored in real time, and the debugging state is entered.

[0071] In one embodiment, after directly acquiring the debugging information in the RISC-V chip and displaying it, the real-time monitoring and debugging method of the RISC-V chip also includes but is not limited to: updating the value of the program counter according to the address of the next instruction of the ebreak instruction, and the updated value of the program counter points to the execution program.

[0072] In one embodiment, the address of the next instruction of the ebreak instruction stores the instruction to be executed, and the value of the program counter is updated according to the address of the next instruction of the ebreak instruction to obtain the value of the updated program counter. The updated value of the program counter points to the program statement to be executed. By changing the value of the program counter, it can be ensured that the program continues to be executed smoothly after the debugging state.

[0073] like Figure 2As shown, the embodiment of the present application provides a schematic diagram of the overall flow of a real-time monitoring and debugging method for a RISC-V chip. First, the ebreakm bit of the debug mode control and status register is initialized. When the ebreakm bit does not exist, it means that there is no storage bit capable of storing the indicating interrupt value on the debug device side, and then the ebreakm bit is created to store the value corresponding to the read ebreakm bit, which is used for subsequent judgment whether to execute the interrupt instruction. When the ebreakm bit exists, it means that there is a storage bit capable of storing the indicating interrupt value on the debug device side, and the value corresponding to the read ebreakm bit is directly stored, and then the subsequent judgment whether to execute the interrupt instruction can be made. By initializing the ebreakm bit in the debug mode control and status register, the initial condition for debugging is constructed. Then it is judged whether the ebreakm bit is modified, that is, it is judged whether the value stored in the ebreakm bit indicates the execution of the interrupt instruction. In the case of being modified to the debug bit, that is, the value in the ebreakm bit is 1 in the debug specification, indicating interrupt debugging, then the ebreak instruction is executed to enter the debug state later. According to the executed break instruction, the pause bit of the RISC-V chip, that is, the value of the break instruction, is read. When the value of the breadk instruction is 1, it indicates that the program has entered the debugging stage. When entering the debugging state, the debug module status register and the cause bit of the debug mode control and status register are modified through the preset debug interface. By modifying the value of the corresponding register, it is used to determine whether to perform program interrupt debugging in the future. Among them, the debug module status register includes the allhalted bit and the anyhalted bit. The values ​​corresponding to the allhalted bit and the values ​​corresponding to the anyhalted bit are set to 1, and the corresponding allhalted bit and anyhalted bit are written.

[0074] When the value in the debug module status register indicates a pause, that is, when both the allhalted bit and the anyhalted bit are read as 1, it is determined whether the value of the cause bit is a debug state, and the judgment is made layer by layer to ensure that the debug state is entered, so that the debug information can be read and displayed later. If the allhalted bit or the anyhalted bit is not 1, that is, one of the bits is not 1, it is a non-pause situation. When the value in the debug module status register indicates a non-pause, the program does not pause execution and does not enter the debug state. In this case, the value of the program counter is modified, and the value of the program counter indicates the statement of the execution program. By modifying the value of the program counter, it is possible to jump to the program to be executed. While modifying the program counter, the steps of reading the pause bit of the RISC-V chip are executed, and when entering the debug state, the cause bit of the debug module status register and the debug mode control and status register are modified. By reading the pause bit of the RISC-V chip, it is monitored in real time whether the program execution is interrupted and enters the debug state. When the value of the cause bit indicates a debugging state, the debugging information in the RISC-V chip is directly obtained through the data reading interface, and there is no need to use semihosting to parse and obtain the content, and the structure is relatively simple. When the value of the cause bit indicates a non-debugging state, it means that the program debugging state is not entered, and the value of the program counter is modified. By modifying the value of the program counter, it is possible to jump to the program to be executed. While modifying the program counter, the step of reading the pause bit of the RISC-V chip is executed. When entering the debugging state, the step of modifying the cause bit of the debug module status register and the debug mode control and status register is modified. By reading the pause bit of the RISC-V chip, it is possible to monitor in real time whether the program execution is interrupted and enter the debugging state.

[0075] like Figure 3As shown, the embodiment of the present application provides a real-time monitoring and debugging device 100 for a RISC-V chip, and the real-time monitoring and debugging device 100 for a RISC-V chip is applied to a debugging device, and the debugging device is connected to the RISC-V chip. The real-time monitoring and debugging device 100 for the RISC-V chip initializes the ebreakm bit of the debug mode control and status register through the initialization judgment module 110, and initializes the ebreakm bit to perform subsequent data storage, and determines whether the ebreakm bit is modified, thereby determining whether to execute an interrupt instruction. In the case of being modified to the debug bit, the ebreak instruction is executed, and the program is interrupted by the ebreak instruction; then the data reading and configuration module 120 is used to read Taking the pause bit of the RISC-V chip is helpful to determine whether the ebreak instruction indicates entering the debugging state. When entering the debugging state, modify the cause bit of the debugging module status register and the debugging mode control and status register; then, when the value in the debugging module status register indicates a pause, the state judgment module 130 determines whether the value of the cause bit is a debugging state; finally, when the value of the cause bit indicates a debugging state, the information acquisition and display module 140 is used to directly obtain the debugging information in the RISC-V chip and display it. Through the above judgment, it is determined that the program is paused to enter the debugging state, and the debugging information is directly obtained without parsing. The structure is simple, which improves the development and debugging efficiency.

[0076] It should be noted that the initialization judgment module 110 is connected to the data reading and configuration module 120, the data reading and configuration module 120 is connected to the state judgment module 130, and the state judgment module 130 is connected to the information acquisition and display module 140. The above-mentioned real-time monitoring and debugging method of the RISC-V chip is applied to the real-time monitoring and debugging device 100 of the RISC-V chip of the debugging device. The real-time monitoring and debugging device 100 of the RISC-V chip determines that the program is suspended and enters the debugging state by performing debugging state judgment, and directly obtains debugging information without parsing, has a simple structure, and improves the development and debugging efficiency.

[0077] like Figure 4 As shown, the debugging device also includes a debugger, which is connected to the display device via Bluetooth, WiFi, or a network cable. The display device is a mobile phone or a central control PC. For example, the displayed content is "helloworld". When the display device is a mobile phone, it is connected via Bluetooth or WiFi. When the display device is a central control console / computer, it is connected via a network cable.

[0078] It should also be noted that: when the device provided in the above embodiment realizes its function, only the division of the above functional modules is used as an example. In actual application, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0079] The present application also discloses an electronic device. Figure 5 , Figure 5 The electronic device 500 may include: at least one processor 501 , at least one network interface 504 , a user interface 503 , a memory 505 , and at least one communication bus 502 .

[0080] The communication bus 502 is used to realize the connection and communication between these components.

[0081] The user interface 503 may include a display screen (Display) and a camera (Camera). Optionally, the user interface 503 may also include a standard wired interface and a wireless interface.

[0082] The network interface 504 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0083] Among them, the processor 501 may include one or more processing cores. The processor 501 uses various interfaces and lines to connect various parts in the entire server, and executes various functions of the server and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 505, and calling data stored in the memory 505. Optionally, the processor 501 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 501 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 501, and it can be implemented separately through a chip.

[0084] Among them, the memory 505 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 505 includes a non-transitory computer-readable storage medium. The memory 505 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 505 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 505 may also be optionally at least one storage device located away from the aforementioned processor 501. Refer to Figure 5 , as a computer storage medium, the memory 505 may include an operating system, a network communication module, a user interface module, and an application program for a real-time monitoring and debugging method of a RISC-V chip.

[0085] exist Figure 5In the electronic device 500 shown, the user interface 503 is mainly used to provide an input interface for the user and obtain the data input by the user; and the processor 501 can be used to call the application program of a real-time monitoring and debugging method of a RISC-V chip stored in the memory 505, and when executed by one or more processors 501, the electronic device 500 executes one or more methods in the above-mentioned embodiments. It should be noted that for the aforementioned method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited to the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required for the present application.

[0086] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0088] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0089] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0090] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: various media that can store program codes, such as USB flash drives, mobile hard drives, magnetic disks or optical disks.

[0091] The above are only exemplary embodiments of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification and the truth of practice, those skilled in the art will easily think of other embodiments of the present disclosure.

[0092] This application is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art not described in the present disclosure. The description and examples are to be regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. A real-time monitoring and debugging method for a RISC-V chip, characterized in that: Applied to a debugging device, the debugging device is connected to the RISC-V chip, and the method includes: Initialize the ebreakm bit of the debug mode control and status register, determine whether the ebreakm bit is modified, and if modified to the debug bit, execute the ebreak instruction, wherein the ebreakm bit is a bit in the debug mode control and status register, and is used to store whether to execute an interrupt, indicating the instruction of the debug bit; Read the pause bit of the RISC-V chip, and in the case of entering the debug state, modify the cause bit of the debug module status register and the debug mode control and status register, wherein the cause bit is a bit in the debug mode control and status register, and is used to store whether to execute a program interrupt to enter the debug state instruction; In the case where the value in the debug module status register indicates a pause, determining whether the value of the cause bit is a debug state, wherein the debug module status register includes an allhalted bit and an anyhalted bit, and the value in the debug module status register is a value corresponding to the allhalted bit and the anyhalted bit; When the value of the cause bit indicates a debugging state, the debugging information in the RISC-V chip is directly obtained and displayed.

2. The method according to claim 1, characterized in that After directly acquiring the debugging information in the RISC-V chip and displaying it, the method further includes: The value of the program counter is updated according to the address of the next instruction of the ebreak instruction, and the updated value of the program counter points to the execution program.

3. The method according to claim 1, characterized in that: The initialization of the debug mode control and ebreakm bit of the status register includes: If the ebreakm bit does not exist, create the ebreakm bit to store the value corresponding to the read ebreakm bit; When the ebreakm bit exists, the value corresponding to the read ebreakm bit is directly stored.

4. The method according to claim 1, characterized in that After determining whether the value of the cause bit is in a debugging state, the method includes: When the value of the cause bit indicates a non-debugging state, the value of the program counter is modified, and the step of reading the pause bit of the RISC-V chip is performed. When entering the debugging state, the cause bits of the debug module status register and the debug mode control and status register are modified.

5. The method according to claim 1, characterized in that The modifying the cause bit of the debug module status register and the debug mode control and status register comprises: The value corresponding to the allhalted bit and the value corresponding to the anyhalted bit are both set to 1, and the corresponding allhalted bit and the anyhalted bit are written.

6. The method according to claim 1, characterized in that After modifying the debug module status register, the method includes: When the value in the debug module status register indicates non-pause, the value of the program counter is modified, and the step of reading the pause bit of the RISC-V chip is performed. When entering the debug state, the cause bit of the debug module status register and the debug mode control and status register is modified.

7. A real-time monitoring and debugging device for a RISC-V chip, characterized in that: Applied to a debugging device, the debugging device is connected to the RISC-V chip, and the device comprises: an initialization judgment module, used for initializing the ebreakm bit of the debug mode control and status register, judging whether the ebreakm bit is modified, and executing the ebreak instruction when it is modified to the debug bit, wherein the ebreakm bit is a bit in the debug mode control and status register, used for storing whether to execute an interrupt, indicating the instruction of the debug bit; A data reading and configuration module, used to read the pause bit of the RISC-V chip, and modify the cause bit of the debug module status register and the debug mode control and status register when entering the debug state, wherein the cause bit is a bit in the debug mode control and status register, and is used to store whether to execute a program interrupt to enter the debug state instruction; a state determination module, configured to determine whether the value of the cause bit is a debug state when the value in the debug module state register indicates a pause, wherein the debug module state register includes an allhalted bit and an anyhalted bit, and the value in the debug module state register is a value corresponding to the allhalted bit and the anyhalted bit; The information acquisition and display module is used to directly acquire the debugging information in the RISC-V chip and display it when the value of the cause bit indicates a debugging state.

8. The device according to claim 7, characterized in that The debugging device also includes a debugger, which is connected to a display device via Bluetooth, WiFi, or a network cable. The display device is a mobile phone or a central control PC.

9. An electronic device, characterized in that: It includes a processor, a memory, a user interface, a communication bus and a network interface, wherein the processor, the memory, the user interface and the network interface are respectively connected to the communication bus, the memory is used to store instructions, the user interface and the network interface are used to communicate with other devices, and the processor is used to execute the instructions stored in the memory so that the electronic device executes the method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed, the method according to any one of claims 1 to 6 is performed.

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