Reconfigurable cryptographic coprocessor, baseboard management controller and target data processing method

Abstract

An embodiment of the present application provides a reconfigurable cryptographic coprocessor, a baseboard management controller, and a method for processing target data, wherein the reconfigurable cryptographic coprocessor includes: a first processor, connected to a second processor in a baseboard management controller, and used to send demand information sent by the second processor to an intelligent control module, wherein the demand information is used to indicate a target algorithm for processing the target data; an intelligent control module, connected to a data module and the first processor, and used to adjust the shared computing resources of the reconfigurable cryptographic computing module according to the demand information, and send the target data sent by the data module to the reconfigurable cryptographic computing module; a reconfigurable cryptographic computing module, used to process the target data using the first computing resources obtained after adjustment, wherein the first computing resources include: fixed computing resources in the reconfigurable cryptographic computing module, and shared computing resources after adjustment.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and in particular, to a reconfigurable cryptographic coprocessor, a baseboard management controller, and a method for processing target data. Background Art

[0002] In the related art, an engine core module is proposed, which integrates the AES algorithm and the SM4 algorithm and is applied to the BMC chip. Its architecture is as follows: Figure 1 As shown. The AES algorithm engine unit integrates the three independent AES encryption / decryption operation units and AES key expansion units of AES-128, AES-192, and AES-256 algorithms, as well as the AES column obfuscation unit and AES byte replacement unit. The AES byte replacement unit is mainly used for byte replacement operations. The state matrix of the AES column obfuscation unit after row shift is multiplied with a fixed matrix to obtain the obfuscated state matrix to implement column obfuscation transformation. The SM4 algorithm engine includes the SM4 byte replacement unit, the SM4 encryption / decryption operation unit, and the SM4 key expansion unit. The SM4 byte replacement unit is used for byte replacement operations. The SM4 encryption / decryption operation unit integrates a 32-stage pipeline round function. The round key generated by the SM4 key expansion module is used by the SM4 encryption / decryption operation unit.

[0003] The algorithm engine core module has an AES algorithm engine and an SM4 algorithm engine, which can accelerate the calculation of the two algorithms separately. Both the AES algorithm and the SM4 algorithm are symmetric encryption algorithms, and some of the calculations of the algorithms are similar. The algorithm engine core module calculates the two algorithms separately, which does not fully utilize the characteristics of the algorithms, resulting in hardware resource constraints, making the algorithm engine core module have a larger area and higher power consumption.

[0004] Regarding the related technology, in the existing BMC chip, the hardware acceleration computing units of the AES algorithm and the SM4 algorithm are independent of each other, have a large area and high power consumption, and no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a reconfigurable cryptographic coprocessor, a baseboard management controller, and a method for processing target data, so as to at least solve the problem in the related art that in the existing BMC chip, the hardware acceleration computing units of the AES algorithm and the SM4 algorithm are independent of each other, have a large area and high power consumption.

[0006] According to one embodiment of the present application, a reconfigurable cryptographic coprocessor is provided, including: a first processor, connected to a second processor in a baseboard management controller, and used to send demand information sent by the second processor to an intelligent control module, wherein the demand information is used to indicate a target algorithm for processing target data, and the target data includes: a key, data to be encrypted or data to be decrypted; the intelligent control module, connected to a data module and the first processor, and used to adjust the shared computing resources of a reconfigurable cryptographic computing module according to the demand information, and send the target data sent by the data module to the reconfigurable cryptographic computing module; the reconfigurable cryptographic computing module, used to process the target data by using a first computing resource obtained after adjustment, wherein the first computing resource includes: a fixed computing resource in the reconfigurable cryptographic computing module, and an adjusted shared computing resource.

[0007] In an exemplary embodiment, the reconfigurable cryptographic computing module includes: a first algorithm computing unit, used to calculate a first sub-algorithm of a first algorithm; a second algorithm computing unit, used to calculate a second sub-algorithm of a second algorithm; and a reconfigurable computing unit, connected to the first algorithm computing unit or the second algorithm computing unit, used to calculate a third sub-algorithm, wherein both the first algorithm and the second algorithm include the third sub-algorithm.

[0008] In an exemplary embodiment, the shared computing resources include a plurality of the reconfigurable computing units, and the intelligent control module is further used to: determine the target algorithm based on the requirement information, wherein the target algorithm includes one of the following: the first algorithm, the second algorithm, the first algorithm and the second algorithm; and, determine the second computing resources required for the target algorithm based on the requirement information, and adjust the shared computing resources of the reconfigurable cryptographic computing module based on the target algorithm and the second computing resources.

[0009] In an exemplary embodiment, the intelligent control module is also used to: when the target algorithm is the first algorithm, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit; when the target algorithm is the second algorithm, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit.

[0010] In an exemplary embodiment, the intelligent control module is also used to: when the target algorithm is the first algorithm and the second algorithm, determine the third computing resources required by the first algorithm and the fourth computing resources required by the second algorithm according to the demand information, wherein the second computing resources include the third computing resources and the fourth computing resources; and adjust the multiple reconfigurable computing units according to the third computing resources and the fourth computing resources.

[0011] In an exemplary embodiment, the intelligent control module is further used to: determine whether the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm based on the third computing resource and the fourth computing resource; when it is determined that the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm, control the first reconfigurable computing unit to switch to connect with the first algorithm computing unit, and control the second reconfigurable computing unit to switch to connect with the second algorithm computing unit, wherein the multiple reconfigurable computing units include the first reconfigurable computing unit and the second reconfigurable computing unit, and the ratio of the number of the first reconfigurable computing unit to the number of the second reconfigurable computing unit is determined based on the third computing resource and the fourth computing resource.

[0012] In an exemplary embodiment, the intelligent control module is also used to: determine the priority order of the first algorithm and the second algorithm according to the requirement information when it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm; and adjust the multiple reconfigurable computing units according to the priority order.

[0013] In an exemplary embodiment, the intelligent control module is also used to: when the priority order indicates that the priority of the first algorithm is higher than the priority of the second algorithm, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit; when it is determined that the execution of the first algorithm is completed, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit.

[0014] In an exemplary embodiment, the intelligent control module is also used to: when the priority order indicates that the priority of the second algorithm is higher than the priority of the first algorithm, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit; when it is determined that the execution of the second algorithm is completed, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit.

[0015] In an exemplary embodiment, the intelligent control module is also used to: determine a first data amount of data to be processed by the first algorithm and a second data amount of data to be processed by the second algorithm according to the requirement information when it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm; determine the ratio of the number of third reconfigurable computing units to that of fourth reconfigurable computing units according to the ratio of the first data amount to the second data amount, and control the third reconfigurable computing unit to switch to connect to the first algorithm computing unit, and control the fourth reconfigurable computing unit to switch to connect to the second algorithm computing unit.

[0016] In an exemplary embodiment, the plurality of reconfigurable computing units include: a plurality of groups of reconfigurable computing units, wherein the computing capabilities of each group of reconfigurable computing units in the plurality of groups of reconfigurable computing units are different.

[0017] In an exemplary embodiment, the first algorithm calculation unit includes: a first encryption / decryption calculation unit, used to encrypt the data to be encrypted through a first encryption algorithm, or, used to decrypt the data to be decrypted through a first decryption algorithm; a first key expansion unit, used to expand the key through a first expansion algorithm, wherein the first sub-algorithm includes the first encryption algorithm, the first decryption algorithm and the first expansion algorithm.

[0018] In an exemplary embodiment, the second algorithm calculation unit includes: a second encryption / decryption calculation unit, used to encrypt the data to be encrypted through a second encryption algorithm, or, used to decrypt the data to be decrypted through a second decryption algorithm; a second key expansion unit, used to expand the key through a second expansion algorithm, wherein the second sub-algorithm includes the second encryption algorithm, the second decryption algorithm and the second expansion algorithm.

[0019] In an exemplary embodiment, the reconfigurable cryptographic computing module is also used to: process the target data through the first computing resource to obtain a processing result, wherein the processing result includes one of the following: an encryption result, a decryption result; and store the processing result in the data module.

[0020] According to another embodiment of the present application, a baseboard management controller is provided, including: a second processor connected to a reconfigurable cryptographic coprocessor, for receiving a demand instruction, parsing the demand instruction, obtaining demand information, and sending the demand information to the reconfigurable cryptographic coprocessor, wherein the demand instruction is used to indicate processing of target data, and the demand information is used to indicate a target algorithm for processing the target data, and the target data includes: a key, data to be encrypted or data to be decrypted; the reconfigurable cryptographic coprocessor is used to adjust the shared computing resources in the reconfigurable cryptographic coprocessor according to the demand information, and process the target data through the first computing resources obtained after adjustment, wherein the first computing resources include: fixed computing resources of the reconfigurable cryptographic coprocessor, and shared computing resources after adjustment.

[0021] According to another embodiment of the present application, a method for processing target data is provided, comprising: receiving demand information sent by a second processor in a baseboard management controller, wherein the demand information is used to indicate a target algorithm for processing the target data, and the target data comprises: a key, data to be encrypted or data to be decrypted; adjusting the shared computing resources of the reconfigurable cryptographic coprocessor according to the demand information; processing the target data by using a first computing resource obtained after adjustment, wherein the first computing resource comprises: a fixed computing resource of the reconfigurable cryptographic coprocessor and an adjusted shared computing resource.

[0022] In an exemplary embodiment, the target data is processed by the first computing resource obtained after adjustment, including: processing the target data by the first computing resource to obtain a processing result, wherein the processing result includes one of the following: an encryption result, a decryption result; storing the processing result in a data module in the reconfigurable cryptographic coprocessor.

[0023] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0024] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0025] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0026] Through the present application, when the first processor receives the demand information sent by the baseboard management controller for indicating the target algorithm for processing the target data, the demand information is forwarded to the intelligent control module, wherein the target data includes: a key, data to be encrypted or data to be decrypted; the intelligent control module adjusts the shared computing resources of the reconfigurable cryptographic computing module according to the demand information, and then sends the target data sent by the data module to the reconfigurable cryptographic computing module for processing, and the reconfigurable cryptographic computing module processes the target data through the first computing resources obtained after adjustment, and the first computing resources include the fixed computing resources of the reconfigurable cryptographic computing module and the adjusted shared computing resources; by adopting the above scheme, the calculation of the similar parts of the AES algorithm and the SM4 algorithm is completed by the reconfigurable computing unit, so that the two algorithms can share the resources of the reconfigurable computing unit to complete the encryption and decryption work, thereby reducing the area and power consumption of the cryptographic computing module; thereby solving the problem in the related art that in the existing BMC chip, the hardware acceleration computing units of the AES algorithm and the SM4 algorithm are independent of each other, have a large area and high power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is an architecture diagram of an engine core module according to an embodiment of the present application;

[0028] Figure 2 is a hardware structure block diagram of a method for processing target data according to an embodiment of the present application;

[0029] Figure 3 This is a schematic diagram of the encryption and decryption process of an AES-128 algorithm according to an embodiment of the present application;

[0030] Figure 4 This is a schematic diagram of the encryption and decryption process of a key expansion method of an AES-128 algorithm according to an embodiment of the present application;

[0031] Figure 5 It is a schematic diagram of the encryption and decryption process of an SM4 algorithm according to an embodiment of the present application;

[0032] Figure 6 It is a schematic diagram of the encryption and decryption process of a key expansion method of an SM4 algorithm according to an embodiment of the present application;

[0033] Figure 7 is a structural block diagram of a reconfigurable cryptographic coprocessor according to an embodiment of the present application;

[0034] Figure 8 is a structural block diagram of a reconfigurable cryptographic computing module according to an embodiment of the present application;

[0035] Fig. 9is an architectural diagram of a RISC-V reconfigurable cryptographic coprocessor according to an embodiment of the present application;

[0036] Fig.10 is a structural block diagram of another reconfigurable cryptographic computing module according to an embodiment of the present application;

[0037] Fig.11 is a structural block diagram of a baseboard management controller according to an embodiment of the present application;

[0038] Fig.12 is a structural block diagram of another baseboard management controller according to an embodiment of the present application;

[0039] Fig.13 is a flow chart of a method for processing target data according to an embodiment of the present application;

[0040] Fig.14 It is a flowchart of another method for processing target data according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0043] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 2 1 is a hardware structure block diagram of a computer terminal of a method for processing target data in an embodiment of the present application. Figure 2 As shown, the computer terminal may include one or more ( Figure 2 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 2 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 2 More or fewer components as shown, or with Figure 2 Different configurations are shown.

[0044] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the mapping relationship in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0045] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0046] The following is an explanation of the professional terms used in this application:

[0047] BMC, Baseboard management controller, baseboard management controller;

[0048] AES, Advanced Encryption Standard, Advanced Encryption Standard.

[0049] 1. BMC chip, the full name is Baseboard Management Controller, Chinese name is Baseboard Management Controller. It is an important management chip in the server, responsible for server hardware monitoring (BMC chip can monitor various hardware parameters of the server, including voltage, temperature, fan speed, power status, etc.), fault management (BMC chip can detect and record server faults), remote control (BMC chip allows administrators to remotely control the server, including power on, power off, restart, etc.) and other functions.

[0050] The BMC chip is usually integrated on the server motherboard. It has an independent processor and memory and can run independently of the server operating system. The BMC chip communicates with the outside world through a dedicated management network interface, allowing administrators to remotely access and manage the server.

[0051] The BMC chip is very important for the stability and reliability of the server. It can help administrators detect and solve server failures in a timely manner, and remotely manage and maintain the server, thereby improving the availability and security of the server.

[0052] 2. BMC chip encryption and decryption module: The encryption and decryption module of the BMC chip is an important security component. It can protect the data communicated between the BMC and other devices (such as server management data and firmware update data), protect sensitive data stored in the BMC (such as passwords and certificates), and provide a secure boot function for the BMC. The encryption and decryption module of the BMC chip is very important for the security of servers and other devices, and can improve the stability and security of the server.

[0053] The BMC encryption and decryption module usually supports multiple encryption algorithms, including AES algorithm, RSA algorithm, SHA algorithm, etc.

[0054] 3. Symmetric encryption algorithm: According to the different types of encryption keys, encryption algorithms can be divided into symmetric encryption algorithms and asymmetric encryption algorithms. Symmetric encryption algorithms use the same key in the encryption and decryption process. The encryption and decryption speeds are very fast and are suitable for applications with frequent data transmission and large data transmission volumes. Common symmetric encryption algorithms include AES algorithm, SM4 algorithm, etc.

[0055] 3.1 AES algorithm: AES (Advanced Encryption Standard) algorithm is a symmetric encryption algorithm. The plaintext block length of AES algorithm is fixed at 128 bits, and the key length can be 128 bits, 192 bits or 256 bits. Depending on the length of the key, the corresponding number of transformation rounds is 10, 12 or 14 rounds.

[0056] The encryption and decryption process of the AES-128 algorithm (key is 128 bits) is as follows Figure 3 As shown in the figure, the number of encryption rounds is 10. The first 9 rounds (K1-K9) consist of 4 different transformations: byte replacement, row shift, column confusion, and round key addition. The last round, the 10th round (K10), has no column confusion. The decryption process is the inverse operation of the encryption process. The order of the round keys corresponding to the encryption and decryption processes is just the opposite.

[0057] The AES-128 algorithm performs 11 rounds of key addition operations, including the initial key and 10 round keys. The key expansion method of the AES-128 algorithm is as follows: Figure 4 As shown, Figure 4 (a) includes the initial key and the extended round key of the AES-128 algorithm. The initial key of the AES-128 algorithm is 128 bits. K0, K1, ..., K15 represent one byte of the initial key respectively. The initial key is represented by four 32-bit words after arrangement, which are recorded as w0, w1, w2, w3 respectively. The extended round key consists of w4, w5, ..., w43, where every four 32-bit words constitute a round key. Figure 4 (b) is the expansion process of each round of the round key, taking w0, w1, w2, w3 to generate w4, w5, w6, w7 as an example: w0 and w3 after T transformation (T transformation includes three steps: word loop, byte replacement, and round constant XOR) are XORed to generate w4; w1 and w4 are XORed to generate w5; w2 and w5 are XORed to generate w6; w3 and w6 are XORed to generate w7. Repeat the above process many times to generate 10 expanded round keys.

[0058] 3.2, SM4 algorithm: SM4 algorithm is a symmetric encryption algorithm. SM4 algorithm uses 128 bit key and block size. It is a block cipher algorithm based on round function structure, which realizes encryption and decryption operations by repeatedly executing the same round function structure.

[0059] Figure 5 (a) is the flowchart of the SM4 encryption process. Assume that the input 128-bit plaintext is (X0, X1, X2, X3), where X0, X1, X2, and X3 are all 32-bit data, also known as words. After the first round of operations, the fifth word X4 = F(X0, X1, X2, X3, rk0) is generated, where rk0 is the round key of the first round of encryption. Continue the second round of operations to obtain the sixth word X5 = F(X1, X2, X3, X4, rk1); ...; for X i , X i+1 , X i+2 , X i+3 By rk i Perform the i+1th round of operations and get X i+4 . And so on, a total of 32 rounds are performed, and finally 36 words are obtained. The four words obtained in the last round (X 32 ,X 33 ,X 34 ,X 35 ) are sorted in reverse order to obtain the output ciphertext (Y0, Y1, Y2, Y3) = (X 35 , X 34 , X 33 , X 32 ).

[0060] The T transformation of the round function of the SM4 algorithm is as follows Figure 5 As shown in (b), it consists of a nonlinear transformation τ and a linear transformation L. The nonlinear transformation τ consists of four parallel S-boxes, and the linear transformation includes cyclic shift and XOR calculation, which can specifically include the following steps:

[0061] 1. S-box substitution: In this step, each byte A (a0, a1, a2, a3) in the data block is replaced by a nonlinear transformation (usually an S-box) to obtain B (b0, b1, b2, b3) to increase the security of the algorithm.

[0062] 2. Shift Rows: The rows in the data block are circularly shifted to rearrange the data and increase the diffusion effect.

[0063] 3. Add Round Key: At the end of each round, the round key is XORed with the data block to introduce the key information.

[0064] The key expansion of the SM4 algorithm is as follows Figure 6 As shown in (a), 32 round keys for encryption or decryption are generated. The specific process includes: the SM4 algorithm receives a 128-bit initial key MK, copies it to a 32-byte array, and obtains MK0, MK1, MK2, and MK3; performs a series of permutation operations on it through FK0, FK1, FK2, and FK3 respectively to generate a new 32-byte array; from the permuted key array, a round key is extracted every 4 bytes, and a total of 32 rounds are generated. The round function of key expansion (such as Figure 6 (b)) and the round function in the encryption process (as shown in Figure 5 (b) (shown) is the same in structure, both of which include nonlinear transformation and linear transformation. The nonlinear transformation part is exactly the same as the nonlinear transformation part in the encryption or decryption process, and the cyclic shift of the linear transformation part is different.

[0065] The BMC chip is used to remotely manage and maintain the server, ensuring the stability and security of the server. The encryption and decryption module of the BMC chip is used to protect the data communicated between the BMC and other devices, and to protect sensitive data stored in the BMC, which can improve the stability and security of the server.

[0066] With the development of BMC chips, functional requirements and performance requirements are gradually increasing. Its encryption and decryption modules need to support both the AES algorithm and the SM4 algorithm in symmetric encryption algorithms to adapt to different application scenarios. In common encryption and decryption modules, the hardware acceleration computing units of the AES algorithm and the SM4 algorithm are independent of each other, and their reusable characteristics are not fully utilized, resulting in a large area and high power consumption.

[0067] In order to solve the above problems, a reconfigurable cryptographic coprocessor is provided in this embodiment. Figure 7 is a structural block diagram of a reconfigurable cryptographic coprocessor according to an embodiment of the present application, such as Figure 7 As shown, the reconfigurable cryptographic coprocessor includes:

[0068] The first processor 72 is connected to the second processor in the baseboard management controller, and is used to send the demand information sent by the second processor to the intelligent control module 74, wherein the demand information is used to indicate the target algorithm for processing the target data, and the target data includes: a key, data to be encrypted or data to be decrypted;

[0069] The intelligent control module 74 is connected to the data module and the first processor 72, and is used to adjust the shared computing resources of the reconfigurable cryptographic computing module 76 according to the demand information, and send the target data sent by the data module to the reconfigurable cryptographic computing module 76;

[0070] The reconfigurable cryptographic computing module 76 is used to process the target data through the first computing resources obtained after adjustment, wherein the first computing resources include: fixed computing resources in the reconfigurable cryptographic computing module and shared computing resources after adjustment.

[0071] Through the present application, when the first processor receives the demand information sent by the baseboard management controller for indicating the target algorithm for processing the target data, the demand information is forwarded to the intelligent control module, wherein the target data includes: a key, data to be encrypted or data to be decrypted; the intelligent control module adjusts the shared computing resources of the reconfigurable cryptographic computing module according to the demand information, and then sends the target data sent by the data module to the reconfigurable cryptographic computing module for processing, and the reconfigurable cryptographic computing module processes the target data through the first computing resources obtained after adjustment, and the first computing resources include the fixed computing resources of the reconfigurable cryptographic computing module and the adjusted shared computing resources; by adopting the above scheme, the calculation of the similar parts of the AES algorithm and the SM4 algorithm is completed by the reconfigurable computing unit, so that the two algorithms can share the resources of the reconfigurable computing unit to complete the encryption and decryption work, thereby reducing the area and power consumption of the cryptographic computing module; thereby solving the problem in the related art that in the existing BMC chip, the hardware acceleration computing units of the AES algorithm and the SM4 algorithm are independent of each other, have a large area and high power consumption.

[0072] Furthermore, the reconfigurable cryptographic computing module includes: a first algorithm computing unit, used to calculate a first sub-algorithm of a first algorithm; a second algorithm computing unit, used to calculate a second sub-algorithm of a second algorithm; and a reconfigurable computing unit, connected to the first algorithm computing unit or the second algorithm computing unit, used to calculate a third sub-algorithm, wherein both the first algorithm and the second algorithm include the third sub-algorithm.

[0073] The architecture of the reconfigurable cryptographic computing module 76 is as follows: Figure 8 As shown, it includes a first algorithm calculation unit 82, a second algorithm calculation unit 84, and a reconfigurable calculation unit 86. Optionally, in the present application, the first algorithm may be an AES algorithm, and the second algorithm may be an SM4 algorithm; the first algorithm calculation unit is used to calculate the first sub-algorithm of the AES algorithm, the second algorithm calculation unit is used to calculate the second sub-algorithm of the SM4 algorithm, and the reconfigurable calculation unit is used to calculate the third sub-algorithm included in both the AES algorithm and the SM4 algorithm. That is, the first algorithm calculation unit and the second algorithm calculation unit are used to implement the calculation of the different parts of the two algorithms, and the reconfigurable calculation unit is used to implement the calculation of the similar parts of the two algorithms.

[0074] Through the above embodiments, the calculation of similar parts of the two algorithms is implemented through the reconfigurable computing unit, which saves computing resources and reduces hardware costs.

[0075] Optionally, the reconfigurable cryptographic computing module may also include a third algorithm computing unit, a fourth algorithm computing unit, etc., which are respectively used to calculate part of the third algorithm and the fourth algorithm, such as the SHA algorithm, etc.; correspondingly, the reconfigurable computing unit correspondingly integrates the computing power of similar parts of multiple algorithms, that is, the reconfigurable cryptographic coprocessor provided in the present application is not limited to coordinating two algorithms, but can also coordinate a larger number of algorithms, thereby adapting to the needs of more application scenarios.

[0076] Optionally, an embodiment of the present application provides a RISC-V reconfigurable cryptographic coprocessor architecture, such as Fig. 9 As shown, it includes a RISC-V processor (equivalent to the first processor mentioned above), an intelligent control module, a data module and a reconfigurable cryptographic computing module.

[0077] The RISC-V processor receives signals from the BMC chip processor and controls the reconfigurable cryptographic coprocessor to implement encryption and decryption calculations of the AES and SM4 algorithms. RISC-V instructions can be customized based on the reconfigurable computing characteristics of the AES and SM4 algorithms to improve the overall performance of the coprocessor.

[0078] The data module is used to store data of AES and SM4 algorithms, including keys, encrypted data, and decrypted data.

[0079] The intelligent control module configures the reconfigurable cryptographic calculation module, selects the type of algorithm to be executed, and controls the input of data required for the algorithm calculation and the output of the results obtained by the algorithm calculation.

[0080] The reconfigurable cryptographic computing module includes an AES algorithm computing unit, an SM4 algorithm computing unit, and a reconfigurable computing unit. The reconfigurable computing unit implements the calculation of modules (such as byte replacement) that exist in both the AES algorithm and the SM4 algorithm. The different calculations of the two algorithms are implemented by the AES algorithm computing unit and the SM4 algorithm computing unit respectively.

[0081] Optionally, the shared computing resources include multiple reconfigurable computing units, and the intelligent control module is further used to: determine the target algorithm based on the requirement information, wherein the target algorithm includes one of the following: the first algorithm, the second algorithm, the first algorithm and the second algorithm; and, determine the second computing resources required for the target algorithm based on the requirement information, and adjust the shared computing resources of the reconfigurable cryptographic computing module based on the target algorithm and the second computing resources.

[0082] First, the target algorithm to be used is determined according to the demand information, which may specifically include the following situations: only the first algorithm needs to be used, only the second algorithm needs to be used, or both the first algorithm and the second algorithm need to be used; at the same time, the second computing resources required by the target algorithm are determined according to the demand information, so as to adjust the shared computing resources of the reconfigurable cryptographic computing module according to the type of the target algorithm and the second computing resources.

[0083] Through this embodiment, shared computing resources are flexibly scheduled according to different usage scenarios, so that only fewer computing resources are needed to complete the computing work of the two algorithms.

[0084] Optionally, the intelligent control module is also used to: when the target algorithm is the first algorithm, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit; when the target algorithm is the second algorithm, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit.

[0085] If the requirement information indicates that only the first algorithm needs to be used, the reconfigurable cryptographic computing module is controlled to switch all reconfigurable computing units to be connected to the first algorithm computing unit for use by the first algorithm. If the requirement information indicates that only the second algorithm needs to be used, the reconfigurable cryptographic computing module is controlled to switch all reconfigurable computing units to be connected to the second algorithm computing unit for use by the second algorithm.

[0086] Optionally, the intelligent control module is also used to: when the target algorithm is the first algorithm and the second algorithm, determine the third computing resources required for the first algorithm and the fourth computing resources required for the second algorithm according to the demand information, wherein the second computing resources include the third computing resources and the fourth computing resources; and adjust the multiple reconfigurable computing units according to the third computing resources and the fourth computing resources.

[0087] If the demand information indicates that both the first algorithm and the second algorithm need to be used, the shared computing resources need to be further reasonably allocated to better complete the encryption and decryption tasks. The third computing resources required by the first algorithm and the fourth computing resources required by the second algorithm are determined according to the demand information, and then the multiple reconfigurable computing units are adjusted according to the third computing resources and the fourth computing resources.

[0088] Through the above embodiments, shared computing resources are reasonably allocated according to different requirements corresponding to usage scenarios, so as to complete more computing tasks with fewer computing resources.

[0089] Furthermore, the intelligent control module is also used to: determine whether the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm based on the third computing resource and the fourth computing resource; when it is determined that the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm, control the first reconfigurable computing unit to switch to connect with the first algorithm computing unit, and control the second reconfigurable computing unit to switch to connect with the second algorithm computing unit, wherein the multiple reconfigurable computing units include the first reconfigurable computing unit and the second reconfigurable computing unit, and the ratio of the number of the first reconfigurable computing unit to the number of the second reconfigurable computing unit is determined based on the third computing resource and the fourth computing resource.

[0090] First, determine whether the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm based on the third computing resources and the fourth computing resources. If supported, allocate the multiple reconfigurable computing units based on the third computing resources and the fourth computing resources, switch the first reconfigurable computing unit to connect with the first algorithm computing unit, and switch the second reconfigurable computing unit to connect with the second algorithm computing unit, so as to support the operation of the first algorithm and the second algorithm through the allocated shared computing resources.

[0091] Based on the above steps: the intelligent control module is also used to: when it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm, determine the priority order of the first algorithm and the second algorithm according to the requirement information; and adjust the multiple reconfigurable computing units according to the priority order.

[0092] If the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm, in an optional embodiment, the priority order of executing the first algorithm and the second algorithm is determined according to the demand information, and then the multiple reconfigurable computing units are allocated and adjusted according to the priority order.

[0093] Optionally, the intelligent control module is also used to: when the priority order indicates that the priority of the first algorithm is higher than the priority of the second algorithm, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit; when it is determined that the execution of the first algorithm is completed, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit.

[0094] If the priority order indicates that the priority of the first algorithm is higher than the priority of the second algorithm, the multiple reconfigurable computing units are controlled to switch to the connection with the first algorithm computing unit first; then the first algorithm is monitored to see whether it has been executed. If it has been executed, the multiple reconfigurable computing units are immediately controlled to switch to the connection with the second algorithm computing unit to continue executing the second algorithm.

[0095] Optionally, the intelligent control module is also used to: when the priority order indicates that the priority of the second algorithm is higher than the priority of the first algorithm, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit; when it is determined that the execution of the second algorithm is completed, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit.

[0096] If the priority order indicates that the priority of the second algorithm is higher than that of the first algorithm, the multiple reconfigurable computing units are controlled to switch to connect with the second algorithm computing unit first; then it is monitored whether the second algorithm is executed. If the execution is completed, the multiple reconfigurable computing units are immediately controlled to switch to connect with the first algorithm computing unit to continue executing the first algorithm.

[0097] Through the above embodiments, when the reconfigurable cryptographic computing module does not support the simultaneous execution of multiple algorithms, resources are scheduled according to the priorities of the multiple algorithms to ensure that the tasks of the two algorithms are successfully completed.

[0098] Optionally, the intelligent control module is also used to: determine a first data amount of data to be processed by the first algorithm and a second data amount of data to be processed by the second algorithm according to the requirement information when it is determined that the reconfigurable cryptographic computing module does not support simultaneous execution of the first algorithm and the second algorithm; determine the ratio of the number of third reconfigurable computing units to that of fourth reconfigurable computing units according to the ratio of the first data amount to the second data amount, and control the third reconfigurable computing unit to switch to connect with the first algorithm computing unit, and control the fourth reconfigurable computing unit to switch to connect with the second algorithm computing unit.

[0099] In another optional embodiment, if it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm, the first data amount of the data to be processed by the first algorithm and the second data amount of the data to be processed by the second algorithm can also be determined based on the demand information, and then the ratio of the number of the third reconfigurable computing unit to the fourth reconfigurable computing unit is determined based on the first data amount and the second data amount, and then the third reconfigurable computing unit is controlled to be connected to the first algorithm computing unit, and the fourth reconfigurable computing unit is controlled to be connected to the second algorithm computing unit.

[0100] It should be noted that the above-mentioned reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm, which can be understood as the reconfigurable cryptographic computing module cannot support the execution of the first algorithm and the second algorithm at a higher execution rate at the same time. In this embodiment, the reconfigurable computing units are allocated according to the first data volume and the second data volume in order to sacrifice the execution rate to a certain extent to ensure the smooth completion of the two algorithms.

[0101] Through the above embodiment, when the reconfigurable cryptographic computing module does not support the simultaneous execution of multiple algorithms, the resources of the reconfigurable computing unit are allocated according to the amount of data to be processed by the multiple algorithms to ensure that the tasks of the two algorithms are successfully completed.

[0102] Optionally, the multiple reconfigurable computing units include: multiple groups of reconfigurable computing units, wherein the computing capabilities of each group of reconfigurable computing units in the multiple groups of reconfigurable computing units are different.

[0103] The reconfigurable computing unit includes a plurality of reconfigurable computing units, and the plurality of reconfigurable computing units may be all the same or may be divided into a plurality of groups, such as Fig.10 As shown in the figure, the reconfigurable computing units are divided into two groups, and the computing capabilities of the multiple groups of reconfigurable computing units are different. The calculations of similar parts of the AES algorithm and the SM4 algorithm are jointly completed by the multiple groups of reconfigurable computing units.

[0104] Optionally, the first algorithm calculation unit includes: a first encryption / decryption calculation unit, used to encrypt the data to be encrypted through a first encryption algorithm, or, used to decrypt the data to be decrypted through a first decryption algorithm; a first key expansion unit, used to expand the key through a first expansion algorithm, wherein the first sub-algorithm includes the first encryption algorithm, the first decryption algorithm and the first expansion algorithm.

[0105] Optionally, the second algorithm calculation unit includes: a second encryption / decryption calculation unit, used to encrypt the data to be encrypted through a second encryption algorithm, or, used to decrypt the data to be decrypted through a second decryption algorithm; a second key expansion unit, used to expand the key through a second expansion algorithm, wherein the second sub-algorithm includes the second encryption algorithm, the second decryption algorithm and the second expansion algorithm.

[0106] like Fig.10 As shown, the reconfigurable cryptographic computing module includes an AES algorithm computing unit (i.e., the first algorithm computing unit mentioned above), an SM4 algorithm computing unit (i.e., the second algorithm computing unit mentioned above), and a reconfigurable computing unit. The AES algorithm and the SM4 algorithm include encryption / decryption computing and key expansion computing, so the AES algorithm computing unit and the SM4 algorithm computing unit are both composed of an encryption / decryption computing unit and a key expansion unit to realize the calculation of different parts of the two algorithms. The reconfigurable computing unit realizes the calculation of similar parts of the AES algorithm and the SM4 algorithm, and is configured accordingly according to the required algorithm type.

[0107] based on Fig.10 The architecture of the reconfigurable cryptographic computing module shown in FIG. 1 shows that when the computing resource requirements of the AES algorithm and the SM4 algorithm are different, the intelligent control module will reconfigure the computing unit (i.e. Fig.10 For example, when encryption / decryption calculations require more computing resources than key expansion calculations, more reconfigurable computing units are used for encryption / decryption calculations; when only encryption / decryption calculations are performed, all reconfigurable computing units are used for encryption / decryption calculations; if the application requires the calculation of both the AES algorithm and the SM4 algorithm, then according to the amount of data to be processed, a part of the reconfigurable computing units can be used for the AES algorithm calculation, and the other part can be used for the SM4 algorithm calculation.

[0108] Optionally, the reconfigurable cryptographic computing module is further used to: process the target data through the first computing resource to obtain a processing result, wherein the processing result includes one of the following: an encryption result, a decryption result; and store the processing result in the data module.

[0109] After completing the allocation of computing resources, the target data is encrypted / decrypted according to the first resource finally allocated to the target algorithm to obtain a processing result, which is an encryption result or a decryption result; then the processing result is stored in the data module to complete the encryption / decryption process.

[0110] According to another embodiment of the present application, a baseboard management controller is provided, such as Fig.11 As shown, including:

[0111] The second processor 112 is connected to the reconfigurable cryptographic coprocessor 114, and is used to receive a demand instruction, parse the demand instruction, obtain demand information, and send the demand information to the reconfigurable cryptographic coprocessor 114, wherein the demand instruction is used to indicate processing of target data, and the demand information is used to indicate a target algorithm for processing the target data, and the target data includes: a key, data to be encrypted, or data to be decrypted;

[0112] The reconfigurable cryptographic coprocessor 114 is used to adjust the shared computing resources in the reconfigurable cryptographic coprocessor 114 according to the demand information, and process the target data through the first computing resources obtained after the adjustment, wherein the first computing resources include: the fixed computing resources of the reconfigurable cryptographic coprocessor 114 and the adjusted shared computing resources.

[0113] Through the above-mentioned baseboard management controller, the demand instruction sent by the user is first parsed by the second processor to obtain demand information for indicating the target algorithm for processing the target data; then the reconfigurable cryptographic coprocessor adjusts the shared computing resources according to the demand information, and processes the target data through the first computing resources obtained after the adjustment, and the first computing resources include: fixed computing resources of the reconfigurable cryptographic coprocessor, and shared computing resources after the adjustment; the baseboard management controller is adopted to solve the problem in the related technology that the hardware acceleration computing units of the AES algorithm and the SM4 algorithm in the existing BMC chip are independent of each other, have a large area and high power consumption.

[0114] Optionally, the above-mentioned reconfigurable cryptographic coprocessor 114 includes: a first processor, connected to the second processor, and used to send the demand information sent by the second processor to an intelligent control module; the intelligent control module, connected to the data module and the first processor, and used to adjust the shared computing resources of the reconfigurable cryptographic computing module according to the demand information, and send the target data sent by the data module to the reconfigurable cryptographic computing module; the reconfigurable cryptographic computing module is used to process the target data through the first computing resources obtained after adjustment.

[0115] Optionally, the reconfigurable cryptographic computing module includes: a first algorithm computing unit, used to calculate a first sub-algorithm of a first algorithm; a second algorithm computing unit, used to calculate a second sub-algorithm of a second algorithm; and a reconfigurable computing unit, connected to the first algorithm computing unit or the second algorithm computing unit, used to calculate a third sub-algorithm, wherein both the first algorithm and the second algorithm include the third sub-algorithm.

[0116] Optionally, the shared computing resources include multiple reconfigurable computing units, and the intelligent control module is further used to: determine the target algorithm based on the requirement information, wherein the target algorithm includes one of the following: the first algorithm, the second algorithm, the first algorithm and the second algorithm; and, determine the second computing resources required for the target algorithm based on the requirement information, and adjust the shared computing resources of the reconfigurable cryptographic computing module based on the target algorithm and the second computing resources.

[0117] Optionally, the intelligent control module is also used to: when the target algorithm is the first algorithm, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit; when the target algorithm is the second algorithm, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit.

[0118] Optionally, the intelligent control module is also used to: when the target algorithm is the first algorithm and the second algorithm, determine the third computing resources required for the first algorithm and the fourth computing resources required for the second algorithm according to the demand information, wherein the second computing resources include the third computing resources and the fourth computing resources; and adjust the multiple reconfigurable computing units according to the third computing resources and the fourth computing resources.

[0119] Optionally, the intelligent control module is also used to: determine whether the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm based on the third computing resource and the fourth computing resource; when it is determined that the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm, control the first reconfigurable computing unit to switch to connect with the first algorithm computing unit, and control the second reconfigurable computing unit to switch to connect with the second algorithm computing unit, wherein the multiple reconfigurable computing units include the first reconfigurable computing unit and the second reconfigurable computing unit, and the ratio of the number of the first reconfigurable computing unit to the number of the second reconfigurable computing unit is determined based on the third computing resource and the fourth computing resource.

[0120] Optionally, the intelligent control module is also used to: determine the priority order of the first algorithm and the second algorithm according to the requirement information when it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm; and adjust the multiple reconfigurable computing units according to the priority order.

[0121] Optionally, the intelligent control module is also used to: when the priority order indicates that the priority of the first algorithm is higher than the priority of the second algorithm, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit; when it is determined that the execution of the first algorithm is completed, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit.

[0122] Optionally, the intelligent control module is also used to: when the priority order indicates that the priority of the second algorithm is higher than the priority of the first algorithm, control the multiple reconfigurable computing units to switch to connect with the second algorithm computing unit; when it is determined that the execution of the second algorithm is completed, control the multiple reconfigurable computing units to switch to connect with the first algorithm computing unit.

[0123] Optionally, the intelligent control module is also used to: determine a first data amount of data to be processed by the first algorithm and a second data amount of data to be processed by the second algorithm according to the requirement information when it is determined that the reconfigurable cryptographic computing module does not support simultaneous execution of the first algorithm and the second algorithm; determine the ratio of the number of third reconfigurable computing units to that of fourth reconfigurable computing units according to the ratio of the first data amount to the second data amount, and control the third reconfigurable computing unit to switch to connect with the first algorithm computing unit, and control the fourth reconfigurable computing unit to switch to connect with the second algorithm computing unit.

[0124] Optionally, the multiple reconfigurable computing units include: multiple groups of reconfigurable computing units, wherein the computing capabilities of each group of reconfigurable computing units in the multiple groups of reconfigurable computing units are different.

[0125] Optionally, the first algorithm calculation unit includes: a first encryption / decryption calculation unit, used to encrypt the data to be encrypted through a first encryption algorithm, or, used to decrypt the data to be decrypted through a first decryption algorithm; a first key expansion unit, used to expand the key through a first expansion algorithm, wherein the first sub-algorithm includes the first encryption algorithm, the first decryption algorithm and the first expansion algorithm.

[0126] Optionally, the second algorithm calculation unit includes: a second encryption / decryption calculation unit, used to encrypt the data to be encrypted through a second encryption algorithm, or, used to decrypt the data to be decrypted through a second decryption algorithm; a second key expansion unit, used to expand the key through a second expansion algorithm, wherein the second sub-algorithm includes the second encryption algorithm, the second decryption algorithm and the second expansion algorithm.

[0127] Optionally, the reconfigurable cryptographic computing module is further used to: process the target data through the first computing resource to obtain a processing result, wherein the processing result includes one of the following: an encryption result, a decryption result; and store the processing result in the data module.

[0128] Optionally, the embodiment of the present application also provides an optional architecture diagram of a baseboard management controller, such as Fig.12 As shown, the BMC chip (i.e., the above-mentioned baseboard management controller) architecture includes: a processor (i.e., the above-mentioned second processor), a storage module, a RISC-V reconfigurable cryptographic coprocessor (i.e., the above-mentioned reconfigurable cryptographic coprocessor) and other functional modules.

[0129] The processor is the control and computing core unit of the BMC chip. The processor is an Arm processor or a RISC-V processor. The processor can be a single-core processor or a multi-core processor. When the processor is composed of multiple different Arm or RISC-V processors, one of the highest-performance processors is the master processor, which handles high-speed and high-complexity tasks, and the other processors are slave processors, which are responsible for low-speed and low-complexity tasks.

[0130] The storage module is used for data storage of the BMC chip, including SRAM, DDR SDRAM, ROM, FLASH and other chips.

[0131] The RISC-V reconfigurable cryptographic coprocessor is used to implement encryption and decryption calculations of the AES algorithm and SM4 algorithm, and different algorithms are selected according to different application scenarios.

[0132] Other functional modules are used to implement hardware monitoring, fault management, remote control and other functions of the BMC chip, including clock module, power module, video display module, hardware monitoring module, etc.

[0133] The processor, storage module, RISC-V reconfigurable cryptographic coprocessor and other functional modules are connected through buses, including AXI bus, AHB bus and APB bus.

[0134] In an optional embodiment, the present application provides a method for processing target data, the process is as follows: Fig.13As shown, the following steps are included:

[0135] Step S1302, receiving demand information sent by a second processor in the baseboard management controller, wherein the demand information is used to indicate a target algorithm for processing target data, and the target data includes: a key, data to be encrypted or data to be decrypted;

[0136] Step S1304, adjusting the shared computing resources of the reconfigurable cryptographic coprocessor according to the demand information;

[0137] Step S1306, processing the target data by using the first computing resources obtained after adjustment, wherein the first computing resources include: fixed computing resources of the reconfigurable cryptographic coprocessor and shared computing resources after adjustment.

[0138] Through the above steps, the demand information sent by the second processor in the baseboard management controller is first received, the demand information is used to indicate the target algorithm for processing the target data, and the target data includes: a key, data to be encrypted or data to be decrypted; the shared computing resources of the reconfigurable cryptographic coprocessor are adjusted according to the demand information; the target data is processed by the first computing resources obtained by adjustment, and the first computing resources include the fixed computing resources of the reconfigurable cryptographic coprocessor and the adjusted shared computing resources; the above steps are adopted to solve the problem in the related art that the hardware acceleration computing units of the AES algorithm and the SM4 algorithm in the existing BMC chip are independent of each other, have a large area and high power consumption.

[0139] Optionally, the target data is processed by the first computing resource obtained after adjustment, including: processing the target data by the first computing resource to obtain a processing result, wherein the processing result includes one of the following: an encryption result, a decryption result; storing the processing result in a data module in the reconfigurable cryptographic coprocessor.

[0140] The process of processing the target data includes: first executing the target algorithm through the first computing resource to complete the processing of the target data and obtain the processing result, which includes one of the following: encryption result, decryption result; and then storing the processing result in the data module.

[0141] Optionally, the shared computing resources include multiple reconfigurable computing units, and adjusting the shared computing resources of the reconfigurable cryptographic coprocessor according to the requirement information includes: determining the target algorithm according to the requirement information, wherein the target algorithm includes one of the following: a first algorithm, a second algorithm, the first algorithm and the second algorithm; and, determining the second computing resources required for the target algorithm according to the requirement information, and adjusting the shared computing resources of the reconfigurable cryptographic computing module according to the target algorithm and the second computing resources.

[0142] Optionally, adjusting the shared computing resources of the reconfigurable cryptographic computing module according to the target algorithm and the second computing resources includes: when the target algorithm is the first algorithm, controlling the plurality of the reconfigurable computing units to switch to connect with the first algorithm computing unit; when the target algorithm is the second algorithm, controlling the plurality of the reconfigurable computing units to switch to connect with the second algorithm computing unit.

[0143] Optionally, adjusting the shared computing resources of the reconfigurable cryptographic computing module according to the target algorithm and the second computing resources includes: when the target algorithm is the first algorithm and the second algorithm, determining the third computing resources required for the first algorithm and the fourth computing resources required for the second algorithm according to the requirement information, wherein the second computing resources include the third computing resources and the fourth computing resources; and adjusting the multiple reconfigurable computing units according to the third computing resources and the fourth computing resources.

[0144] Optionally, the adjusting of the plurality of reconfigurable computing units according to the third computing resource and the fourth computing resource includes: determining whether the reconfigurable cryptographic computing module supports simultaneous execution of the first algorithm and the second algorithm according to the third computing resource and the fourth computing resource; when it is determined that the reconfigurable cryptographic computing module supports simultaneous execution of the first algorithm and the second algorithm, controlling the first reconfigurable computing unit to switch to connection with the first algorithm computing unit, and controlling the second reconfigurable computing unit to switch to connection with the second algorithm computing unit, wherein the plurality of reconfigurable computing units include the first reconfigurable computing unit and the second reconfigurable computing unit, and the ratio of the number of the first reconfigurable computing unit to the number of the second reconfigurable computing unit is determined according to the third computing resource and the fourth computing resource.

[0145] Optionally, after determining whether the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm based on the third computing resource and the fourth computing resource, the method further includes: when it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm, determining the priority order of the first algorithm and the second algorithm based on the requirement information; and adjusting the multiple reconfigurable computing units according to the priority order.

[0146] Optionally, adjusting the multiple reconfigurable computing units according to the priority order includes: when the priority order indicates that the priority of the first algorithm is higher than the priority of the second algorithm, controlling the multiple reconfigurable computing units to switch to connection with the first algorithm computing unit; when it is determined that the execution of the first algorithm is completed, controlling the multiple reconfigurable computing units to switch to connection with the second algorithm computing unit.

[0147] Optionally, adjusting the multiple reconfigurable computing units according to the priority order includes: when the priority order indicates that the priority of the second algorithm is higher than the priority of the first algorithm, controlling the multiple reconfigurable computing units to switch to connection with the second algorithm computing unit; when it is determined that the execution of the second algorithm is completed, controlling the multiple reconfigurable computing units to switch to connection with the first algorithm computing unit.

[0148] Optionally, after determining whether the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm based on the third computing resource and the fourth computing resource, the method further includes: in a case where it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm, determining a first data amount of data to be processed by the first algorithm and a second data amount of data to be processed by the second algorithm based on the requirement information; determining a ratio between the number of third reconfigurable computing units and a fourth reconfigurable computing unit based on the ratio of the first data amount to the second data amount, and controlling the third reconfigurable computing unit to switch to connect to the first algorithm computing unit, and controlling the fourth reconfigurable computing unit to switch to connect to the second algorithm computing unit.

[0149] Optionally, the multiple reconfigurable computing units include: multiple groups of reconfigurable computing units, wherein the computing capabilities of each group of reconfigurable computing units in the multiple groups of reconfigurable computing units are different.

[0150] Optionally, the present application embodiment provides an optional method for processing target data, the process of which is as follows: Fig.14 As shown, the following steps are included:

[0151] 1. The processor of the BMC chip determines the encryption algorithm to be used (AES algorithm or SM4 algorithm) according to the application scenario of the BMC chip;

[0152] 2. The RISC-V processor receives information from the BMC chip processor and then configures the intelligent control module;

[0153] 3. The intelligent control module configures the reconfigurable cryptographic calculation module, selects the algorithm to be executed, and configures the data module, inputting the key, encrypted data or decrypted data into the reconfigurable cryptographic calculation module;

[0154] 4. The reconfigurable cryptographic calculation module performs encryption / decryption calculations of the AES algorithm or SM4 algorithm;

[0155] 5. The encryption / decryption calculation results are stored in the data module.

[0156] With the development of BMC chips, the demand for the diversity of encryption algorithms is gradually increasing. The AES and SM4 algorithm reconfigurable cryptographic coprocessor is compatible with the AES algorithm and the SM4 algorithm, and can select and switch algorithms according to different usage scenarios. The reconfigurable cryptographic coprocessor makes full use of the similarities between the AES algorithm and the SM4 algorithm, which can effectively reduce the area of ​​the coprocessor chip and reduce chip power consumption.

[0157] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0158] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0159] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0160] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0161] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0162] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0163] An embodiment of the present application further provides a computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program product, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0164] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0165] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0166] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A reconfigurable cryptographic coprocessor, characterized in that: include: A first processor is connected to a second processor in a baseboard management controller, and is used to send demand information sent by the second processor to an intelligent control module, wherein the demand information is used to indicate a target algorithm for processing target data, and the target data includes: a key, data to be encrypted, or data to be decrypted; The intelligent control module is connected to the data module and the first processor, and is used to adjust the shared computing resources of the reconfigurable cryptographic computing module according to the demand information, and send the target data sent by the data module to the reconfigurable cryptographic computing module; The reconfigurable cryptographic computing module is used to process the target data through the first computing resources obtained after adjustment, wherein the first computing resources include: the fixed computing resources of the reconfigurable cryptographic computing module and the shared computing resources after adjustment; Wherein, the reconfigurable cryptographic computing module comprises: A first algorithm calculation unit, used for calculating a first sub-algorithm of a first algorithm; A second algorithm calculation unit, used for calculating a second sub-algorithm of the second algorithm; a reconfigurable computing unit, connected to the first algorithm computing unit or the second algorithm computing unit, and configured to compute a third sub-algorithm, wherein both the first algorithm and the second algorithm include the third sub-algorithm; Wherein, the shared computing resource includes a plurality of the reconfigurable computing units, and the intelligent control module is further used for: determining the target algorithm according to the demand information, wherein the target algorithm includes one of the following: the first algorithm, the second algorithm, the first algorithm and the second algorithm; and, The second computing resources required by the target algorithm are determined according to the demand information, and the shared computing resources of the reconfigurable cryptographic computing module are adjusted according to the target algorithm and the second computing resources.

2. The reconfigurable cryptographic coprocessor according to claim 1, characterized in that: The intelligent control module is also used for: When the target algorithm is the first algorithm, controlling the plurality of reconfigurable computing units to switch to be connected to the computing unit of the first algorithm; When the target algorithm is the second algorithm, the plurality of reconfigurable computing units are controlled to switch to be connected to the second algorithm computing unit.

3. The reconfigurable cryptographic coprocessor according to claim 1, characterized in that: The intelligent control module is also used for: In a case where the target algorithm is the first algorithm and the second algorithm, determining a third computing resource required by the first algorithm and a fourth computing resource required by the second algorithm according to the requirement information, wherein the second computing resource includes the third computing resource and the fourth computing resource; The plurality of reconfigurable computing units are adjusted according to the third computing resource and the fourth computing resource.

4. The reconfigurable cryptographic coprocessor according to claim 3, characterized in that: The intelligent control module is also used for: Determining whether the reconfigurable cryptographic computing module supports executing the first algorithm and the second algorithm simultaneously according to the third computing resource and the fourth computing resource; When it is determined that the reconfigurable cryptographic computing module supports the simultaneous execution of the first algorithm and the second algorithm, the first reconfigurable computing unit is controlled to switch to connect with the first algorithm computing unit, and the second reconfigurable computing unit is controlled to switch to connect with the second algorithm computing unit, wherein the multiple reconfigurable computing units include the first reconfigurable computing unit and the second reconfigurable computing unit, and the ratio of the number of the first reconfigurable computing unit to the number of the second reconfigurable computing unit is determined according to the third computing resources and the fourth computing resources.

5. The reconfigurable cryptographic coprocessor according to claim 4, characterized in that: The intelligent control module is also used for: In the case where it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm, determining a priority order of the first algorithm and the second algorithm according to the requirement information; The plurality of reconfigurable computing units are adjusted according to the priority order.

6. The reconfigurable cryptographic coprocessor according to claim 5, characterized in that: The intelligent control module is also used for: When the priority order indicates that the priority of the first algorithm is higher than the priority of the second algorithm, controlling the plurality of reconfigurable computing units to switch to connect with the computing unit of the first algorithm; When it is determined that the execution of the first algorithm is completed, the plurality of reconfigurable computing units are controlled to switch to be connected to the second algorithm computing unit.

7. The reconfigurable cryptographic coprocessor according to claim 5, characterized in that: The intelligent control module is also used for: When the priority order indicates that the priority of the second algorithm is higher than the priority of the first algorithm, controlling the plurality of reconfigurable computing units to switch to connect with the computing unit of the second algorithm; When it is determined that the execution of the second algorithm is completed, the plurality of reconfigurable computing units are controlled to switch to be connected to the computing unit of the first algorithm.

8. The reconfigurable cryptographic coprocessor according to claim 4, characterized in that: The intelligent control module is also used for: In the case where it is determined that the reconfigurable cryptographic computing module does not support the simultaneous execution of the first algorithm and the second algorithm, determining a first data volume of data to be processed by the first algorithm and a second data volume of data to be processed by the second algorithm according to the requirement information; The ratio of the number of the third reconfigurable computing unit to the number of the fourth reconfigurable computing unit is determined according to the ratio of the first data amount to the second data amount, and the third reconfigurable computing unit is controlled to switch to connect with the first algorithm computing unit, and the fourth reconfigurable computing unit is controlled to switch to connect with the second algorithm computing unit.

9. The reconfigurable cryptographic coprocessor according to any one of claims 1 to 8, characterized in that: The plurality of reconfigurable computing units include: A plurality of groups of reconfigurable computing units, wherein the computing capabilities of each group of reconfigurable computing units in the plurality of groups of reconfigurable computing units are different.

10. The reconfigurable cryptographic coprocessor according to any one of claims 1 to 8, characterized in that: The first algorithm calculation unit includes: A first encryption / decryption calculation unit, used to encrypt the data to be encrypted using a first encryption algorithm, or to decrypt the data to be decrypted using a first decryption algorithm; The first key expansion unit is used to expand the key through a first expansion algorithm, wherein the first sub-algorithm includes the first encryption algorithm, the first decryption algorithm and the first expansion algorithm.

11. The reconfigurable cryptographic coprocessor according to any one of claims 1 to 8, characterized in that: The second algorithm calculation unit includes: A second encryption / decryption calculation unit, used to encrypt the data to be encrypted by using a second encryption algorithm, or to decrypt the data to be decrypted by using a second decryption algorithm; The second key expansion unit is used to expand the key through a second expansion algorithm, wherein the second sub-algorithm includes the second encryption algorithm, the second decryption algorithm and the second expansion algorithm.

12. The reconfigurable cryptographic coprocessor according to any one of claims 1 to 8, characterized in that: The reconfigurable password calculation module is also used for: Processing the target data by the first computing resource to obtain a processing result, wherein the processing result includes one of the following: an encryption result, a decryption result; The processing result is stored in the data module.

13. A baseboard management controller, characterized in that: A reconfigurable cryptographic coprocessor comprising any one of claims 1 to 12, include: A second processor is connected to the reconfigurable cryptographic coprocessor, and is used to receive a demand instruction, parse the demand instruction, obtain demand information, and send the demand information to the reconfigurable cryptographic coprocessor, wherein the demand instruction is used to indicate processing of target data, and the demand information is used to indicate a target algorithm for processing the target data, and the target data includes: a key, data to be encrypted, or data to be decrypted; The reconfigurable cryptographic coprocessor is used to adjust the shared computing resources in the reconfigurable cryptographic coprocessor according to the demand information, and process the target data through the first computing resources obtained after the adjustment, wherein the first computing resources include: the fixed computing resources of the reconfigurable cryptographic coprocessor and the adjusted shared computing resources.

14. A method for processing target data, characterized in that: A reconfigurable cryptographic coprocessor according to any one of claims 1 to 12, include: Receiving demand information sent by a second processor in the baseboard management controller, wherein the demand information is used to indicate a target algorithm for processing target data, and the target data includes: a key, data to be encrypted or data to be decrypted; adjusting the shared computing resources of the reconfigurable cryptographic coprocessor according to the demand information; The target data is processed by the first computing resources obtained after adjustment, wherein the first computing resources include: the fixed computing resources of the reconfigurable cryptographic coprocessor and the shared computing resources after adjustment.

15. The method for processing target data according to claim 14, characterized in that: The first computing resource obtained through adjustment processes the target data, including: Processing the target data by the first computing resource to obtain a processing result, wherein the processing result includes one of the following: an encryption result, a decryption result; The processing result is stored in a data module in the reconfigurable cryptographic coprocessor.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in claim 14 or 15 when executed by a processor.

17. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to claim 14 or 15 are implemented.

18. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to claim 14 or 15 are implemented.

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