A method and device for incrementally improving FPGA timing performance

Abstract

Disclosed are a method and device for incrementally improving FPGA timing performance. The present invention first calls timing analysis to obtain a connection set C with the smallest time margin. Then, for each connection c in the connection set C, firstly, incremental boxing is performed to move the BLE at the starting point of c to the CLB where the BLE at the end point of c is located. Then, incremental boxing is performed to move the BLE at the end point of c to the CLB where the BLE at the starting point of c is located. If one of the two incremental boxing is feasible and makes the minimum time margin better or the number of connections with the smallest time margin smaller, then the result of the incremental boxing is maintained, the connection set C is updated, and the next round of optimization is entered. Otherwise, the result before the incremental boxing is restored, and the optimization of the next connection in the set C is entered. Therefore, the present invention can achieve timing convergence without modifying the original code, improve timing performance, and has fast calculation speed and accurate calculation value.

Description

Technical Field

[0001] The present invention relates to the technical field of field programmable gate arrays (FPGAs) in digital integrated circuits, and in particular to a method for incrementally improving FPGA timing performance, and a device for incrementally improving FPGA timing performance. Background Art

[0002] FPGA (Field-Programmable Gate Array) is a general-purpose logic circuit, and is known as one of the three major general-purpose signal processing devices along with CPU and DSP.

[0003] At present, FPGA has become an indispensable way to achieve digital circuits. It has obvious advantages in development cycle and programmable flexibility. Its application fields are becoming more and more extensive, involving many fields such as communications, aerospace, medical, mathematical calculations, image processing, consumer products, etc. Timing performance is one of the most important indicators of FPGA. In FPGA logic design, the combinational logic on the timing path will give the path incremental delay. Reasonable layout and routing can reduce the delay on the path, so by reducing the delay on the critical path, the purpose of optimization can be achieved. After the conventional EDA (Electronic design automation) software is laid out and routed, the critical path has been determined, and it is difficult to meet the timing performance. Timing convergence can only be achieved by modifying the original code. Summary of the invention

[0004] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a method for incrementally improving the timing performance of FPGA, which can achieve timing convergence without modifying the original code, improve timing performance, and has fast calculation speed and accurate calculation value.

[0005] The technical solution of the present invention is: the method for incrementally improving the timing performance of FPGA comprises the following steps:

[0006] (1) Run timing analysis, back up the current timing delay, obtain the connection set C with the smallest time margin, and mark each connection in connection C as optimizable;

[0007] (2) Determine whether there are any connections that can be optimized in C. If so, find the first connection c in set C that can be optimized; otherwise, go to step (13);

[0008] (3) Perform simulated incremental packing to determine whether incremental packing is possible, but do not actually perform incremental packing. Move the component at the starting point c to the element cluster where the component at the end point c is located, and only change the coordinate position of the component;

[0009] (4) Determine whether the packing is feasible. If so, execute step (5); otherwise, execute step (7);

[0010] (5) Routing the s-coordinates and ports of the element cluster where the components are located, performing incremental routing, updating the affected wire delay to the timing netlist, running incremental timing analysis, and obtaining the latest minimum time margin;

[0011] (6) Determine whether the minimum time margin value has improved or the number of connections with the minimum time margin has decreased. If so, execute step (11); otherwise, restore the component coordinates, restore the wiring results, restore the timing delay, and execute step (7);

[0012] (7) Perform incremental packing to move the components at the end point c to the element cluster where the components at the start point c are located; route the s coordinates and ports of the element cluster where the components are located, perform incremental routing, and update the affected wire net delays to the timing netlist;

[0013] (8) Determine whether the packing is feasible. If so, execute step (9); otherwise, execute step (12);

[0014] (9) The s-coordinates and ports of the element cluster where the components are located are routed, and the routing is incrementally compiled and routed. The affected wire delay is updated to the timing netlist, and the timing analysis is performed to obtain the latest established minimum time margin;

[0015] (10) Determine whether the minimum time margin value has improved or the number of connections with the minimum time margin has decreased. If so, execute step (11); otherwise, execute step (12);

[0016] (11) Keep the incremental packing results, perform formal incremental packing and formal incremental routing, back up the timing delay, and update the connection set C with the minimum time margin of the latest timing analysis results; go to step (3);

[0017] (12) Restore the packing results, restore the routing results, restore the component coordinates, restore the timing delay, and mark the current connection c as non-optimizable; go to step (2);

[0018] (13) End.

[0019] The present invention first calls timing analysis to obtain a connection set C with the smallest time margin, and then for each connection c in the connection set C, first performs incremental boxing to move the BLE at the starting point of c to the CLB where the BLE at the end point of c is located, and then performs incremental boxing to move the BLE at the end point of c to the CLB where the BLE at the starting point of c is located; if one of the two incremental boxing is feasible and makes the minimum time margin established better or the number of connections with the smallest time margin decreases, then the result of the incremental boxing is maintained, the connection set C is updated, and the next round of optimization is entered; otherwise, the result before the incremental boxing is restored, and the optimization of the next connection in the set C is entered; therefore, the present invention can achieve timing convergence without modifying the original code, improve timing performance, and have a fast calculation speed and accurate calculation values.

[0020] A device for incrementally improving FPGA timing performance is also provided, comprising:

[0021] A timing analysis unit configured to run timing analysis, back up the current timing delay, obtain a set of connections C with the smallest establishment time margin, and mark each connection in the connection C as being optimizable;

[0022] The simulated incremental packing unit is configured to simulate incremental packing, determine whether incremental packing is possible, but does not actually perform incremental packing. It moves the components at the c starting point to the element cluster where the c end point components are located, and only changes the coordinate position of the components;

[0023] The incremental timing analysis unit is configured to route the s-coordinates and ports of the element cluster where the components are located, perform incremental routing, update the affected net delay to the timing netlist, run incremental timing analysis, and obtain the latest established minimum time margin;

[0024] The incremental packing unit is configured to perform incremental packing, moving the components at the c end point to the element cluster where the c start point components are located; routing the s coordinates and ports of the element cluster where the components are located, and performing incremental routing, and updating the affected wire net delays to the timing netlist;

[0025] A time margin minimum value acquisition unit is configured to route the s coordinates and ports of the element cluster where the components are located, perform incremental compilation and routing, update the affected wire net delay to the timing netlist, run timing analysis, and obtain the latest established time margin minimum value;

[0026] A formal incremental packing and routing unit configured to retain the incremental packing results, perform formal incremental packing and formal incremental routing, back up the timing delay, and update the time margin minimum connection set C of the latest timing analysis result;

[0027] A restoration unit is configured to restore packing results, restore routing results, restore component coordinates, restore timing delays, and mark the current connection c as non-optimizable. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A flow chart of a method for incrementally improving FPGA timing performance according to the present invention is shown.

[0029] Figure 2 A flow chart of incremental timing analysis according to the present invention is shown.

[0030] Figure 3 A flow chart of step (5.2) according to the present invention is shown.

[0031] Figure 4 A flow chart of step (5.3) according to the present invention is shown.

[0032] Figure 5 A flow chart of step (5.4) according to the present invention is shown.

[0033] Figure 6 A flow chart of step (5.5) according to the present invention is shown.

[0034] Figure 7 A flow chart of simulating bin packing according to the present invention is shown.

[0035] Figure 8 A flow chart of real box packing according to the present invention is shown.

[0036] Fig. 9 A flow chart of incremental wiring according to the present invention is shown. DETAILED DESCRIPTION

[0037] like Figure 1 As shown, this method of incrementally improving FPGA timing performance includes the following steps:

[0038] (1) Run timing analysis, back up the current timing delay, obtain the connection set C with the smallest time margin, and mark each connection in connection C as optimizable;

[0039] (2) Determine whether there are any connections that can be optimized in C. If so, find the first connection c in set C that can be optimized; otherwise, go to step (13);

[0040] (3) Perform simulated incremental packing to determine whether incremental packing is possible, but do not actually perform incremental packing. Move the component at the starting point c to the element cluster where the component at the end point c is located, and only change the coordinate position of the component;

[0041] (4) Determine whether the packing is feasible. If so, execute step (5); otherwise, execute step (7);

[0042] (5) Routing the s-coordinates and ports of the element cluster where the components are located, performing incremental routing, updating the affected wire delay to the timing netlist, running incremental timing analysis, and obtaining the latest minimum time margin;

[0043] (6) Determine whether the minimum time margin value has improved or the number of connections with the minimum time margin has decreased. If so, execute step (11); otherwise, restore the component coordinates, restore the wiring results, restore the timing delay, and execute step (7);

[0044] (7) Perform incremental packing to move the components at the end point c to the element cluster where the components at the start point c are located; route the s coordinates and ports of the element cluster where the components are located, perform incremental routing, and update the affected wire net delays to the timing netlist;

[0045] (8) Determine whether the packing is feasible. If so, execute step (9); otherwise, execute step (12);

[0046] (9) The s-coordinates and ports of the element cluster where the components are located are routed, and the routing is incrementally compiled and routed. The affected wire delay is updated to the timing netlist, and the timing analysis is performed to obtain the latest established minimum time margin;

[0047] (10) Determine whether the minimum time margin value has improved or the number of connections with the minimum time margin has decreased. If so, execute step (11); otherwise, execute step (12);

[0048] (11) Keep the incremental packing results, perform formal incremental packing and formal incremental routing, back up the timing delay, and update the connection set C with the minimum time margin of the latest timing analysis results; go to step (3);

[0049] (12) Restore the packing results, restore the routing results, restore the component coordinates, restore the timing delay, and mark the current connection c as non-optimizable; go to step (2);

[0050] (13) End.

[0051] The present invention first calls timing analysis to obtain a connection set C with the smallest time margin, and then for each connection c in the connection set C, first performs incremental boxing to move the BLE at the starting point of c to the CLB where the BLE at the end point of c is located, and then performs incremental boxing to move the BLE at the end point of c to the CLB where the BLE at the starting point of c is located; if one of the two incremental boxing is feasible and makes the minimum time margin established better or the number of connections with the smallest time margin decreases, then the result of the incremental boxing is maintained, the connection set C is updated, and the next round of optimization is entered; otherwise, the result before the incremental boxing is restored, and the optimization of the next connection in the set C is entered; therefore, the present invention can achieve timing convergence without modifying the original code, improve timing performance, and have a fast calculation speed and accurate calculation values.

[0052] Preferably, if Figure 2 As shown, the incremental timing analysis of step (5) includes the following sub-steps:

[0053] (5.1) Find the starting and ending points of the connection corresponding to the nodes v and d on the timing graph respectively, then find the edge (v, d) corresponding to the connection on the timing graph, and finally update the delay of the edge (v, d);

[0054] (5.2) Slice the timing graph according to the set of connections with delayed changes, and cut out the subgraph consisting of the affected points and edges as the basis for the next step of timing analysis;

[0055] (5.3) Start from the smallest level on the time series graph subgraph and traverse from front to back layer by layer, only traverse the points on the subgraph and analyze the arrival time of each passing point;

[0056] (5.4) Traverse the last layer of the timing graph subgraph from back to front and analyze the required time to pass each point;

[0057] (5.5) For each affected connection in the netlist, calculate the timing margin and criticality of the connection.

[0058] Preferably, in the step (5.2), V' is a subset of V, and for each point v of V', slice(v) = true is satisfied, and the method for slicing the timing graph includes: for each connection with a delay change, first find the starting point and the end point of the connection corresponding to the nodes v and d on the timing graph, add v and d to the point set V' of the subgraph, and set slice(v) = true, slice(d) = true; traverse the timing graph G layer by layer from node d backward, and add each point passed through to the set V' of the subgraph respectively; traverse each level from node v forward on the timing graph G, and for each node v' of each level before node v, if there is an edge whose end point d' is a point of the subgraph V', satisfying slice(d') = true, then add the node v' to the subgraph point set V', and set slice(v') = true.

[0059] Preferably, if Figure 3 As shown, the step (5.2) includes the following sub-steps:

[0060] (5.2.1) Traverse each connection with a changed delay, and for each connection with a changed delay, execute steps (5.2.2)-(5.2.4);

[0061] (5.2.2) Find the starting and ending points of the connection corresponding to the nodes v and d on the timing graph, add v and d to the point set V' of the subgraph, and set slice(v) = true, slice(d) = true;

[0062] (5.2.3) Traverse the time graph G from node d layer by layer, and add each point passed through to the subgraph set V'. The level of node d is level, and the maximum level of graph G is N. First, add the end point d' of each output edge of node d to the subgraph point set V', and set slice(d') = true; for each level i from level+1 to N-1, for each node v' at level i, if slice(v') = true, then add the end point d' of each output edge of node v' to the subgraph point set V', and slice(d') = true;

[0063] (5.2.4) On the sequential graph G, traverse each level from node v forward, and add each node that reaches the subgraph G to the subgraph set V'. The level of node v is level, and the minimum level of graph G is 0. For each level i from level-1 to 0, for each node v' at level i, traverse each output edge e of node v'. If the end point d' of e is a node in the subgraph V' and slice(d') = true is satisfied, then add node v' to the subgraph point set V' and set slice(v') = true.

[0064] Preferably, in step (5.3), traverse each point v in V' to find the minimum value min_level and the maximum value max_level of the level where v is located; traverse each level i from min_level to max_level-1, and for each point v in level i, if slice(v) = true, traverse each output edge e of point v, and if the end point d of e satisfies slice(d) = true, then calculate the maximum arrival time of node d according to the formula Tarrive(d) = max(Tarrive(d), Tarrive(v) + delay(v, d)), where delay(v, d) represents the delay of the edge from v to d.

[0065] Preferably, if Figure 4 As shown, the step (5.3) includes the following sub-steps:

[0066] (5.3.1) Traverse each point v in V' and find the minimum value min_level and the maximum value max_level of the level where v is located;

[0067] (5.3.2) Traverse each level i from min_level to max_level-1 and execute steps (5.3.3)-(5.3.7);

[0068] (5.3.3) For each point v at level i, perform steps (5.3.4)-(5.3.7);

[0069] (5.3.4) If slice(v) = true, then execute steps (5.3.5)-(5.3.7);

[0070] (5.3.5) Traverse each outgoing edge e of point v;

[0071] (5.3.6) If the end point d of e satisfies slice(d) = true, then execute step (5.3.7);

[0072] (5.3.7) The maximum arrival time of node d is calculated according to the formula Tarrive(d) = max(Tarrive(d), Tarrive(v) + delay(v, d)), where delay(v, d) represents the delay of the edge from v to d.

[0073] Preferably, in step (5.4), each level i from max_level-1 to min_level is traversed, and for each point v at level i, if slice(v) = true, then each output edge e of point v is traversed, and if the end point d of e satisfies slice(d) = true, then the minimum required time of node v is calculated according to the formula Trequired(v) = min(Trequired (v), Trequired (v) -delay(v, d)).

[0074] Preferably, if Figure 5 As shown, the step (5.4) includes the following sub-steps:

[0075] (5.4.1) Traverse each level i from max_level-1 to min_level and execute steps (5.4.2)-(5.4.6);

[0076] (5.4.2) For each point v at level i, perform steps (5.4.3)-(5.4.6);

[0077] (5.4.3) If slice(v) = true, then execute steps (5.4.4)-(5.4.6);

[0078] (5.4.4) Traverse each outgoing edge e of point v;

[0079] (5.4.5) If the end point d of e satisfies slice(d) = true, then execute step (5.4.6);

[0080] (5.4.6) Calculate the minimum required time for node v according to the formula Trequired(v) = min(Trequired (v), Trequired (d) - delay(v, d)).

[0081] Preferably, in step (5.5), each wire net in the netlist is traversed to find the node v on the timing diagram corresponding to the starting point of the wire net. If slice(v) = true is satisfied, each end point of the wire net is traversed to find the node d on the timing diagram corresponding to each end point. If d satisfies slice(d) = true, the timing margin of the connection (v, d) is calculated according to formula (3), and then the criticality of the connection (v, d) is calculated according to formula (4).

[0082] After completing the arrival time analysis and the required time analysis, we start to calculate the new timing margin and criticality of each affected connection in the netlist. The specific process of calculating the timing results is as follows: Figure 6 shown.

[0083] Based on the incremental packing method of moving components, each coordinate (element cluster) on the structure in the FPGA can place up to 10 components, and these 10 components must comply with the packing rules. The basic principle of incremental packing is to first set the coordinates to be moved and obtain the affected signals. Collect the changed information and cache it, and notify the routing at the same time. When the routing is completed, calculate the critical path. If the timing performance is improved, perform real packing, otherwise delete the cached information. Figure 7 The steps of simulating bin packing are shown. Figure 8 The actual packing steps are shown.

[0084] like Fig. 9 As shown, incremental routing is also divided into two steps, virtual routing and implementation routing.

[0085] Virtual routing is not real routing, but parallel virtual routing based on the results returned by incremental packing. The routing results are saved, and the delay affecting the signal is fed back to the timing netlist for incremental timing analysis. After incremental timing analysis, it is determined whether the timing performance has improved. If it has improved, real routing is performed, otherwise the routing results are restored.

[0086] After virtual routing, if the timing performance is improved, the cached results are differentiated into the routing results and the routing results are saved.

[0087] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the above-mentioned embodiment method, and the storage medium can be: ROM / RAM, disk, optical disk, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also includes a device for incrementally improving the timing performance of FPGA, which is usually represented in the form of functional modules corresponding to the steps of the method. The device includes:

[0088] A timing analysis unit configured to run timing analysis, back up the current timing delay, obtain a set of connections C with the smallest establishment time margin, and mark each connection in the connection C as being optimizable;

[0089] The simulated incremental packing unit is configured to simulate incremental packing, determine whether incremental packing is possible, but does not actually perform incremental packing. It moves the components at the c starting point to the element cluster where the c end point components are located, and only changes the coordinate position of the components;

[0090] The incremental timing analysis unit is configured to route the s-coordinates and ports of the element cluster where the components are located, perform incremental routing, update the affected net delay to the timing netlist, run incremental timing analysis, and obtain the latest established minimum time margin;

[0091] The incremental packing unit is configured to perform incremental packing, moving the components at the c end point to the element cluster where the c start point components are located; routing the s coordinates and ports of the element cluster where the components are located, and performing incremental routing, and updating the affected wire net delays to the timing netlist;

[0092] A time margin minimum value acquisition unit is configured to route the s coordinates and ports of the element cluster where the components are located, perform incremental compilation and routing, update the affected wire net delay to the timing netlist, run timing analysis, and obtain the latest established time margin minimum value;

[0093] A formal incremental packing and routing unit configured to retain the incremental packing results, perform formal incremental packing and formal incremental routing, back up the timing delay, and update the time margin minimum connection set C of the latest timing analysis result;

[0094] A restoration unit is configured to restore packing results, restore routing results, restore component coordinates, restore timing delays, and mark the current connection c as non-optimizable.

[0095] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A method for incrementally improving FPGA timing performance, characterized in that: It includes the following steps: (1) Run timing analysis, back up the current timing delay, obtain the connection set C with the smallest time margin, and mark each connection in the connection set C as optimizable; (2) Determine whether there are any optimizable connections in the connection set C. If so, find the first optimizable connection c in the connection set C; otherwise, go to step (13); (3) Perform simulated incremental packing to determine whether incremental packing is possible, but do not actually perform incremental packing. Move the component at the starting point c to the element cluster where the component at the end point c is located, and only change the coordinate position of the component; (4) Determine whether the packing is feasible. If so, execute step (5); otherwise, execute step (7); (5) Routing the s-coordinates and ports of the element cluster where the components are located, performing incremental routing, updating the affected wire delay to the timing netlist, running incremental timing analysis, and obtaining the latest minimum time margin; (6) Determine whether the minimum time margin value has improved or the number of connections with the minimum time margin has decreased. If so, execute step (11); otherwise, restore the component coordinates, restore the wiring results, restore the timing delay, and execute step (7); (7) Perform incremental packing to move the components at the end point c to the element cluster where the components at the start point c are located; route the s coordinates and ports of the element cluster where the components are located, perform incremental routing, and update the affected wire net delays to the timing netlist; (8) Determine whether the packing is feasible. If so, execute step (9); otherwise, execute step (12); (9) The s-coordinates and ports of the element cluster where the components are located are routed, and the routing is incrementally compiled and routed. The affected wire delay is updated to the timing netlist, and the timing analysis is performed to obtain the latest established minimum time margin; (10) Determine whether the minimum time margin value has improved or the number of connections with the minimum time margin has decreased. If so, execute step (11); otherwise, execute step (12); (11) Keep the incremental packing results, perform formal incremental packing and formal incremental routing, back up the timing delay, and update the connection set C with the minimum time margin of the latest timing analysis results; go to step (3); (12) Restore the packing results, restore the routing results, restore the component coordinates, restore the timing delay, and mark the current connection c as non-optimizable; go to step (2); (13) End.

2. The method for incrementally improving FPGA timing performance according to claim 1, characterized in that: The incremental timing analysis of step (5) includes the following sub-steps: (5.1) Find the starting and ending points of the connection corresponding to the nodes v and d on the timing graph respectively, then find the edge (v, d) corresponding to the connection on the timing graph, and finally update the delay of the edge (v, d); (5.2) Slice the timing graph according to the set of connections with delayed changes, and cut out the subgraph consisting of the affected points and edges as the basis for the next step of timing analysis; (5.3) Start from the smallest level on the time series graph subgraph and traverse from front to back layer by layer, only traverse the points on the subgraph and analyze the arrival time of each passing point; (5.4) Traverse the last layer of the timing graph subgraph from back to front and analyze the required time to pass each point; (5.5) For each affected connection in the netlist, calculate the timing margin and criticality of the connection.

3. The method for incrementally improving FPGA timing performance according to claim 2, characterized in that: In the step (5.2), V' is a subset of V, and for each point v of V', slice(v) = true is satisfied. The method for slicing the timing graph includes: for each connection with a delay change, first find the starting point and the end point of the connection corresponding to the nodes v and d on the timing graph, add v and d to the point set V' of the subgraph, and set slice(v) = true, slice(d) = true; traverse the timing graph G layer by layer from node d backward, and add each point passed through to the set V' of the subgraph respectively; traverse each level from node v forward on the timing graph G, for each node v' of each level before node v, if there is an edge whose end point d' is a point of the subgraph V', satisfying slice(d') = true, then add the node v' to the point set V' of the subgraph, and set slice(v') = true.

4. The method for incrementally improving FPGA timing performance according to claim 2, characterized in that: The step (5.2) comprises the following sub-steps: (5.2.1) Traverse each connection with a changed delay, and for each connection with a changed delay, execute steps (5.2.2)-(5.2.4); (5.2.2) Find the starting and ending points of the connection corresponding to the nodes v and d on the timing graph, add v and d to the point set V' of the subgraph, and set slice(v) = true, slice(d) = true; (5.2.3) Traverse the time graph G from node d layer by layer, and add each point passed through to the subgraph set V'. The level of node d is level, and the maximum level of graph G is N. First, add the end point d' of each output edge of node d to the subgraph point set V', and set slice(d') = true; for each level i from level+1 to N-1, for each node v' at level i, if slice(v') = true, then add the end point d' of each output edge of node v' to the subgraph point set V', and slice(d') = true; (5.2.4) On the sequential graph G, traverse each level from node v forward, and add each node that reaches the subgraph G to the subgraph set V'. The level of node v is level, and the minimum level of graph G is 0. For each level i from level-1 to 0, for each node v' at level i, traverse each output edge e of node v'. If the end point d' of e is a node in the subgraph V' and slice(d') = true is satisfied, then add node v' to the subgraph point set V' and set slice(v') = true.

5. The method for incrementally improving FPGA timing performance according to claim 3, characterized in that: In the step (5.3), traverse each point v in V' and find the minimum min_level and maximum max_level of the level where v is located; traverse each level i from min_level to max_level-1. For each point v in level i, if slice(v) = true, traverse each output edge e of point v. If the end point d of e satisfies slice(d) = true, then calculate the maximum arrival time of node d according to the formula Tarrive(d) = max(Tarrive(d), Tarrive(v) + delay(v, d)). delay(v, d) represents the delay of the edge from v to d.

6. The method for incrementally improving FPGA timing performance according to claim 3, characterized in that: The step (5.3) comprises the following sub-steps: (5.3.1) Traverse each point v in V' and find the minimum value min_level and the maximum value max_level of the level where v is located; (5.3.2) Traverse each level i from min_level to max_level-1 and execute steps (5.3.3)-(5.3.7); (5.3.3) For each point v at level i, perform steps (5.3.4)-(5.3.7); (5.3.4) If slice(v) = true, then execute steps (5.3.5)-(5.3.7); (5.3.5) Traverse each outgoing edge e of point v; (5.3.6) If the end point d of e satisfies slice(d) = true, then execute step (5.3.7); (5.3.7) The maximum arrival time of node d is calculated according to the formula Tarrive(d) = max(Tarrive(d), Tarrive(v) + delay(v, d)), where delay(v, d) represents the delay of the edge from v to d.

7. The method for incrementally improving FPGA timing performance according to claim 5, characterized in that: In the step (5.4), each level i from max_level-1 to min_level is traversed. For each point v at level i, if slice(v) = true, each output edge e of point v is traversed. If the end point d of e satisfies slice(d) = true, the minimum required time of node v is calculated according to the formula Trequired(v) = min(Trequired (v), Trequired (v) - delay(v, d)).

8. The method for incrementally improving FPGA timing performance according to claim 5, characterized in that: The step (5.4) comprises the following sub-steps: (5.4.1) Traverse each level i from max_level-1 to min_level and execute steps (5.4.2)-(5.4.6); (5.4.2) For each point v at level i, perform steps (5.4.3)-(5.4.6); (5.4.3) If slice(v) = true, then execute steps (5.4.4)-(5.4.6); (5.4.4) Traverse each outgoing edge e of point v; (5.4.5) If the end point d of e satisfies slice(d) = true, then execute step (5.4.6); (5.4.6) Calculate the minimum required time for node v according to the formula Trequired(v) = min(Trequired (v), Trequired (d) - delay(v,d)).

9. A device for incrementally improving FPGA timing performance, characterized in that: It is used to perform the method according to claim 1 and comprises: A timing analysis unit configured to run timing analysis, back up the current timing delay, obtain a connection set C with the smallest establishment time margin, and mark each connection in the connection set C as optimizable; The simulated incremental packing unit is configured to simulate incremental packing, determine whether incremental packing is possible, but does not actually perform incremental packing. It moves the components at the c starting point to the element cluster where the c end point components are located, and only changes the coordinate position of the components; The incremental timing analysis unit is configured to route the s-coordinates and ports of the element cluster where the components are located, perform incremental routing, update the affected net delay to the timing netlist, run incremental timing analysis, and obtain the latest established minimum time margin; The incremental packing unit is configured to perform incremental packing, moving the components at the c end point to the element cluster where the c start point components are located; routing the s coordinates and ports of the element cluster where the components are located, and performing incremental routing, and updating the affected wire net delays to the timing netlist; A time margin minimum value acquisition unit is configured to route the s coordinates and ports of the element cluster where the components are located, perform incremental compilation and routing, update the affected wire net delay to the timing netlist, run timing analysis, and obtain the latest established time margin minimum value; A formal incremental packing and routing unit configured to retain the incremental packing results, perform formal incremental packing and formal incremental routing, back up the timing delay, and update the time margin minimum connection set C of the latest timing analysis result; A restoration unit is configured to restore packing results, restore routing results, restore component coordinates, restore timing delays, and mark the current connection c as non-optimizable.

Images