Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present application discloses a semiconductor device and a method for preparing the same, a power module, a power conversion circuit and a vehicle, and belongs to the field of semiconductor technology. The semiconductor device includes: a silicon carbide substrate, an epitaxial layer, a gate, an interlayer insulating layer, a source electrode, a passivation layer, and a drain electrode, wherein the interlayer insulating layer has a first contact hole exposing the epitaxial layer, the source electrode fills the first contact hole and is in electrical contact with the epitaxial layer, the passivation layer has a second contact hole, the source electrode also includes a contact area, the second contact hole exposes the contact area, and the grain size at the contact area is larger than the grain size outside the contact area. The passivation layer of the semiconductor device has no residue in the contact area, which effectively improves the reliability of the device.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a method for preparing the same, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In semiconductor devices, as the cell size decreases, the aspect ratio of the related contact holes in the device continues to increase. The existing metal filling process is difficult to meet the demand. The large aspect ratio contact holes will form voids after metal filling. In the subsequent process of forming the passivation layer, part of the passivation layer will remain in the void, ultimately affecting the reliability of the device. Summary of the invention

[0003] To improve reliability, an embodiment of the present application provides a semiconductor device, including: a silicon carbide substrate, an epitaxial layer, a gate, an interlayer insulating layer, a source, a passivation layer, and a drain, wherein the silicon carbide substrate includes a first surface and a second surface opposite to each other, the epitaxial layer is arranged on the first surface, the gate is arranged on the side of the epitaxial layer away from the silicon carbide substrate, the interlayer insulating layer is arranged on the side of the gate away from the silicon carbide substrate, the interlayer insulating layer has a first contact hole exposing the epitaxial layer, the source is arranged on the side of the interlayer insulating layer away from the silicon carbide substrate, the source fills the first contact hole and is in electrical contact with the epitaxial layer, the passivation layer is arranged on the side of the source away from the silicon carbide substrate, the passivation layer has a second contact hole, and the drain is arranged on the second surface. The source includes a far contact region, the second contact hole exposes the contact region, and the grain size at the contact region is larger than the grain size outside the contact region.

[0004] In some embodiments, along a direction parallel to the first surface, a grain size at the contact region is larger than a grain size outside the contact region.

[0005] In some embodiments, along a direction perpendicular to the first surface, a grain size of the contact region farther from the first surface is larger than a grain size closer to the first surface.

[0006] In some embodiments, the material of the source includes at least one of aluminum, aluminum copper, copper, titanium, titanium nitride, or nickel; and / or, the material of the source includes a doping element.

[0007] In the above embodiment, the source electrode is filled with the first contact hole of the interlayer insulating layer, and the second contact hole of the passivation layer exposes the contact area of ​​the source electrode. The grain size at the contact area is larger than the grain size outside the contact area, which means that the source electrode contact area is subjected to relevant process treatments during the process of filling the first contact hole, such as heating, melting, reflowing and recrystallization, so that the grain size at the contact area is larger than the grain size outside the contact area. Further, this makes the contact area have a relatively flat surface, so that there is no residue of the passivation layer in the contact area, and the passivation layer can completely expose the contact area, effectively avoiding the residue of the passivation layer from affecting the source contact characteristics in the contact area. For example, when the source electrode is externally connected or related tests are performed, the residue can be prevented from affecting the internal heat conduction of the device and accelerating the aging of the device, and the local electrochemical corrosion of the device caused by the residue absorbing moisture in a high temperature and high humidity environment can also be prevented. Therefore, the above embodiment of the present application improves the reliability of the device.

[0008] In a second aspect, the present application also provides a method for preparing a semiconductor device, which specifically comprises the following steps S1 to S7:

[0009] Step S1: forming an epitaxial layer on a silicon carbide substrate, the silicon carbide substrate comprising a first surface and a second surface opposite to each other, the epitaxial layer being located on the first surface.

[0010] Step S2: forming a gate, where the gate is located on a side of the epitaxial layer away from the silicon carbide substrate.

[0011] Step S3: forming an interlayer insulating layer, wherein the interlayer insulating layer is located on a side of the gate away from the silicon carbide substrate, and the interlayer insulating layer has a first contact hole exposing the epitaxial layer.

[0012] Step S4: forming a source electrode, the source electrode is located on a side of the interlayer insulating layer away from the silicon carbide substrate, the source electrode is electrically contacted with the epitaxial layer through the first contact hole; the source electrode includes a third surface away from the silicon carbide substrate, and the third surface includes a contact area.

[0013] Step S5: irradiating the source electrode with laser so that the source electrode fills the first contact hole.

[0014] Step S6: forming a passivation layer, wherein the passivation layer has a second contact hole, and the second contact hole exposes the contact area; an orthographic projection of the passivation layer on the silicon carbide substrate does not overlap with an orthographic projection of the contact area on the silicon carbide substrate.

[0015] Step S7: forming a drain electrode on the second surface.

[0016] In some embodiments, the laser irradiates at least a contact region of the third surface of the source.

[0017] In some embodiments, the wavelength of the laser is in the range of 50nm to 1000nm, the energy is in the range of 1mj to 100j, the duration of irradiation is in the range of 1ns to 100ms, and the area of ​​the spot is in the range of 100nm. 2 ~1cm 2 .

[0018] In the above embodiment, by adopting the laser irradiation method, the source electrode is melted and reflowed to fill the first contact hole. The laser irradiation method enables the contact area to form a relatively flat surface, thereby avoiding the formation of voids in the contact area of ​​the source electrode, thereby avoiding part of the passivation layer remaining in the void when the passivation layer is formed in the subsequent process, which is beneficial to ensuring the contact characteristics of the source electrode in the contact area. For example, it can prevent the residue from affecting the internal heat conduction of the device and accelerating the aging of the device, and it can also prevent the local electrochemical corrosion of the device caused by the residue absorbing moisture in a high temperature and high humidity environment, thereby improving the reliability of the device.

[0019] On the other hand, an embodiment of the present application further provides a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to carry the semiconductor device.

[0020] In another aspect, an embodiment of the present application further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0021] On the other hand, an embodiment of the present application also provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0022] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a local microstructure of a semiconductor device provided in an embodiment of the present application;

[0026] Figure 3A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0027] Figure 4 A diagram showing the steps of preparing an interlayer insulating layer provided in an embodiment of the present application;

[0028] Figure 5 A diagram showing the steps for preparing a source electrode provided in an embodiment of the present application;

[0029] Figure 6 A diagram showing the steps of laser irradiation of a source electrode provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of local laser irradiation provided in an embodiment of the present application;

[0031] Figure 8 A schematic diagram of global laser irradiation provided in an embodiment of the present application;

[0032] Fig. 9 A diagram of the steps of source patterning provided in an embodiment of the present application;

[0033] Fig.10 A diagram showing the steps of forming a passivation layer provided in an embodiment of the present application;

[0034] Fig.11 A diagram showing the steps of forming a drain provided in an embodiment of the present application;

[0035] Fig.12 A schematic diagram of the structure of a power module provided in an embodiment of the present application;

[0036] Fig.13 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application;

[0037] Fig.14 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0042] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0043] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0044] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0045] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0046] In the related art, since the preparation process of semiconductor devices is inevitably accompanied by the need to etch vias, and in the metal filling process after etching, affected by the aspect ratio of the vias and process limitations, voids are easily formed after metal filling. The voids may also have passivation layer residues in the subsequent process of forming the passivation layer, which will affect the reliability of the device. For example, in high temperature and high humidity reverse bias testing or temperature cycle testing, voids and residues may interfere with the heat conduction inside the device, leading to the formation of local hot spots, accelerating device aging, and reducing the service life of the device. Alternatively, in a high temperature and high humidity environment, residues may absorb moisture, leading to local electrochemical corrosion or forming a conductive path, affecting the electrical performance and stability of the device. In other words, voids and residues will reduce device reliability and cause the device to fail the test.

[0047] To improve reliability, the present application embodiment provides a semiconductor device 10, such as Figure 1 As shown, Figure 1 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application, the semiconductor device 10 includes: a silicon carbide substrate 101, an epitaxial layer 102, a gate 103, an interlayer insulating layer 104, a source 105, a passivation layer 106 and a drain 108.

[0048] The silicon carbide substrate 101 includes a first surface P1 and a second surface P2 opposite to each other. The epitaxial layer 102 is arranged on the first surface P1. The gate 103 is arranged on the side of the epitaxial layer 102 away from the silicon carbide substrate 101. The interlayer insulating layer 104 is arranged on the side of the gate 103 away from the silicon carbide substrate 101, and the interlayer insulating layer 104 has a first contact hole V1 exposing the epitaxial layer 102. The source 105 is arranged on the side of the interlayer insulating layer 104 away from the silicon carbide substrate 101, and the source 105 fills the first contact hole V1 and is in electrical contact with the epitaxial layer 102. The passivation layer 106 is arranged on the side of the source 105 away from the silicon carbide substrate 101, and the passivation layer 106 has a second contact hole V2. The drain 108 is arranged on the second surface P2.

[0049] The source electrode 105 includes a contact region 107 , and the second contact hole V2 exposes the contact region 107 . The grain size at the contact region 107 is greater than the grain size outside the contact region 107 .

[0050] like Figure 1As shown, the source 105 includes a third surface P3 away from the silicon carbide substrate 101. The grain size at the contact area 107 is larger than the grain size outside the contact area 107, which means that in the process of filling the first contact hole V1 with the source 105, the contact area 107 has undergone relevant process treatments, such as heating, melting, reflowing and recrystallization, so that the grain size at the contact area 107 is larger than the grain size outside the contact area 107. Further, this makes the third surface P3 relatively flat and less prone to etching residues. The flatness mentioned here refers to a relatively flat surface formed by the natural reflow of the liquid within the error range of the natural properties of the material, allowing the presence of naturally formed curvatures or drops locally, that is, excluding voids caused by human factors. This relatively flat surface morphology can provide a good surface foundation for the subsequent formation of the passivation layer 106 and patterning, and can effectively avoid the problem of residues in the passivation layer 106 caused by the presence of voids. In other words, it means that after forming the source electrode 105, there is no residue of the passivation layer 106 in the contact area 107, and the passivation layer 106 completely exposes the contact area 107, which effectively avoids the residue of the passivation layer 106 remaining in the contact area 107 and affecting the contact characteristics of the source electrode 105. For example, it can prevent the residue from affecting the internal heat conduction of the device and accelerating the aging of the device, and it can also prevent the local electrochemical corrosion of the device caused by the residue absorbing moisture in a high temperature and high humidity environment, thereby improving the reliability of the device.

[0051] In some embodiments, Figure 2 As shown, Figure 2 A schematic diagram of a local microstructure of a semiconductor device provided in an embodiment of the present application, along a direction parallel to the first surface P1, that is, as shown in FIG. Figure 1 or Figure 2 On the third surface P3 shown, the grain size at the contact region 107 is larger than the grain size outside the contact region 107 .

[0052] In some embodiments, Figure 2 As shown, along a direction perpendicular to the first surface P1 , that is, along a direction perpendicular to the third surface P3 , the grain size of the contact region 107 away from the first surface P1 is larger than the grain size close to the first surface P1 .

[0053] The size mentioned here refers to the structure of the grain, and can also be understood as the projected area of ​​the grain in a certain observation direction, for example, the projected area of ​​the grain on the silicon carbide substrate 101. This grain structure is related to the manufacturing process of the device.

[0054] In some embodiments, the material of the source 105 includes at least one of aluminum, aluminum copper, copper, titanium, titanium nitride, or nickel, and the material of the source 105 may also include doping elements. High electrical conductivity, good thermal conductivity, stable chemical properties, and appropriate economy are the key to selecting the material of the source 105 to ensure device performance requirements and reliability requirements.

[0055] In a second aspect, the present application also provides a method for preparing a semiconductor device, such as Figure 3 As shown, Figure 3 A flow chart of a semiconductor device manufacturing method provided in an embodiment of the present application specifically includes the following steps S1 to S7:

[0056] Step S1 : forming an epitaxial layer 102 on a silicon carbide substrate 101 . The silicon carbide substrate 101 includes a first surface P1 and a second surface P2 opposite to each other. The epitaxial layer 102 is located on the first surface P1 .

[0057] Step S2 : forming a gate 103 , where the gate 103 is located on a side of the epitaxial layer 102 away from the silicon carbide substrate 101 .

[0058] Step S3 : forming an interlayer insulating layer 104 . The interlayer insulating layer 104 is located on a side of the gate 103 away from the silicon carbide substrate 101 . The interlayer insulating layer 104 has a first contact hole V1 exposing the epitaxial layer 102 .

[0059] Step S4: forming a source 105 , the source 105 is located on a side of the interlayer insulating layer 104 away from the silicon carbide substrate 101 , the source 105 is electrically contacted with the epitaxial layer 102 through the first contact hole V1 ; the source 105 includes a third surface P3 away from the silicon carbide substrate 101 , the third surface P3 includes a contact region 107 .

[0060] Step S5: irradiating the source electrode 105 with laser so that the source electrode 105 fills the first contact hole V1.

[0061] Step S6: forming a passivation layer 106 having a second contact hole V2 , wherein the second contact hole V2 exposes the contact region 107 ; the orthographic projection of the passivation layer 106 on the silicon carbide substrate 101 does not overlap with the orthographic projection of the contact region 107 on the silicon carbide substrate 101 .

[0062] Step S7: forming a drain electrode 108 on the second surface.

[0063] In the above preparation process, Figures 4 to 6 As shown, Figure 4 A diagram showing the steps for preparing an interlayer insulating layer provided in an embodiment of the present application. Figure 5 A diagram showing the steps for preparing a source electrode provided in an embodiment of the present application. Figure 6This is a diagram of the steps of laser irradiation source provided in the embodiment of the present application. Figure 4 As shown, in step S3, after forming the interlayer insulating layer 104, an etching process is performed to form a first contact hole V1, so that the first contact hole V1 exposes a portion of the epitaxial layer 102, for example, the first contact hole V1 exposes the contact area 107 of the epitaxial layer 102. Figure 5 As shown, a source electrode 105 is formed, and the source electrode 105 is electrically connected to the epitaxial layer 102 through the first contact hole V1. At this time, due to the existence of the first contact hole V1, the source electrode 105 will form a corresponding hollow morphology, such as Figure 5 The dotted oval circle indicates the portion indicated. The contact region 107 of the source electrode 105 is used for subsequent electrical connection. To ensure device reliability, the source electrode 105 in the contact region 107 should have good and reliable contact characteristics.

[0064] In order to avoid the residue of the passivation layer 106 remaining in the cavity morphology during the subsequent process of forming the passivation layer 106, thereby affecting the contact characteristics of the source 105, such as Figure 6 As shown, after the source electrode 105 is formed in step S4, step S6 is performed to irradiate the source electrode 105 with laser so that the source electrode 105 reflows and fills the first contact hole V1. Then, the source electrode 105 is patterned and etched to form the final required pattern of the source electrode 105.

[0065] In some embodiments, the laser irradiates at least the contact area 107 of the third surface P3 of the source electrode 105. Figure 7-8 As shown, Figure 7 A schematic diagram of local laser irradiation provided in an embodiment of the present application, Figure 8 A schematic diagram of global laser irradiation provided in an embodiment of the present application. Figure 7 It represents local laser irradiation, that is, irradiating the cavity morphology area with a large aspect ratio. Figure 8 It represents global laser irradiation, that is, the entire layer of the source electrode 105 is irradiated with laser.

[0066] In some embodiments, the wavelength of the laser is in the range of 50nm to 1000nm, the energy is in the range of 1mj to 100j, the duration of irradiation is in the range of 1ns to 100ms, and the area of ​​the spot is in the range of 100nm. 2 ~1cm 2 For example, the wavelength of the laser is 50nm, 100nm, 150nm...1000nm, etc., the energy range is 1mj, 10mj, 50mj, 100mj...100j, etc., the irradiation time is 1ns, 2ns, 5ns, 10ns, 20ns...100ms, etc., and the area range of the spot is 100nm 2 , 200nm 2 , 250nm 2 , 500nm2 ……1cm 2 wait.

[0067] During laser irradiation, the irradiation depth can be adjusted by adjusting the wavelength of the laser light source. At the same time, the laser spot size can be adjusted to achieve local patterned irradiation and local patterning without the need for lithography-related deposition and etching processes. The spot size can also be adjusted and the wafer can be globally irradiated by overlapping laser pulses. In addition, the overall thermal budget can be adjusted by adjusting the laser pulse time to reduce heat damage to the device. The laser pulse time scale can be nanoseconds, which is more precise and less damaging to the device.

[0068] After the source electrode 105 is irradiated by laser, it melts, reflows and recrystallizes. The grains in the area irradiated by laser increase, showing an arrangement in which the grains on the surface of the irradiated area are large and the grains on the bottom and in the unirradiated area are small. Figure 2 As shown, when the irradiated area is the contact area 107, on the third surface P3 of the source 105, the size of the grains located in the contact area 107 is larger than the size of the grains located outside the contact area 107. The same is true for other laser irradiation schemes.

[0069] At this point, after the laser irradiation in step S5 , a relatively flat surface structure of the contact area 107 is formed.

[0070] Afterwards, if Fig. 9 As shown, Fig. 9 This is a diagram of the steps of patterning the source electrode according to an embodiment of the present application. After the source electrode 105 forms a relatively flat surface, a patterning process is performed to obtain the desired pattern of the source electrode 105 .

[0071] Then, if Figures 10-11 As shown, Fig.10 A diagram showing the steps of forming a passivation layer provided in an embodiment of the present application, Fig.11 According to the step diagram for forming a drain electrode provided in the embodiment of the present application, a passivation layer 106 is formed according to the process of step S6, and the passivation layer 106 is patterned and etched to form a second contact hole V2, so that the second contact hole V2 exposes the contact area 107 to facilitate subsequent electrical connection.

[0072] At this time, it can be ensured that the orthographic projection of the passivation layer 106 on the silicon carbide substrate 101 does not overlap with the orthographic projection of the contact area 107 on the silicon carbide substrate 101 , that is, there is no residue of the passivation layer 106 in the contact area 107 .

[0073] Then, step S7 is performed to form a drain electrode 108 on the second surface for subsequent electrical connection of the semiconductor device.

[0074] On the other hand, an embodiment of the present application further provides a power module, Fig.12A schematic diagram of the structure of a power module provided in an embodiment of the present application.

[0075] like Fig.12 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10 .

[0076] Exemplarily, the power module 200 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0077] On the other hand, an embodiment of the present application further provides a power conversion circuit, Fig.13 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application.

[0078] like Fig.13 As shown, the power conversion circuit 300 includes a circuit board 301 and a semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0079] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0080] On the other hand, an embodiment of the present application further provides a vehicle, Fig.14 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application.

[0081] like Fig.14As shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment, and the power conversion circuit 300 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 401 to power the load 401.

[0082] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A silicon carbide substrate including a first surface and a second surface opposite to each other; an epitaxial layer, disposed on the first surface; A gate, disposed on a side of the epitaxial layer away from the silicon carbide substrate; An interlayer insulating layer, disposed on a side of the gate away from the silicon carbide substrate, the interlayer insulating layer having a first contact hole exposing the epitaxial layer; A source electrode is arranged on a side of the interlayer insulating layer away from the silicon carbide substrate; the source electrode fills the first contact hole and is in electrical contact with the epitaxial layer; A passivation layer, disposed on a side of the source electrode away from the silicon carbide substrate, the passivation layer having a second contact hole; A drain electrode is disposed on the second surface; Wherein, the source electrode includes a contact area, and the second contact hole exposes the contact area; The grain size at the contact area is larger than the grain size outside the contact area.

2. The semiconductor device according to claim 1, wherein: Along a direction parallel to the first surface, a grain size at the contact region is larger than a grain size outside the contact region.

3. The semiconductor device according to claim 1, wherein: Along a direction perpendicular to the first surface, a grain size of the contact region away from the first surface is larger than a grain size close to the first surface.

4. The semiconductor device according to claim 1, wherein: The material of the source electrode includes at least one of aluminum, aluminum copper, copper, titanium, titanium nitride or nickel.

5. A method for preparing a semiconductor device, characterized in that: include: Forming an epitaxial layer on a silicon carbide substrate, wherein the silicon carbide substrate comprises a first surface and a second surface opposite to each other, and the epitaxial layer is located on the first surface; forming a gate, wherein the gate is located on a side of the epitaxial layer away from the silicon carbide substrate; forming an interlayer insulating layer, wherein the interlayer insulating layer is located on a side of the gate away from the silicon carbide substrate, and the interlayer insulating layer has a first contact hole exposing the epitaxial layer; forming a source electrode, the source electrode being located on a side of the interlayer insulating layer away from the silicon carbide substrate, the source electrode being in electrical contact with the epitaxial layer through the first contact hole; the source electrode comprising a third surface away from the silicon carbide substrate, the third surface comprising a contact region; irradiating the source electrode with laser so that the source electrode fills the first contact hole; forming a passivation layer, the passivation layer having a second contact hole, the second contact hole exposing the contact area; an orthographic projection of the passivation layer on the silicon carbide substrate does not overlap with an orthographic projection of the contact area on the silicon carbide substrate; A drain electrode is formed on the second surface.

6. The preparation method according to claim 5, characterized in that: The laser irradiates at least a contact region of the third surface of the source electrode.

7. The preparation method according to claim 5 or 6, characterized in that: The wavelength range of the laser is 50nm~1000nm, the energy range is 1mj~100j, the irradiation time is 1ns~100ms, and the area range of the spot is 100nm 2 ~1cm 2 .

8. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 4, wherein the substrate is used to carry the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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