Layout structure of digital analog mixed circuit

Abstract

The present invention discloses a layout structure of a digital analog hybrid circuit, comprising a first layout area, a second layout area, a third layout area and a fourth layout area overlapping the first layout area, the second layout area and the third layout area, wherein a PMOS tube in an analog circuit is arranged in an area of ​​the first layout area that does not overlap with the fourth layout area, an NMOS tube in a digital circuit and an NMOS tube in an analog circuit are arranged in an area of ​​the second layout area that does not overlap with the fourth layout area, a PMOS tube in a digital circuit is arranged in an area of ​​the third layout area that does not overlap with the fourth layout area, and a voltage conversion circuit is arranged in the fourth layout area. The layout structure of the digital analog hybrid circuit of the present invention can optimize the complexity of metal routing, reduce circuit performance loss caused by parasitics between complex metal wires, make the communication flow between signals clear, and improve the simulation pass rate.

Description

Technical Field

[0001] The invention belongs to the technical field of digital analog hybrid circuits, and in particular relates to a layout structure of a digital analog hybrid circuit. Background Art

[0002] In circuits involving analog and digital signals, the conversion between digital and analog signals is an indispensable part of circuit design. Nowadays, digital-to-analog signal conversion is widely used in different application scenarios, so devices such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) play an important role in today's integrated circuit design.

[0003] Nowadays, in the layout, the difference between digital modules and analog modules is the primary factor that engineers consider. The different voltage domains of the two lead to the distinction in the arrangement of metal wires. The direct communication of signals between different voltage domains may cause the digital module to break down, thus affecting the performance of the entire circuit. Thus, the voltage / level converter (LevelShift, LS) was born, which is a basic device often used in design. Its main function is to switch the input signal from one voltage domain to another.

[0004] As for the efficiency of layout, the alternating placement of adjacent digital signals and analog signals directly affects the complexity of metal wiring, deepens the influence between the metal in the same layer and the adjacent layer, and brings problems such as parasitics and noise interference, thus affecting the chip design cycle. How to optimize the layout structure of digital analog mixed circuits while ensuring circuit safety has become the primary consideration for people in this field.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The purpose of the present invention is to provide a layout structure of a digital-analog hybrid circuit, which can reduce noise interference in the digital-analog hybrid circuit, make the signal flow in the circuit clear, and avoid breakdown.

[0007] In order to achieve the above-mentioned purpose, a specific embodiment of the present invention provides a layout structure of a digital-analog hybrid circuit, including a first layout area, a second layout area, a third layout area and a fourth layout area which are sequentially arranged in a chip and overlap with the first layout area, the second layout area and the third layout area, the digital-analog hybrid circuit includes a digital circuit, an analog circuit and a voltage conversion circuit, the PMOS tube in the analog circuit is arranged in an area of ​​the first layout area that does not overlap with the fourth layout area, the NMOS tube in the digital circuit and the NMOS tube in the analog circuit are arranged in an area of ​​the second layout area that does not overlap with the fourth layout area, the PMOS tube in the digital circuit is arranged in an area of ​​the third layout area that does not overlap with the fourth layout area, and the voltage conversion circuit is arranged in the fourth layout area.

[0008] In one or more embodiments of the present invention, the area in the second layout area that does not overlap with the fourth layout area is divided into a fifth layout area and a sixth layout area, the NMOS tube in the analog circuit is arranged in the fifth layout area, and the NMOS tube in the digital circuit is arranged in the sixth layout area.

[0009] In one or more embodiments of the present invention, the first layout area, the fifth layout area, the sixth layout area and the third layout area are arranged in sequence.

[0010] In one or more embodiments of the present invention, the fifth layout area and the sixth layout area are located on both sides of the fourth layout area.

[0011] In one or more embodiments of the present invention, the fourth layout area overlaps with the first layout area, the second layout area, and the third layout area to form a seventh layout area, an eighth layout area, and a ninth layout area. The PMOS tube working in the first voltage domain in the voltage conversion circuit is arranged in the ninth layout area, the PMOS tube working in the second voltage domain in the voltage conversion circuit is arranged in the seventh layout area, and the NMOS tube in the voltage conversion circuit is arranged in the eighth layout area.

[0012] In one or more embodiments of the present invention, the eighth layout area is divided into a tenth layout area and an eleventh layout area, the NMOS tube working in the first voltage domain in the voltage conversion circuit is arranged in the eleventh layout area, and the NMOS tube working in the second voltage domain in the voltage conversion circuit is arranged in the tenth layout area.

[0013] In one or more embodiments of the present invention, the tenth layout area is arranged close to the fifth layout area, and the eleventh layout area is arranged close to the sixth layout area.

[0014] In one or more embodiments of the present invention, guard rings are arranged on the outer sides of the seventh layout area, the outer sides of the eighth layout area, and the outer sides of the ninth layout area.

[0015] In one or more embodiments of the present invention, the protection ring is arranged between the seventh layout area and the eighth layout area, between the eighth layout area and the ninth layout area, and on the side opposite to the seventh layout area and the eighth layout area and on the side opposite to the ninth layout area and the eighth layout area, and one or more protection rings are arranged between the seventh layout area and the eighth layout area and between the eighth layout area and the ninth layout area.

[0016] In one or more embodiments of the present invention, a first voltage metal line and a second voltage metal line are further provided in the chip, the first voltage metal line is provided on the other side of the third layout area relative to the second layout area, the first voltage metal line extends into the third layout area and the fourth layout area and is connected to the digital circuit and the voltage conversion circuit, the second voltage metal line is provided on the other side of the first layout area relative to the second layout area, the second voltage metal line extends into the first layout area and the fourth layout area and is connected to the voltage conversion circuit and the analog circuit.

[0017] Compared with the prior art, the layout structure of the digital analog hybrid circuit of the present invention can optimize the complexity of the metal routing connecting the devices in different voltage domains, reduce the circuit performance loss caused by parasitics between complex metal wires, and make the communication flow between signals clear. The metal routing of the power line is convenient, and there is no interference around the metal wiring of each part. The circuit performance loss caused by parasitic parameters is small, and the simulation pass rate is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a schematic diagram of the layout structure in the first embodiment of the present invention.

[0020] Figure 2 4 is a circuit diagram of a voltage conversion circuit in Embodiment 1 of the present invention.

[0021] Figure 3 This is a schematic diagram of the fourth layout area in the first embodiment of the present invention.

[0022] Figure 4 It is a schematic diagram of the layout structure in the second embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0024] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features. Embodiment 1

[0025] like Figure 1 As shown, the layout structure of the digital analog hybrid circuit in one embodiment of the present invention includes: a first layout area 01, a second layout area 02, a third layout area 03, and a fourth layout area 04 that overlaps the first layout area 01, the second layout area 02, and the third layout area 03. A first voltage metal line L1 and a second voltage metal line L2 are also provided in the chip. The digital analog hybrid circuit includes a digital circuit, an analog circuit, and a voltage conversion circuit.

[0026] Specifically, the first layout area 01, the second layout area 02, and the third layout area 03 are arranged in parallel from top to bottom, and the fourth layout area 04 is arranged in the middle of the first layout area 01, the second layout area 02, and the third layout area 03. In other embodiments, the first layout area 01, the second layout area 02, and the third layout area 03 can also be arranged from bottom to top or left to right, and the fourth layout area 04 can also be arranged in other positions.

[0027] The PMOS tube in the analog circuit is arranged in the area of ​​the first layout area 01 that does not overlap with the fourth layout area 04, the NMOS tube in the digital circuit and the NMOS tube in the analog circuit are arranged in the area of ​​the second layout area 02 that does not overlap with the fourth layout area 04, the PMOS tube in the digital circuit is arranged in the area of ​​the third layout area 03 that does not overlap with the fourth layout area 04, and the voltage conversion circuit is arranged in the fourth layout area 04.

[0028] In one embodiment, the analog circuit and the digital circuit also include other devices such as capacitors and resistors, which can be arranged in the chip according to actual needs.

[0029] The first voltage metal line L1 is arranged on the other side of the third layout area 03 relative to the second layout area 02, and the first voltage metal line L1 extends into the third layout area 03 and the fourth layout area 04 and is connected to the digital circuit and the voltage conversion circuit. The second voltage metal line L2 is arranged on the side of the first layout area 01 opposite to the second layout area 02, and the second voltage metal line L2 extends into the first layout area 01 and the fourth layout area 04 and is connected to the voltage conversion circuit and the analog circuit. The first voltage metal line L1 and the second voltage metal line L2 are respectively connected to the first voltage V1 and the second voltage V2, and are used to transmit power supply voltage for the digital circuit, the analog circuit and the voltage conversion circuit.

[0030] In one embodiment, the digital circuit operates in a first voltage domain, and the analog circuit operates in a second voltage domain. The first voltage V1 is a low voltage, and the second voltage V2 is a high voltage.

[0031] In other embodiments, the first voltage V1 and the second voltage V2 may also be other operating voltages used by the digital circuit and the analog circuit, respectively.

[0032] like Figure 1 As shown, the area in the second layout area 02 that does not overlap with the fourth layout area 04 is divided into the fifth layout area 05 and the sixth layout area 06. The NMOS transistor in the analog circuit is set in the fifth layout area 05, and the NMOS transistor in the digital circuit is set in the sixth layout area 06.

[0033] In one embodiment, the fifth layout area 05 and the sixth layout area 06 are located on both sides of the fourth layout area 04. Specifically, the left area after the second layout area 02 is divided by the fourth layout area 04 is the fifth layout area 05, and the right area is the sixth layout area 06. The NMOS tube in the fifth layout area 05 is connected to the PMOS tube in the first layout area 01 to form an analog circuit, and the NMOS tube in the sixth layout area 06 is connected to the PMOS tube in the third layout area 03 to form a digital circuit, so that the digital signal under the first voltage domain and the analog signal under the second voltage domain flow in two non-overlapping areas respectively, and the signal flow is clear and does not interfere with each other.

[0034] In other embodiments, the left area of ​​the second layout area 02 after being divided by the fourth layout area 04 can be divided into the sixth layout area 06, and the right area can be divided into the fifth layout area 05, or the upper half of the left area of ​​the second layout area 02 after being divided by the fourth layout area 04 can be divided into the fifth layout area 05, and the lower half can be divided into the sixth layout area 06, and the upper half of the right area of ​​the second layout area 02 after being divided by the fourth layout area 04 can be divided into the fifth layout area 05, and the lower half can be divided into the sixth layout area 06.

[0035] like Figure 2 As shown, in one embodiment, the voltage conversion circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7 and an eighth MOS tube M8.

[0036] The gate of the first MOS tube M1, the gate of the second MOS tube M2, the gate of the sixth MOS tube M6, and the gate of the eighth MOS tube M8 are connected to the digital circuit to receive the input signal in, the source of the first MOS tube M1 is connected to the first voltage V1, the drain of the first MOS tube M1, the drain of the second MOS tube M2, the gate of the fifth MOS tube M5 and the gate of the seventh MOS tube M7 are connected, the source of the second MOS tube M2, the source of the seventh MOS tube M7, and the source of the eighth MOS tube M8 are connected to the ground voltage V The source of the third MOS tube M3 and the source of the fourth MOS tube M4 are connected to the second voltage V2, the drain of the third MOS tube M3 is connected to the source of the fifth MOS tube M5, the drain of the fourth MOS tube M4 is connected to the source of the sixth MOS tube M6, the gate of the third MOS tube M3 and the drain of the sixth MOS tube M6 are connected to the drain of the eighth MOS tube M8, the gate of the fourth MOS tube M4, the drain of the fifth MOS tube M5 and the drain of the seventh MOS tube M7 are connected to the analog circuit to generate an output signal.

[0037] The first MOS tube M1, the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5 and the sixth MOS tube M6 are all P-type MOS tubes, and the second MOS tube M2, the seventh MOS tube M7 and the eighth MOS tube M8 are all N-type MOS tubes.

[0038] The input signal in is in the first voltage domain, and the voltage conversion circuit converts the input signal in into an output signal in the second voltage domain to match the working requirements of the analog circuit.

[0039] like Figure 1 As shown, the fourth layout area 04 overlaps with the first layout area 01 , the second layout area 02 , and the third layout area 03 to form the seventh layout area 07 , the eighth layout area 08 , and the ninth layout area 09 .

[0040] The PMOS tube working in the first voltage domain in the voltage conversion circuit is set in the ninth layout area 09, the PMOS tube working in the second voltage domain in the voltage conversion circuit is set in the seventh layout area 07, and the NMOS tube in the voltage conversion circuit is set in the eighth layout area 08.

[0041] Specifically, the first MOS tube M1 is arranged in the ninth layout area 09 , the second MOS tube M2 , the seventh MOS tube M7 and the eighth MOS tube M8 are arranged in the eighth layout area 08 , and the third MOS tube M3 , the fourth MOS tube M4 , the fifth MOS tube M5 and the sixth MOS tube M6 are arranged in the seventh layout area 07 .

[0042] like Figure 1 As shown, the eighth layout area 08 is divided into a tenth layout area 10 and an eleventh layout area 11. The NMOS transistor working in the first voltage domain in the voltage conversion circuit is arranged in the eleventh layout area 11, and the NMOS transistor working in the second voltage domain in the voltage conversion circuit is arranged in the tenth layout area 10. That is, the second MOS transistor M2 is arranged in the eleventh layout area 11, and the seventh MOS transistor M7 and the eighth MOS transistor M8 are arranged in the tenth layout area 10.

[0043] Specifically, the tenth layout area 10 is set close to the fifth layout area 05 , and the eleventh layout area 11 is set close to the sixth layout area 06 .

[0044] In one embodiment, the left half of the eighth layout area 08 is divided into the tenth layout area 10 , and the right half is divided into the eleventh layout area 11 .

[0045] Through the above-mentioned area division, the signals of the second voltage domain (high voltage domain) are limited to the first layout area 01, the fifth layout area 05 and the tenth layout area 10, and the signals of the first voltage domain (low voltage domain) are limited to the third layout area 03, the sixth layout area 06 and the eleventh layout area 11, thereby reducing the crosstalk between signals. By dividing the voltage conversion circuit into three parts, it is easy to connect with analog circuits and digital circuits, and it is convenient to optimize the subsequent metal wiring, so that the signal communication between modules is smoother.

[0046] At the same time, by placing the first voltage metal line L1 and the second voltage metal line L2 at both ends of the entire hybrid circuit, it is beneficial to isolate the circuits in different voltage domains, so that the parasitics between them are small, thereby preventing latch up (latch effect) and various secondary effects from affecting the performance of the layout. There is no interference around the first voltage metal line L1 and the second voltage metal line L2, and the post-simulation pass rate is high.

[0047] In other embodiments, other forms of voltage conversion circuits may also be used.

[0048] In other embodiments, the right half of the eighth layout area 08 may be divided into the tenth layout area 10, and the left half may be divided into the eleventh layout area 11. Alternatively, the upper half of the eighth layout area 08 may be divided into the tenth layout area 10, and the lower half may be divided into the eleventh layout area 11.

[0049] like Figure 3 As shown, guard rings are arranged on the outer side of the seventh layout area 07 , the outer side of the eighth layout area 08 , and the outer side of the ninth layout area 09 , and the guard rings are used to reduce interference between circuits and devices.

[0050] Specifically, protection rings are arranged between the seventh layout area 07 and the eighth layout area 08, between the eighth layout area 08 and the ninth layout area 09, and on the other side of the seventh layout area 07 relative to the eighth layout area 08 and on the other side of the ninth layout area 09 relative to the eighth layout area 08. There are two protection rings between the seventh layout area 07 and the eighth layout area 08 and two protection rings between the eighth layout area 08 and the ninth layout area 09.

[0051] In other embodiments, one or more guard rings may be provided between the seventh layout area 07 and the eighth layout area 08 and between the eighth layout area 08 and the ninth layout area 09 according to actual needs. Embodiment 2

[0052] In the layout structure of the digital analog hybrid circuit in one embodiment of the present invention, the first layout area 01, the second layout area 02, the third layout area 03 are sequentially arranged in the chip, and the fourth layout area 04 is arranged overlapping with the first layout area 01, the second layout area 02 and the third layout area 03. The chip is also provided with a first voltage metal line L1 and a second voltage metal line L2. The digital analog hybrid circuit includes a digital circuit, an analog circuit and a voltage conversion circuit.

[0053] Specifically, the fourth layout area 04 is arranged at the edge of the first layout area 01, the second layout area 02 and the third layout area 03. In one embodiment, the fourth layout area 04 is located at the right edge of the first layout area 01, the second layout area 02 and the third layout area 03. In other embodiments, the fourth layout area 04 may be located at the left edge of the first layout area 01, the second layout area 02 and the third layout area 03.

[0054] The PMOS tube in the analog circuit is arranged in the area of ​​the first layout area 01 that does not overlap with the fourth layout area 04, the NMOS tube in the digital circuit and the NMOS tube in the analog circuit are arranged in the area of ​​the second layout area 02 that does not overlap with the fourth layout area 04, the PMOS tube in the digital circuit is arranged in the area of ​​the third layout area 03 that does not overlap with the fourth layout area 04, and the voltage conversion circuit is arranged in the fourth layout area 04.

[0055] In one embodiment, the analog circuit and the digital circuit also include other devices such as capacitors and resistors, which can be arranged in the chip according to actual needs.

[0056] The first voltage metal line L1 is arranged on the other side of the third layout area 03 relative to the second layout area 02, and the first voltage metal line L1 extends into the third layout area 03 and the fourth layout area 04 and is connected to the digital circuit and the voltage conversion circuit. The second voltage metal line L2 is arranged on the side of the first layout area 01 opposite to the second layout area 02, and the second voltage metal line L2 extends into the first layout area 01 and the fourth layout area 04 and is connected to the voltage conversion circuit and the analog circuit. The first voltage metal line L1 and the second voltage metal line L2 are respectively connected to the first voltage V1 and the second voltage V2, and are used to provide power supply voltage for the digital circuit, the analog circuit and the voltage conversion circuit.

[0057] In one embodiment, the digital circuit operates in a first voltage domain, and the analog circuit operates in a second voltage domain. The first voltage V1 is a low voltage, and the second voltage V2 is a high voltage.

[0058] In other embodiments, the first voltage V1 and the second voltage V2 may also be other operating voltages used by the digital circuit and the analog circuit, respectively.

[0059] like Figure 1 As shown, the area in the second layout area 02 that does not overlap with the fourth layout area 04 is divided into the fifth layout area 05 and the sixth layout area 06. The NMOS transistor in the analog circuit is set in the fifth layout area 05, and the NMOS transistor in the digital circuit is set in the sixth layout area 06.

[0060] In one embodiment, the first layout area 01, the fifth layout area 05, the sixth layout area 06 and the third layout area 03 are arranged in sequence from top to bottom. The NMOS tube in the fifth layout area 05 is connected to the PMOS tube in the first layout area 01 and forms an analog circuit, and the NMOS tube in the sixth layout area 06 is connected to the PMOS tube in the third layout area 03 and forms a digital circuit, so that the digital signal under the first voltage domain and the analog signal under the second voltage domain flow in two non-overlapping areas respectively, and the signal flow direction is clear and does not interfere with each other. In other embodiments, the first layout area 01, the fifth layout area 05, the sixth layout area 06 and the third layout area 03 can be arranged in different ways.

[0061] The specific structure and connection method of the voltage conversion circuit in this embodiment are exactly the same as the specific structure and connection method of the voltage conversion circuit in Embodiment 1, and will not be repeated here.

[0062] like Figure 4As shown, the fourth layout area 04 overlaps with the first layout area 01 , the second layout area 02 , and the third layout area 03 to form the seventh layout area 07 , the eighth layout area 08 , and the ninth layout area 09 .

[0063] The PMOS tube working in the first voltage domain in the voltage conversion circuit is set in the ninth layout area 09, the PMOS tube working in the second voltage domain in the voltage conversion circuit is set in the seventh layout area 07, and the NMOS tube in the voltage conversion circuit is set in the eighth layout area 08.

[0064] Specifically, the first MOS tube M1 is arranged in the ninth layout area 09 , the second MOS tube M2 , the seventh MOS tube M7 and the eighth MOS tube M8 are arranged in the eighth layout area 08 , and the third MOS tube M3 , the fourth MOS tube M4 , the fifth MOS tube M5 and the sixth MOS tube M6 are arranged in the seventh layout area 07 .

[0065] like Figure 4 As shown, the eighth layout area 08 is divided into the tenth layout area 10 and the eleventh layout area 11. The NMOS transistor working in the first voltage domain in the voltage conversion circuit is arranged in the eleventh layout area 11, and the NMOS transistor working in the second voltage domain in the voltage conversion circuit is arranged in the tenth layout area 10. That is, the second MOS transistor M2 is arranged in the eleventh layout area 11, and the seventh MOS transistor M7 and the eighth MOS transistor M8 are arranged in the tenth layout area 10.

[0066] Specifically, the tenth layout area 10 is set close to the fifth layout area 05 , and the eleventh layout area 11 is set close to the sixth layout area 06 .

[0067] In one embodiment, the upper half of the eighth layout area 08 is divided into the tenth layout area 10, and the lower half is divided into the eleventh layout area 11, that is, the tenth layout area 10 and the eleventh layout area 11 are arranged in sequence from top to bottom.

[0068] Through the above-mentioned area division, the signals of the second voltage domain (high voltage domain) are limited to the first layout area 01, the fifth layout area 05 and the tenth layout area 10, and the signals of the first voltage domain (low voltage domain) are limited to the third layout area 03, the sixth layout area 06 and the eleventh layout area 11, thereby reducing the crosstalk between signals. By dividing the voltage conversion circuit into three parts, it is easy to connect with analog circuits and digital circuits, and it is convenient to optimize the subsequent metal wiring, so that the signal communication between modules is smoother.

[0069] At the same time, by placing the first voltage metal line L1 and the second voltage metal line L2 at both ends of the entire hybrid circuit, it is beneficial to isolate the circuits in different voltage domains, so that the parasitics between them are small, thereby preventing latch up (latch effect) and various secondary effects from affecting the performance of the layout. There is no interference around the first voltage metal line L1 and the second voltage metal line L2, and the post-simulation pass rate is high.

[0070] In addition, from the overall perspective, the voltage conversion circuit is located on the right side of the entire layout, which makes the analog circuit and digital circuit on the left side more evenly distributed in the layout, further reducing interference between each other and making the layout clearer.

[0071] In this embodiment, protection rings are also provided on the outer sides of the seventh layout area 07, the outer sides of the eighth layout area 08 and the outer sides of the ninth layout area 09, and the setting method of the protection rings is exactly the same as that in the first embodiment, which will not be repeated here.

[0072] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0073] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A layout structure of a digital analog hybrid circuit, characterized in that: The invention comprises a first layout area, a second layout area, a third layout area and a fourth layout area overlapping the first layout area, the second layout area and the third layout area, which are sequentially arranged in the chip. The digital analog hybrid circuit comprises a digital circuit, an analog circuit and a voltage conversion circuit. The PMOS tube in the analog circuit is arranged in an area of ​​the first layout area that does not overlap with the fourth layout area. The NMOS tube in the digital circuit and the NMOS tube in the analog circuit are arranged in an area of ​​the second layout area that does not overlap with the fourth layout area. The area of ​​the second layout area that does not overlap with the fourth layout area is divided into a fifth layout area and a sixth layout area. The NMOS tube in the analog circuit is arranged in the fifth layout area. The NMOS tube in the digital circuit is arranged in the sixth layout area. The PMOS tube in the digital circuit is arranged in an area of ​​the third layout area that does not overlap with the fourth layout area. The voltage conversion circuit is arranged in the fourth layout area.

2. The layout structure of the digital analog hybrid circuit according to claim 1, characterized in that: The first layout area, the fifth layout area, the sixth layout area and the third layout area are set in sequence.

3. The layout structure of the digital analog hybrid circuit according to claim 1, characterized in that: The fifth layout area and the sixth layout area are located on both sides of the fourth layout area.

4. The layout structure of the digital analog hybrid circuit according to any one of claims 1 to 3, characterized in that: The fourth layout area overlaps with the first layout area, the second layout area, and the third layout area to form the seventh layout area, the eighth layout area, and the ninth layout area. The PMOS tube working in the first voltage domain in the voltage conversion circuit is arranged in the ninth layout area, the PMOS tube working in the second voltage domain in the voltage conversion circuit is arranged in the seventh layout area, and the NMOS tube in the voltage conversion circuit is arranged in the eighth layout area.

5. The layout structure of the digital analog hybrid circuit according to claim 4, characterized in that: The eighth layout area is divided into a tenth layout area and an eleventh layout area. The NMOS tube working in the first voltage domain in the voltage conversion circuit is arranged in the eleventh layout area, and the NMOS tube working in the second voltage domain in the voltage conversion circuit is arranged in the tenth layout area.

6. The layout structure of the digital analog hybrid circuit according to claim 5, characterized in that: The tenth layout area is arranged close to the fifth layout area, and the eleventh layout area is arranged close to the sixth layout area.

7. The layout structure of the digital analog hybrid circuit according to claim 4, characterized in that: Guard rings are arranged on the outer sides of the seventh layout area, the outer sides of the eighth layout area and the outer sides of the ninth layout area.

8. The layout structure of the digital analog hybrid circuit according to claim 7, characterized in that: The protection rings are arranged between the seventh layout area and the eighth layout area, between the eighth layout area and the ninth layout area, and on the other side of the seventh layout area relative to the eighth layout area and on the other side of the ninth layout area relative to the eighth layout area. There are one or more protection rings between the seventh layout area and the eighth layout area and between the eighth layout area and the ninth layout area.

9. The layout structure of the digital analog hybrid circuit according to claim 1, characterized in that: The chip is also provided with a first voltage metal wire and a second voltage metal wire. The first voltage metal wire is arranged on the other side of the third layout area relative to the second layout area, the first voltage metal wire extends into the third layout area and the fourth layout area and is connected to the digital circuit and the voltage conversion circuit, and the second voltage metal wire is arranged on the other side of the first layout area relative to the second layout area, the second voltage metal wire extends into the first layout area and the fourth layout area and is connected to the voltage conversion circuit and the analog circuit.

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