Method for reducing bus load, CXL module, processing system and processor chip

Abstract

A method for reducing bus load, a CXL module, a processing system and a processor chip are applied to the computer field, and include a processing system of multiple processing units. The processing unit obtains configuration information of a consistent cache area through a cache consistency configuration interface, and configures a part of the cache area of ​​the processing unit as a consistent cache area, so as to use the consistent cache area to cache data in a shared memory of multiple processing units. The CXL module can obtain configuration information of a shared memory through a shared memory configuration instruction of a shared memory configuration interface, and configure a part of the memory area in the memory medium as the shared memory. The disclosed embodiment can prevent the problem of excessive bus load caused by operations to maintain cache consistency.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the computer field, and more specifically, to a method for reducing bus load, a CXL module, a processing system, and a processor chip. Background Art

[0002] In some multi-processor architectures, multiple processor chips are connected through a bus. The processor chip is provided with a processor and a memory. The memory connected to the processor based on a high-bandwidth interface can be used as a cache for the processor to provide high-performance computing capabilities. The multi-processor architecture can use a cache consistency protocol to make the changes made by one processor visible to all other processors. It is not possible for a processor to modify the data but other processors still see the old data. At the same time, it is necessary to ensure that the access order of different processors to shared data conforms to the set operation order to prevent data inconsistency caused by out-of-order execution or concurrent access. This mechanism can improve system performance and concurrent access efficiency while ensuring data correctness. Summary of the invention

[0003] An embodiment of the present disclosure provides a CXL module, the CXL module comprising a CXL controller and a memory medium connected to the CXL controller, the CXL controller being configured to perform the following processing:

[0004] Receive and parse a shared memory configuration instruction to obtain configuration information of the shared memory; wherein the shared memory is a memory area shared by multiple processing units connected to the CXL module;

[0005] Determining an address range of the shared memory according to the configuration information of the shared memory;

[0006] According to the address range of the shared memory, part of the memory area in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

[0007] The embodiment of the present disclosure further provides a shared memory configuration method, which is applied to a CXL module, wherein the CXL module includes a CXL controller and a memory medium connected to the CXL controller, and the method includes:

[0008] Receive and parse a shared memory configuration instruction to obtain configuration information of the shared memory; wherein the shared memory is a memory area shared by multiple processing units connected to the CXL module;

[0009] Determining an address range of the shared memory according to the configuration information of the shared memory;

[0010] According to the address range of the shared memory, part of the memory area in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

[0011] The above-mentioned embodiment of the present disclosure expands the CXL protocol and adds an interface for shared memory configuration. The CXL module parses the shared memory configuration instructions defined by the interface to obtain the configuration information of the shared memory; then determines the address range of the shared memory based on the configuration information of the shared memory, thereby configuring part of the memory area in the memory medium as the shared memory, and only performs cache consistency maintenance on the data in the shared memory. That is, the size of the shared memory in the CXL module can be limited by configuration, and the CXL module only performs cache consistency maintenance on the data in the shared memory. The embodiment of the present disclosure limits the size of the shared memory in the CXL module to a set range by configuration, which can prevent the operation of maintaining cache consistency from being too frequent, resulting in the problem of excessive bus load.

[0012] The present disclosure also provides a processing system, including a bus and a plurality of processing units, wherein the plurality of processing units are connected via the bus, wherein the processing units are all provided with a cache and a configuration interface having cache coherence, and the processing units are configured as follows:

[0013] Acquiring configuration information of a consistent cache area through the cache consistency configuration interface, and determining an address range of the consistent cache area according to the configuration information of the consistent cache area;

[0014] According to the address range of the consistent cache area, a part of the cache area of ​​the processing unit is configured as a consistent cache area, so as to use the consistent cache area to cache data in the shared memory of a plurality of the processing units.

[0015] The embodiment of the present disclosure further provides a method for reducing bus load, which is applied to a system including multiple processing units, wherein the multiple processing units are connected via a bus, and the multiple processing units are all provided with a cache and a configuration interface having cache consistency, and the method includes:

[0016] The processing unit obtains configuration information of a consistent cache area through the configuration interface of the cache consistency, and determines an address range of the consistent cache area according to the configuration information of the consistent cache area;

[0017] The processing unit configures a partial area of ​​the cache of the processing unit as a consistent cache area according to the address range of the consistent cache area, so as to use the consistent cache area to cache data in the shared memory of multiple processing units.

[0018] An embodiment of the present disclosure further provides a processor chip, including a processor core and a cache, wherein the processor core is configured to execute the method for reducing bus load performed by the processing unit as described in any embodiment of the present disclosure.

[0019] The embodiments of the present disclosure further provide a non-transitory computer storage medium storing a computer program. When the computer program is executed by a processor, the method for reducing the bus load described in any embodiment of the present disclosure can be implemented.

[0020] The embodiments of the present disclosure further provide a computer product. When the computer product is executed by a processor, the method for reducing the bus load described in any embodiment of the present disclosure can be implemented.

[0021] The above-mentioned embodiments of the present disclosure are based on a system in which multiple processing units are connected through a bus, and a cache consistency configuration interface is newly added. The processing unit can obtain the configuration information of the consistent cache area through the cache consistency configuration interface, and determine the address range of the consistent cache area according to the configuration information of the consistent cache area; then, according to the address range of the consistent cache area, a part of the cache area of ​​the processing unit is configured as a consistent cache area, so as to use the consistent cache area to cache the data in the shared memory of multiple processing units. That is, the size of the consistent cache area of ​​the processing unit can be limited by configuration, because the data of the shared memory of multiple processing units is only cached to the consistent cache area of ​​each processing unit. The embodiment of the present disclosure limits the size of the consistent cache area of ​​multiple processing units within a set range by configuration, which can prevent the problem of excessive bus load caused by the operation of maintaining cache consistency when there are too many cache lines in the consistent cache area.

[0022] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0024] Figure 1 is a schematic diagram of a multi-processor architecture according to an embodiment of the present disclosure;

[0025] Figure 2 is a flow chart of a method for reducing bus load according to an embodiment of the present disclosure;

[0026] Figure 3is a schematic diagram of the partitioning of the cache area of ​​a processing unit according to an embodiment of the present disclosure;

[0027] Figure 4 is a schematic diagram of memory area division in a CXL module according to an embodiment of the present disclosure;

[0028] Figure 5 It is a schematic diagram of address mapping between a coherent cache area in a processor chip and shared memories in a plurality of CXL modules according to an embodiment of the present disclosure;

[0029] Figure 6 is a schematic diagram of searching cache data according to an address according to an embodiment of the present disclosure;

[0030] Figure 7 The figure is a flowchart of a shared memory configuration method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it is apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0032] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form an inventive solution protected by the present disclosure. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another inventive solution protected by the present disclosure. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0033] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be appreciated by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0034] Figure 1 The figure shows an exemplary multi-processor architecture of an embodiment of the present disclosure, which includes multiple processors interconnected by a bus, and the multiple processors are respectively located in different processor chips, and the processor chips provide CXL interfaces to the outside and are interconnected by CXL buses. The processor chip may include one or more processor cores (only one is shown in the figure). However, the processors of the multi-processor architecture may also be connected by other types of buses such as PCIe buses. Multiple processors can be connected by an interconnection network, and the bus between processors can be shared or independent, depending on the system design, and the bus connection shown in the figure is only schematic.

[0035] The processor of this embodiment can be a GPU, a CPU or other types of processors. One or more processor cores can also be integrated in a processor chip, and the types of these processor cores can be the same or different. The processor chip is encapsulated with a memory medium and a processor core (core). The memory medium and the processor core are connected based on a high-bandwidth interface, and its capacity and bandwidth are much higher than the general DDR interface. The memory medium in the illustrated example is an embedded DRAM integrated in the processor chip, such as HBM, GDDR6X and other types of media. These memory media can be used as a cache for the processor to provide high-performance computing capabilities. The processor chip may also include other memory interfaces (such as DDR interfaces) not shown in the figure to connect external memory devices, as well as clock circuits, memory management and other parts.

[0036] In a multi-processor architecture, multiple processors can access the same memory area, which is called shared memory. The shared memory of multiple processors can be set up with one or more areas, which can be areas in the processor's local memory, or areas in the memory of an external device such as a CXL module, or both areas in the processor's local memory and areas in the memory of an external device. In a multi-processor architecture, a processor can have its own cache, and it is necessary to ensure that access to shared data between different processors is consistent. To this end, it is necessary to maintain the consistency of data in shared memory in the cache of each processor based on a cache consistency protocol (referred to as cache consistency) to improve system performance and concurrent access efficiency.

[0037] Operations related to maintaining cache coherence in multiprocessor architectures can include:

[0038] The processor needs to always pay attention to the cache line (CacheLine) related operations on the bus. The operations of other processors on the CacheLine will trigger bus broadcast events, thereby increasing the bus load.

[0039] After the processor receives the bus sniffing event, it needs to compare it with the cache line in the cache area corresponding to the processor to decide whether to modify the state of the current cache line.

[0040] In addition, when the processor core (such as x64) uses a store buffer, the latency will increase significantly when writing the store buffer data back to the main memory based on the CXL interface, which will also affect the communication overhead of the bus and increase the bus load.

[0041] CXL is developed based on PCIe 5.0 and runs on the PCIe physical layer. According to the characteristics of memory access, CXL is divided into three sub-protocols: CXL.io, CXL.mem and CXL.cache. Correspondingly, CXL devices are divided into the first type of CXL devices (Type1 CXL device, referred to as Type1 device), the second type of CXL devices (Type2 CXL device, referred to as Type2 device) and the third type of CXL devices (Type3 CXL device, referred to as Type3 device). Type2 devices and Type3 devices are both equipped with device memory, which can be DDR, HBM (High Bandwidth Memory) and other types. Taking Type2 devices as an example, Type2 devices can be accelerator cards (such as GPUs) in actual application scenarios. The Host provides data and the accelerator card is responsible for calculation. The Host Direct Management (HDM) model allows the host to directly manage and control the storage space on the Type2 device, dynamically allocate and configure device memory according to application requirements, and directly perform read and write operations. Type 3 devices can provide large-capacity DRAM for the Host and can also support persistent media (ie, non-volatile media, such as flash memory chips).

[0042] Alternatively, if Figure 1 As shown, multiple processors in the multi-processor architecture are also connected to the CXL module via a CXL bus. The CXL module disclosed herein refers to a CXL device including a memory medium, such as a Type 2 device, a Type 3 device, etc. As shown in the figure, the CXL module includes a control chip and one or more memory media connected to the control chip, wherein the memory medium is DRAM particles as an example in the illustrated example. The memory in the CXL module can be used as an extended memory for the processor connected thereto, and the extended memory can be used to store data shared by multiple processors or multiple processing cores, such as storing data of types such as global variables as a shared memory.

[0043] In the multi-processor architecture of this embodiment, a large-capacity and high-bandwidth memory medium is used inside the processor chip, the available cache space is increased, the processor chips are connected based on the CXL bus, the memory usage range can be expanded based on the CXL module, and the available memory range will also increase, which will introduce the following problems:

[0044] 1) The amount of data cached by each processor increases, resulting in an increase in the load overhead of maintaining cache coherence on the bus; in extreme cases, if only one cacheline is maintained to maintain cache coherence, the related signaling interactions will be minimized.

[0045] 2) The access latency of CXL is longer than that of local DDR. After the current CPU broadcasts on the bus, the broadcast event may trigger other processors to first access CXL storage (such as refreshing the cache data of the current processor), and then give feedback on the broadcast event to the current CPU, which will increase the processing latency and increase the bus load. One way is the local write operation (Local Write) of the host processor (Host CPU). If the cache line (Cacheline) at the same position in the CXL device is in the modified state at this time, the data needs to be written back to the main memory and the state needs to be modified; at the same time, the state of the current host processor cache line is changed to Modified (the latency of the CXL device to write data back to the main memory is long). The long feedback time of data leads to slow control information interaction, and the long access latency will also cause bus load congestion. Each cacheline will contribute to the load of bus interaction. When the cache that needs to maintain cache consistency is large, that is, the number of cachelines is large, these problems are aggravated.

[0046] 3) The high latency of CXL is due to the CXL path. When the cache consistency information reaches the CXL device, the algorithm for finding a specific cacheline based on a specific address also has a latency. When the cache is large, the load of locating the cacheline inside the processor chip increases, and the cacheline positioning efficiency is low, which indirectly leads to an increase in feedback latency, that is, the latency increases with the number of cachelines. Cacheline positioning exists on the host side (such as the processor side) or the CXL device side.

[0047] Therefore, the bus load is related to the number of cachelines used to maintain consistency and the consistency signaling interaction delay, which in turn is related to the efficiency of locating cachelines on the device and host sides.

[0048] Although the above example uses a system with a multi-processor architecture, other systems including multiple processing units also have the above problems. For example, in some multi-core chipsets, there are also problems with sharing memory and maintaining cache consistency between multiple processor cores. If the cache set for the processor core is too large, it will also cause the bus load between the multiple processor cores to be too large. For another example, distributed systems or other systems with large-scale parallel computing that include multiple processors and require cache consistency maintenance also have similar problems.

[0049] In actual application scenarios, the scope of multi-core process shared memory is relatively small; for example, in the training process based on AI or large language models, there is less interaction data between layers. From the perspective of CPU or GPU parallelism, this means that there are fewer scenarios for large-scale interaction data between cores. In other words, in some scenarios, it is not necessary to maintain cache consistency for all caches and external memories.

[0050] For a system with a processing unit (such as a processor or a processor core) having a large cache space and requiring cache consistency maintenance, in some embodiments of the present disclosure, a cache consistency configuration interface is added (such as defining corresponding configuration instructions) to configure the cache area of ​​the processing unit for cache consistency, thereby reducing the number of cachelines used for cache consistency, thereby reducing the bus overhead of the system maintaining consistency. In some embodiments of the present disclosure, a cache consistency configuration interface is added to configure the area of ​​shared memory of multiple processing units, thereby reducing the capacity of the shared memory, thereby reducing the bus overhead of the system maintaining consistency. In some embodiments of the present disclosure, the cacheline search algorithm in the cache is improved to improve the cacheline positioning efficiency, so that the feedback delay is reduced, thereby reducing the bus overhead of the system maintaining consistency.

[0051] It should be noted that although the embodiments of the present disclosure are more effective when applied to a processing unit with a larger cache space, the application of the embodiments of the present disclosure is not limited by the size of the cache space. It can also be applied to a system composed of processing units with smaller cache spaces that needs to maintain cache consistency, and can also reduce the load on the bus.

[0052] An embodiment of the present disclosure provides a method for reducing bus load, which is applied to a system including multiple processing units, wherein the multiple processing units are connected via a bus, and the multiple processing units are all provided with a cache and a configuration interface having cache coherence, and the method includes:

[0053] Step 110, the processing unit obtains configuration information of the consistent cache area through the cache consistency configuration interface, and determines the address range of the consistent cache area according to the configuration information of the consistent cache area;

[0054] Step 120: The processing unit configures a partial area of ​​the cache of the processing unit as a consistent cache area according to the address range of the consistent cache area, so as to use the consistent cache area to cache data in the shared memory of multiple processing units.

[0055] By using the method of this embodiment, the cache of the processing unit can be divided into two parts, such as Figure 3As shown, one part is a coherent cache area (Coherence Area), and the other part is other cache areas, which are marked as non-coherence cache areas (Non Coherence Area) in the figure. The processing unit uses the coherence cache area to cache the data in the shared memory of multiple processing units, which means that when a processing unit caches the data in the shared memory of multiple processing units, they are all cached to the coherence cache area configured for the processing unit, and will not be cached to the non-coherence cache area. This embodiment can set a cache coherence configuration interface for one or more processing units in the system. When setting a cache coherence configuration interface for multiple processing units, the cache coherence configuration interfaces of the multiple processing units can be independent of each other, or a unified interface can be used, and the types of configuration interfaces of different processing units can be the same or different.

[0056] Figure 3 The non-coherent cache area in the memory can also be subdivided into multiple areas of different properties to meet actual needs. In one example, the embedded DRAM (such as HBM) in the processor chip can be used as the cache of the processing unit. The capacity of the cache is much larger than the traditional cache and can reach the GB level.

[0057] There is no interface for dividing the cache into the above-mentioned areas in the related art. This embodiment can divide a part of the area in the cache of the processing unit as the consistent cache area of ​​the processing unit by adding a cache consistency configuration interface, so that the size of the consistent cache area of ​​the processing unit can be limited by configuration, instead of using all the cache space of the processing unit to cache the data in the shared memory of multiple processing units. Because the data of the shared memory of multiple processing units is only cached in the consistent cache area of ​​each processing unit, by limiting the size of the consistent cache area within a set range, it can prevent the problem of excessive bus load caused by the operation of maintaining cache consistency when there are too many cache lines in the consistent cache area.

[0058] The processing unit of this embodiment is a processor or a processor core. The types of multiple processing units in the system may be the same or different. In one example, multiple processing units are processors, and the system including multiple processing units may be a system with a multi-processor architecture; in another example, multiple processing units are processor cores, and the system including multiple processing units may include a processor with a multi-core architecture; in another example, some of the multiple processing units are processors and the other part is a processor core, then the system includes a processor with a multi-core architecture and a single-core processor. The processor core may be a CPU core but is not limited thereto. It should also be noted that in the system to which the method of this embodiment is applied, as long as there are multiple processing units connected by a bus and provided with a cache, it is not required that all processing units in the system are connected by a bus, nor is it required that all processing units are provided with their own cache.

[0059] In an exemplary embodiment of the present disclosure, the capacity of the cache of at least one of the processing units is greater than or equal to 128M or 256M. The cache space may be provided by an embedded high-bandwidth memory integrated in the processor chip. However, the present disclosure is not limited thereto, and the capacity of the cache of multiple processing units may be less than 128M.

[0060] In an exemplary embodiment of the present disclosure, the configuration information of the coherent cache area includes the size of the coherent cache area, and may also include location information of the coherent cache area such as a starting location.

[0061] In an exemplary embodiment of the present disclosure, the processing unit obtains configuration information of the consistent cache area through the cache consistency configuration interface, including: the processing unit receives the cache area configuration instruction issued by the central control hardware unit of the system, parses the cache area configuration instruction, and obtains the configuration information of the consistent cache area; or, the processing unit obtains the configuration information of the consistent cache area according to the programming interface provided by the system software; wherein, in this embodiment, the sizes of the consistent cache areas configured for different processing units among the multiple processing units can be the same or different.

[0062] In an example of the present embodiment, the processing unit receives a cache area configuration instruction issued by a central control hardware unit, parses the cache area configuration instruction, and obtains the configuration information of the consistent cache area. When a server including multiple processing units is included in the system, the central control hardware unit may be, for example, the basic input / output system (BIOS) of the server, and the setting of the consistent cache area is started by the BIOS. In one case, the configuration information of the consistent cache area may include the size and position of the consistent cache area, and the processing unit can determine the address range of the consistent cache area according to the configuration information of the consistent cache area. In another case, the configuration information of the consistent cache area includes the size of the consistent cache area, and the processing unit determines the address range of the consistent cache area in combination with the default position of the locally stored consistent cache area or the position of the consistent cache area obtained by other means. In this article, a server with multiple processing units refers to an entity in the system that can perform configuration management on multiple processing units. Such as may include but not limited to the BIOS hardware unit of the server or the server firmware.

[0063] In another example of this embodiment, the processing unit obtains the configuration information of the consistent cache area based on the programming interface provided by the system software. The operating system load maintains and manages all hardware resources of the computer device, and the processing unit can obtain the configuration information of the consistent cache area based on the application programming interface (API) provided by the operating system. For example, the CPU can provide a graphical interface to determine the size of the consistent cache area according to the user's input. For example, two fields that can set the size are provided for Cache: Coherence and Non Coherence, and the size of the Coherence field set by the user is used as the size of the consistent cache area configured by the user, and the size of the Non Coherence field set by the user is used as the size of the non-consistent cache area configured by the user. The graphical interface can also allow the user to configure the location of the consistent cache area. At this time, the configuration information of the consistent cache area obtained by the processing unit through the graphical interface includes the size and location of the consistent cache area. In the case where the graphical interface only allows the user to configure the size of the consistent cache area, the location of the consistent cache area can be obtained using a pre-stored default location or other methods. The processing unit can determine the address range of the consistent cache area in the cache based on the size of the consistent cache area in the configuration information and the location of the consistent cache area.

[0064] In an example of this embodiment, there are different types of processing units in the system, such as GPU, CPU, etc. The cache sizes of different processing units are not necessarily the same, and the sizes of the consistent cache areas configured for different processing units may also be the same or different.

[0065] In an exemplary embodiment of the present disclosure, the system further includes an external device connected to the plurality of processing units via a bus, and the external device is provided with a memory medium; the method further includes:

[0066] The external device receives and parses the shared memory configuration instruction to obtain the configuration information of the shared memory, and determines the address information of the shared memory according to the configuration information of the shared memory;

[0067] The external device configures part of the memory area in the device as the shared memory of the multiple processing units according to the address range of the shared memory. Herein, the shared memory may also be referred to as a shared memory area, that is, a memory area accessible to the multiple processing units.

[0068] The above-mentioned external device refers to a device located outside the processor chip, rather than a device outside the system. Although the present embodiment uses part of the memory area of ​​the memory medium in the external device as a shared memory, the present disclosure is not limited to this. In other embodiments, part of the memory area of ​​the memory medium embedded in the processor chip can also be configured as a shared memory. In this case, the configuration of the shared memory can be completed by the processing unit according to the shared memory configuration instruction, that is, the processing unit receives and parses the shared memory configuration instruction, obtains the configuration information of the shared memory, and determines the address information of the shared memory according to the configuration information of the shared memory; and, the processing unit configures part of the memory area in the local memory medium as the shared memory of multiple processing units according to the address range of the shared memory.

[0069] In one example, the configuration information of the shared memory carried by the shared memory configuration instruction includes the size and position (such as the starting position) of the shared memory, and the external device can determine the address information of the shared memory based on the configuration information obtained by parsing the shared memory configuration instruction. In another example, the configuration information of the shared memory carried by the shared memory instruction includes the size of the shared memory, and the external device needs to parse the shared memory configuration instruction to obtain the size of the shared memory, and then combine it with the default position preset for the shared memory or the position of the shared memory obtained by other means to obtain the configuration information of the shared memory, and then determine the address information of the shared memory.

[0070] In an exemplary embodiment of the present disclosure, the external device includes a CXL module that communicates with the plurality of processing units through a CXL interface, the CXL module including a controller (such as a control chip or a control chipset) and a group of memory chips connected to the controller; the shared memory configuration instruction is sent to the CXL module by the interconnection network manager of the system through the CXL interface. The interconnection network manager (FM: Fabric Manager) in this article refers to an entity that can be used to configure and manage CXL devices. This embodiment adds a shared memory configuration function to the CXL interface, and the shared memory of the CXL module can be configured through the shared memory configuration instruction; the interconnection network manager can be integrated in the processing unit in the system, or it can be independent of any processing unit in the system and set at a different location from the plurality of processing units in the system, such as it can be implemented using a processing unit outside the system.

[0071] like Figure 1 and Figure 4 In the example shown, the CXL module includes three DRAM particles. When configuring shared memory, the control chip in the CXL module can configure one of the DRAM particles as shared memory for multiple processing units, and the other memory areas, that is, the other two DRAM particles, can be called non-shared memory or non-shared memory areas. It is easy to understand that the division method shown in the figure is only schematic. The shared memory can also be a partial area in a DRAM particle, or it can be composed of areas in multiple DRAM particles. In a module composed of multiple DRAM particles, shared memory and non-shared memory are presented to the outside as address ranges (logical concepts).

[0072] Although the present embodiment uses the CXL module as an example of an external device, in other embodiments, the external device may also be a memory chip such as a DDR chip connected to a processor chip through a memory interface.

[0073] In an exemplary embodiment of the present disclosure, the internet network manager also sends the configuration information of the shared memory to the multiple processing units respectively; in another exemplary embodiment of the present disclosure, the internet network manager also sends the configuration information of the shared memory to the server of the multiple processing units, and the server sends the configuration information of the shared memory to the multiple processing units respectively to complete the entire configuration process. In this case, the server can determine the configuration information of the consistent cache area in the multiple processing units in combination with the configuration information of the shared memory, carry the configuration information of the multiple consistent cache areas in multiple cache area configuration instructions respectively, and send them to the multiple processing units respectively through the central control hardware unit of the system. Among them, the configuration information of the shared memory includes the size of the shared memory, and the configuration information of the consistent cache area includes the size of the consistent cache area. The server determines the size of the consistent cache area in the multiple processing units in combination with the configuration information of the shared memory. For example, the size of the configured consistent cache area can be positively correlated with the size of the shared memory, thereby coordinating the size of the shared memory and the consistent cache area so that the two are adapted to achieve better efficiency (if the size of the shared memory and the consistent cache area is very different, such as the shared memory is large and the consistent cache area is too small, the speed of searching the shared memory data in the cache will be too slow, and if the shared memory is small and the consistent cache area is too large, it will cause a waste of resources). After completing the configuration, the server can send cache area configuration instructions to the multiple processing units respectively through the central control hardware unit. The central control hardware unit can be a part of the server, or the central control hardware unit is independent of the server and can communicate with the server.

[0074] In an exemplary embodiment of the present disclosure, the method further includes: the processing unit establishes a first address mapping relationship between the shared memory and the consistent cache area according to the address range of the shared memory and the address range of the consistent cache area. In this embodiment, a consistent cache area can establish an address mapping relationship with one or more shared memories, and the first address mapping relationship between the shared memory and the consistent cache area can use direct connection mapping, group connection mapping or full connection methods. After the processing unit configures the consistent cache area according to the address range of the consistent cache area, combined with the address range of the shared memory obtained previously, any of the three mapping methods can be used to establish the first address mapping relationship between the consistent cache area and the shared memory.

[0075] like Figure 5 , which shows the address mapping relationship between the coherent cache area of ​​a cache in a processor chip under a multi-processor architecture and the shared memory of the memory medium in multiple CXL modules.

[0076] The above-mentioned first address mapping relationship reflects the relationship between the storage location of the data in the shared memory and the cache location in the consistent cache area, and the processing unit can generate a physical address or a virtual address for accessing the data based on this, so as to search for the data in the shared memory in the consistent cache area. The memory management unit (MMU) in the processor can participate in address management such as generating an address for accessing data in the shared memory, and the generated address can be used as the input address of the Cache. When the relative position of the MMU and the cache is different, the input address can be a virtual address (the Cache is located between the CPU and the MMU) or a physical address (the MMU is located between the Cache and the CPU).

[0077] In an example of this embodiment, the processing unit may also establish a second address mapping relationship between other cache areas of the processing unit except the consistent cache area and other memory areas of the external device except the shared memory according to the address range of the shared memory and the address range of the consistent cache area. Figure 3 and Figure 4 The second address mapping relationship is to establish an address mapping relationship between the non-coherent cache area in the cache and the non-shared memory in the CXL module, and the address mapping relationship can be established in a direct connection mapping, a group connection mapping or a full connection manner. In another example of this embodiment, the processing unit only establishes an address mapping relationship between a part of the non-coherent cache area of ​​the processing unit and a part of the non-shared memory of the external device, that is, a part of the memory area in the external device does not need to be mapped with the cache.

[0078] In an exemplary embodiment of the present disclosure, the coherent cache area is divided into a plurality of cache groups, each cache group includes a plurality of cache lines; the address used by the processing unit when accessing the data in the shared memory includes the following fields: Tag meta 、Tag data and Offset; or include the following fields: Tag meta 、Index meta 、Tag data and Offset;

[0079] in:

[0080] Tags meta is a field used to identify the consistency cache area;

[0081] Index meta A field for identifying a cache group in the coherent cache area;

[0082] Tagsdata A field for identifying a cache line of a cache group in the coherent cache region;

[0083] Offset is a field used to identify data offset.

[0084] On the basis of dividing the cache into a consistent cache area and an inconsistent cache area through a configuration interface, this embodiment further improves the address of accessing data and adds a field Tag for distinguishing the consistent cache area and the inconsistent cache area. meta For example, you can use the value of 1 bit data to identify the meta When it is 0, it means that the data to be accessed may be cached in the non-consistent cache area. meta When it is 1, it means that the data to be accessed may be cached in the consistent cache area. Therefore, there is no need to search and locate in the entire cache range, which can improve the efficiency of positioning. In addition, you can also set the field Index meta The search range is located in the cache group in the consistent cache area, thereby further improving the efficiency of positioning. The improvement of cache line positioning efficiency can reduce the latency of accessing data in the shared memory, and the reduction of access latency is conducive to avoiding bus congestion.

[0085] Although the fields included in the address of this embodiment are not limited to including Tag meta 、Tag data and Offset, or including Tags meta 、Index meta 、Tag data and Offset, and other fields. For example, if the address includes the Tag field meta 、Index meta 、Tag data and Offset, also includes a meta The field index for locating the cache subgroup in the identified cache group data ,

[0086] In an exemplary embodiment of the present disclosure, the system is configured with multiple shared memories, and the memory media to which different shared memories belong have different characteristics; the multiple cache groups divided by the consistent cache area correspond one-to-one to the multiple shared memories; wherein the characteristics of the memory medium include any one or more of latency and bandwidth. Dividing the cache groups in the consistent cache area according to the characteristics of the memory medium to which the shared memories belong can unify the division standards and facilitate interconnection between devices from different manufacturers. Index of this embodiment metaYou can define sharing between several CXL DRAMs, that is, group the CXL DRAMs in the system, and divide different cache groups according to the latency, bandwidth and other characteristics of the external memory media. For example, you can map some cache groups to slower memory media (such as CXL based shared SSD), and other cache groups to faster memory media (such as CXL based DRAM). The memory media of CXL modules in the same cache group have the same access latency, and the corresponding Index meta The same makes it easier for processing units to use the same cacheline access strategy to access.

[0087] In an exemplary embodiment of the present disclosure, the method further includes: when the processing unit searches for data in the shared cache area in the cache, according to the tag in the address meta、 Index meta Determine the cache group in the consistent cache area, and then according to the tag in the address data A cache line that caches the data is searched in the determined cache group.

[0088] In one example of the embodiment, Tag meta It has multiple values, one of which indicates that the cache area of ​​the data is the consistent cache area; Index meta An index representing a cache group in the coherent cache region;

[0089] The processing unit firstly processes the address according to the tag in the address. meta、 Index meta Determine the cache group in the consistent cache area, and then according to the tag in the address data Searching for a cache line that caches the data in the determined cache group includes:

[0090] According to the Tag in the address meta The value of the metadata table of the consistent cache area is searched, and each record in the metadata table includes the following fields: Tag meta and cache group offset; where Tag meta The value of indicates that the cache area of ​​the data is the coherent cache area, and the value of the cache group offset indicates the position offset of the cache group in the record in the coherent cache area;

[0091] According to the Index in the address meta The value of the address is used to find the corresponding record in the metadata table, and then the search range in the consistent cache area is determined according to the cache group offset in the corresponding record; and according to the tag in the address dataThe corresponding cache line is searched in the search range to determine whether the cache is hit.

[0092] In one example of the present embodiment, the size of the cache group in the consistent cache area can be a fixed setting. In another example, the size of the cache group in the consistent cache area can be variable, such as calculated according to the size of the corresponding shared memory combined with a preset algorithm. The size of the cache group can be represented by the data of the cache lines included in the cache group but is not limited to this. In the case where the size of the cache group can be changed, the field "cache group size" can be added to the metadata table to record it, or it can be calculated based on other metadata (such as the corresponding shared memory size), or determined based on the cache group offset in the next record. In the metadata table of the consistent cache area, other fields can also be set, such as a replacement flag can be set to indicate the replacement mechanism of the cache lines in the cache group.

[0093] The metadata table of the above-mentioned consistent cache area can be established in the process of setting the cache consistent area, and the values ​​of fields such as the cache group offset in the record can be generated in the configuration process.

[0094] like Figure 6 In the example shown, the address generated by the processor (CPU or GPU) (taking the physical address as an example) includes four fields in sequence: region tag (Tag meta ), cache group flag (Index meta ), Tag data ) and offset. In the metadata table of the consistent cache area, each record corresponds to a cache group in the consistent cache area, including the following fields: Area Tag meta ), replacement flag (Ctrl flag) and cache group offset (Cacheline Area Offset) and other fields. When the accessed data is data in the shared memory, the Tag in the input address of the access cache meta The value of the tag in the metadata table meta The value of is the same, and Index meta It can be regarded as the index recorded in the metadata table of the consistent cache area, so according to the tag in the address meta and Index meta The value of can locate a record in the metadata table. By searching the fields Ctrl flag and Cacheline Area Offset of the record, the replacement mechanism of the cache group can be determined, and the position offset of the corresponding cache group in the consistent cache area can be found. Each cache line in the consistent cache area includes the field Tag data and cached data, and look for a cache line tag within the cache group. dataThe value is equal to the Tag in the address data If the value is found, it means a cache hit, and the required data can be extracted according to the value of Offset in the address; if not found, it means a cache miss, and the shared memory can be accessed according to the address to read the corresponding data.

[0095] The above-mentioned metadata table and other information related to cache consistency maintenance can be maintained by a designated processor in the system, such as a main processor. The main processor can manage and control the consistent cache area of ​​all processing units in the system, or the consistent cache area of ​​all processing units in the system and the shared memory of the system, including controlling the ownership of the cache line.

[0096] In order to improve the location efficiency of CacheLine, this embodiment can add a Meta area in the Coherence Area to describe the location information of the corresponding CacheLine. According to the physical address generated by the processor, the relevant fields of the metadata are defined, such as Tag Meta , Index meta ; By introducing Meta-related fields, the cachelines of the consistent cache area can be further grouped (such as grouped according to external memory characteristics), reducing the number of cachelines in the group. When searching for a specific cacheline, the number of cacheline comparisons in the group is reduced. The existing solution is to compare all cachelines in a specific group (identified by index) based on the tag value, which is applicable when the cache space is small; when the cache space is large, the efficiency is low. This embodiment can improve the efficiency of cacheline positioning.

[0097] The size of the cache inside the CPU usually depends on the specific implementation of the CPU manufacturer. For the cache, the CPU only provides a static information description and does not provide an interface that can be changed and set. In view of this situation, the above-mentioned embodiment of the present disclosure proposes a configuration interface for setting a consistent cache area, and also proposes a configuration interface for setting a shared memory. The cache and shared memory inside the CPU can be configured to set the size of the consistent cache area and the size of the shared memory. When the internal cache space of the processor chip is too large, the problem of high bus load caused by consistency maintenance between multiple processors or multiple processor cores can be solved, and the positioning efficiency of cache lines can also be improved.

[0098] An embodiment of the present disclosure also provides a processing system, as shown in Figure 1 and Figure 5The processing system includes a bus and a plurality of processing units, wherein the plurality of processing units are connected via the bus, each of the processing units is provided with a cache and has a configuration interface for cache coherence, and the processing units are configured as follows:

[0099] Acquiring configuration information of a consistent cache area through the cache consistency configuration interface, and determining an address range of the consistent cache area according to the configuration information of the consistent cache area;

[0100] According to the address range of the consistent cache area, a part of the cache area of ​​the processing unit is configured as a consistent cache area, so as to use the consistent cache area to cache data in the shared memory of a plurality of the processing units.

[0101] In an exemplary embodiment of the present disclosure, the processing unit is a processor or a processor core; the cache capacity of at least one of the processing units is greater than or equal to 128M or 256M; and the configuration information of the consistent cache area includes the size of the consistent cache area.

[0102] In an exemplary embodiment of the present disclosure,

[0103] The processing system further comprises: a central control hardware unit configured to issue a cache region configuration instruction to the processing unit, carrying configuration information of the coherent cache region;

[0104] The processing unit obtains configuration information of the consistent cache area through the cache consistency configuration interface, including: receiving a cache area configuration instruction issued by the central control hardware unit, parsing the cache area configuration instruction, and obtaining the configuration information of the consistent cache area;

[0105] The sizes of the coherent cache areas configured for different processing units are the same or different.

[0106] In an exemplary embodiment of the present disclosure, the processing unit obtains the configuration information of the consistent cache area through the cache consistency configuration interface, including: the processing unit obtains the configuration information of the consistent cache area based on a programming interface provided by system software.

[0107] In an exemplary embodiment of the present disclosure,

[0108] The system further comprises an external device connected to the plurality of processing units via a bus, wherein the external device is provided with a memory medium;

[0109] The external device is configured as:

[0110] Receive and parse a shared memory configuration instruction to obtain configuration information of the shared memory, and determine address information of the shared memory according to the configuration information of the shared memory;

[0111] According to the address range of the shared memory, part of the memory area in the device is configured as the shared memory of the plurality of processing units.

[0112] In an exemplary embodiment of the present disclosure, the external device includes a CXL module that communicates with the multiple processing units through a CXL interface, and the CXL module includes a controller and a group of memory chips connected to the controller; the processing system also includes: an internetwork manager configured to send the shared memory configuration instruction to the CXL module through the CXL interface.

[0113] In an exemplary embodiment of the present disclosure, the internetwork manager is further configured to send the configuration information of the shared memory to the plurality of processing units respectively; wherein the configuration information of the shared memory includes the size of the shared memory, and the configuration information of the consistent cache area includes the size of the consistent cache area.

[0114] In an exemplary embodiment of the present disclosure,

[0115] The processing system also includes a server and a central control hardware unit for a plurality of the processing units;

[0116] The internetwork manager is further configured to send configuration information of the shared memory to the server;

[0117] The server is configured to send the configuration information of the shared memory to the plurality of processing units respectively; and determine the configuration information of the coherent cache areas in the plurality of processing units in combination with the configuration information of the shared memory, and carry the configuration information of the plurality of coherent cache areas in a plurality of cache area configuration instructions respectively, and send them to the plurality of processing units respectively through the central control hardware unit;

[0118] The configuration information of the shared memory includes the size of the shared memory, and the configuration information of the consistent cache area includes the size of the consistent cache area.

[0119] The above-mentioned Internet network manager, server and central control hardware unit can be physically integrated together or set up separately.

[0120] In an exemplary embodiment of the present disclosure, the processing unit is further configured to: establish a first address mapping relationship between the shared memory and the coherent cache area according to an address range of the shared memory and an address range of the coherent cache area.

[0121] In an exemplary embodiment of the present disclosure, the coherent cache region is divided into a plurality of cache groups, each cache group including a plurality of cache lines;

[0122] The address used by the processing unit to access the data in the shared memory includes the following fields: Tag meta 、Tag data and Offset; or include the following fields: Tag meta 、Index meta 、Tag data and Offset; where:

[0123] Tags meta is a field used to identify the consistency cache area;

[0124] Index meta A field for identifying a cache group in the coherent cache area;

[0125] Tags data A field for identifying a cache line of a cache group in the coherent cache region;

[0126] Offset is a field used to identify data offset.

[0127] In an exemplary embodiment of the present disclosure, the system is configured with multiple shared memories, and the memory media to which different shared memories belong have different characteristics; the multiple cache groups divided by the consistent cache area correspond one-to-one to the multiple shared memories; wherein the characteristics of the memory media include any one or more of latency and bandwidth.

[0128] In an exemplary embodiment of the present disclosure, the method further includes: when the processing unit searches for data in the shared cache area in the cache, first searching for data in the shared cache area according to the tag in the address. meta、 Index meta Determine the cache group in the consistent cache area, and then according to the tag in the address data A cache line that caches the data is searched in the determined cache group.

[0129] In an exemplary embodiment of the present disclosure,

[0130] Tags meta It has multiple values, one of which indicates that the cache area of ​​the data is the consistent cache area; Index meta An index representing a cache group in the coherent cache region;

[0131] The processing unit receives the tag in the address meta、 Index metaDetermine the cache group in the consistent cache area, and then according to the tag in the address data Searching for a cache line that caches the data in the determined cache group includes:

[0132] According to the Tag in the address meta The value of the tag is used to search the metadata table of the consistent cache area. Each record in the metadata table includes the following fields: meta and cache group offset; where Tag meta The value of indicates that the cache area of ​​the data is the coherent cache area, and the value of the cache group offset indicates the position offset of the cache group in the record in the coherent cache area;

[0133] According to the Index in the address meta The value of the address is used to find the corresponding record in the metadata table, and then the search range in the consistent cache area is determined according to the cache group offset in the corresponding record; and according to the tag in the address data The corresponding cache line is searched in the search range to determine whether the cache is hit.

[0134] An embodiment of the present disclosure further provides a processor chip, including a processor and a cache. Figure 1 , the processor is configured to execute the method for reducing bus load executed by the processor as described in any embodiment of the present disclosure.

[0135] An embodiment of the present disclosure further provides a non-transitory computer storage medium storing a computer program. When the computer program is executed by a processor, the method for reducing bus load or the shared memory configuration method described in any embodiment of the present disclosure can be implemented.

[0136] An embodiment of the present disclosure also provides a CXL module, which can be found at Figure 1 The CXL module includes a CXL controller (the example in the figure is a control chip) and a memory medium connected to the CXL controller (the example in the figure is a DRAM particle). The CXL controller is configured to perform the following processing:

[0137] Receive and parse a shared memory configuration instruction to obtain configuration information of the shared memory; wherein the shared memory is a memory area shared by multiple processing units connected to the CXL module;

[0138] Determining an address range of the shared memory according to the configuration information of the shared memory;

[0139] According to the address range of the shared memory, part of the memory area in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

[0140] In an exemplary embodiment of the present disclosure, the controller receives a shared memory configuration instruction, comprising: the controller receives a shared memory configuration instruction issued by an internetwork manager in the system through a configuration interface of the shared memory. The internetwork manager refers to an entity in the system including the CXL device that can be used to configure and manage the CXL device.

[0141] An embodiment of the present disclosure further provides a shared memory configuration method, which is applied to a CXL module, wherein the CXL module includes a CXL controller and a memory medium connected to the CXL controller, and the method includes:

[0142] Step 210, receiving and parsing a shared memory configuration instruction to obtain configuration information of the shared memory; wherein the shared memory is a memory area shared by multiple processing units connected to the CXL module;

[0143] Step 220, determining the address range of the shared memory according to the configuration information of the shared memory;

[0144] Step 230: According to the address range of the shared memory, a part of the memory area in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

[0145] In this embodiment, when the host sends a memory read or write request, the metadata table of the device shared memory can be used. If the request sent by the host contains an address within the address range of the shared memory, consistency maintenance is performed; otherwise, if it falls within the address range of the non-shared memory, consistency maintenance is not required. The consistency maintenance of shared memory can be implemented in the following two ways: first, through hardware maintenance (HDM-DB) on the device side, multiple hosts first apply for the control (ownership) of the cacheline, and then start access; second, the device exposes the content in the form of HDM-H, which is maintained by the host, such as the central processing unit handling the control (ownership) of the cacheline between multiple hosts.

[0146] The above-mentioned embodiment of the present disclosure expands the CXL protocol and adds an interface for shared memory configuration. The CXL module parses the shared memory configuration instructions defined by the interface to obtain the configuration information of the shared memory; then determines the address range of the shared memory based on the configuration information of the shared memory, thereby configuring part of the memory area in the memory medium as the shared memory, and only performs cache consistency maintenance on the data in the shared memory. That is, the size of the shared memory in the CXL module can be limited by configuration, and the CXL module only performs cache consistency maintenance on the data in the shared memory. The embodiment of the present disclosure limits the size of the shared memory in the CXL module to a set range by configuration, which can prevent the operation of maintaining cache consistency from being too frequent, resulting in the problem of excessive bus load.

[0147] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A CXL module, characterized in that: The CXL module includes a CXL controller and a memory medium connected to the CXL controller, and the CXL controller is configured to perform the following processing: Receive and parse a shared memory configuration instruction to obtain configuration information of the shared memory; wherein the shared memory is a memory area shared by multiple processing units connected to the CXL module, and the configuration information of the shared memory includes the size of the shared memory; Determining an address range of the shared memory according to the configuration information of the shared memory; According to the address range of the shared memory, part of the memory area in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

2. The CXL module according to claim 1, wherein: The controller receives a shared memory configuration instruction, including: the controller receives a shared memory configuration instruction sent by an internetwork manager in the system through a shared memory configuration interface.

3. A shared memory configuration method, applied to a CXL module, wherein the CXL module includes a CXL controller and a memory medium connected to the CXL controller, the method comprising: Receive and parse a shared memory configuration instruction to obtain configuration information of the shared memory; wherein the shared memory is a memory area shared by multiple processing units connected to the CXL module, and the configuration information of the shared memory includes the size of the shared memory; Determining an address range of the shared memory according to the configuration information of the shared memory; According to the address range of the shared memory, part of the memory area in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

4. A processing system, comprising a bus and a plurality of processing units, wherein the plurality of processing units are connected via the bus, characterized in that: The processing units are all provided with a cache and a configuration interface having cache consistency, and the processing units are configured as follows: Acquire configuration information of a consistent cache area through the configuration interface of the cache consistency, and determine the address range of the consistent cache area according to the configuration information of the consistent cache area; wherein the configuration information of the consistent cache area includes the size of the consistent cache area; According to the address range of the consistent cache area, a partial area of ​​the cache of this processing unit is configured as a consistent cache area, so as to use the consistent cache area to cache data in the shared memory of multiple processing units, wherein the shared memory is a memory area shared by multiple processing units connected to the CXL module.

5. The processing system according to claim 4, characterized in that: The processing unit is a processor or a processor core; the cache capacity of at least one of the processing units is greater than or equal to 128M or 256M.

6. The processing system according to claim 4, characterized in that: The processing system further comprises: a central control hardware unit configured to issue a cache region configuration instruction to the processing unit, carrying configuration information of the coherent cache region; The processing unit obtains configuration information of the consistent cache area through the cache consistency configuration interface, including: receiving a cache area configuration instruction issued by the central control hardware unit, parsing the cache area configuration instruction, and obtaining the configuration information of the consistent cache area; The sizes of the coherent cache areas configured for different processing units are the same or different.

7. The processing system according to claim 4, characterized in that: The processing unit obtains the configuration information of the consistent cache area through the cache consistency configuration interface, including: the processing unit obtains the configuration information of the consistent cache area based on a programming interface provided by system software.

8. The processing system according to claim 4, characterized in that: The system further comprises an external device connected to the plurality of processing units via a bus, wherein the external device is provided with a memory medium; The external device is configured as: Receive and parse a shared memory configuration instruction to obtain configuration information of the shared memory, and determine address information of the shared memory according to the configuration information of the shared memory; According to the address range of the shared memory, part of the memory area in the device is configured as the shared memory of the plurality of processing units.

9. The processing system according to claim 8, characterized in that: The external device includes a CXL module that communicates with the plurality of processing units via a CXL interface, the CXL module including a controller and a group of memory chips connected to the controller; The processing system further includes: an internetwork manager configured to send the shared memory configuration instruction to the CXL module via a CXL interface.

10. The processing system according to claim 9, characterized in that: The internetwork manager is further configured to send the configuration information of the shared memory to the plurality of processing units respectively; wherein the configuration information of the shared memory includes the size of the shared memory.

11. The processing system according to claim 9, characterized in that: The processing system also includes a server and a central control hardware unit for a plurality of the processing units; The internetwork manager is further configured to send configuration information of the shared memory to the server; The server is configured to send the configuration information of the shared memory to the plurality of processing units respectively; and determine the configuration information of the coherent cache areas in the plurality of processing units in combination with the configuration information of the shared memory, and carry the configuration information of the plurality of coherent cache areas in a plurality of cache area configuration instructions respectively, and send them to the plurality of processing units respectively through the central control hardware unit; The configuration information of the shared memory includes the size of the shared memory.

12. The processing system of claim 8, wherein: The processing unit is further configured to establish a first address mapping relationship between the shared memory and the coherent cache area according to an address range of the shared memory and an address range of the coherent cache area.

13. The processing system of claim 4, wherein: The coherent cache area is divided into a plurality of cache groups, each cache group including a plurality of cache lines; The address used by the processing unit to access the data in the shared memory includes the following fields: Tag meta 、Tag data and Offset; or Includes the following fields: Tag meta 、Index meta 、Tag data and Offset; where: Tags meta is a field used to identify the consistency cache area; Index meta A field for identifying a cache group in the coherent cache area; Tags data A field for identifying a cache line of a cache group in the coherent cache region; Offset is a field used to identify data offset.

14. The processing system of claim 13, wherein: The system is configured with multiple shared memories, and the memory media to which different shared memories belong have different characteristics; The multiple cache groups divided by the consistent cache area correspond one-to-one to the multiple shared memories; wherein the characteristics of the memory medium include any one or more of latency and bandwidth.

15. A method for reducing bus load, applied to a system including a plurality of processing units, wherein the plurality of processing units are connected via a bus, and the plurality of processing units are all provided with a cache and a configuration interface having cache consistency, the method comprising: The processing unit obtains configuration information of the consistent cache area through the configuration interface of the cache consistency, and determines the address range of the consistent cache area according to the configuration information of the consistent cache area; wherein the configuration information of the consistent cache area includes the size of the consistent cache area; The processing unit configures a partial area of ​​the cache of the processing unit as a consistent cache area according to the address range of the consistent cache area, so as to use the consistent cache area to cache data in the shared memory of multiple processing units, wherein the shared memory is a memory area shared by multiple processing units connected to the CXL module.

16. The method of claim 15, wherein: The processing unit is a processor or a processor core; The cache capacity of at least one of the processing units is greater than or equal to 128M or 256M.

17. The method of claim 15, wherein: The processing unit obtains the configuration information of the consistent cache area through the configuration interface of the cache consistency, including: the processing unit receives the cache area configuration instruction issued by the central control hardware unit of the system, parses the cache area configuration instruction, and obtains the configuration information of the consistent cache area; or, the processing unit obtains the configuration information of the consistent cache area based on the programming interface provided by the system software; The sizes of the coherent cache areas configured for different processing units are the same or different.

18. The method of claim 15, wherein: The system further includes an external device connected to the plurality of processing units via a bus, wherein the external device is provided with a memory medium; and the method further includes: The external device receives and parses the shared memory configuration instruction to obtain the configuration information of the shared memory, and determines the address information of the shared memory according to the configuration information of the shared memory; The external device configures part of the memory area in the device as the shared memory of the multiple processing units according to the address range of the shared memory.

19. The method of claim 18, wherein: The external device includes a CXL module that communicates with the plurality of processing units via a CXL interface, the CXL module including a controller and a group of memory chips connected to the controller; The shared memory configuration instruction is sent by the Internet network manager of the system to the CXL module through the CXL interface.

20. The method of claim 19, wherein: The internetwork manager further sends the configuration information of the shared memory to the plurality of processing units respectively; or The internetwork manager also sends the configuration information of the shared memory to the servers of the plurality of processing units, and the servers send the configuration information of the shared memory to the plurality of processing units respectively; And, the server further determines configuration information of the coherent cache areas in the plurality of processing units in combination with the configuration information of the shared memory, carries the configuration information of the plurality of coherent cache areas in a plurality of cache area configuration instructions respectively, and issues them to the plurality of processing units respectively through the central control hardware unit of the system; The configuration information of the shared memory includes the size of the shared memory.

21. The method of claim 18, wherein: The method further includes: the processing unit establishing a first address mapping relationship between the shared memory and the coherent cache area according to the address range of the shared memory and the address range of the coherent cache area.

22. The method of claim 15, wherein: The consistent cache area is divided into a plurality of cache groups, each of which includes a plurality of cache lines; the address used by the processing unit when accessing the data in the shared memory includes the following fields: Tag meta 、Tag data and Offset; or Includes the following fields: Tag meta 、Index meta 、Tag data and Offset; where: Tags meta is a field used to identify the consistency cache area; Index meta A field for identifying a cache group in the coherent cache area; Tags data A field for identifying a cache line of a cache group in the coherent cache region; Offset is a field used to identify data offset.

23. The method of claim 22, wherein: The system is configured with multiple shared memories, and the memory media belonging to different shared memories have different characteristics; the multiple cache groups divided by the consistent cache area correspond one-to-one to the multiple shared memories; wherein the characteristics of the memory medium include any one or more of latency and bandwidth.

24. The method of claim 22, wherein: The method further includes: when the processing unit searches for data in the shared cache area in the cache, first searching for data in the shared cache area according to the tag in the address meta、 Index meta Determine the cache group in the consistent cache area, and then according to the tag in the address data A cache line that caches the data is searched in the determined cache group.

25. The method of claim 24, wherein: Tags meta has multiple values, one of which indicates that the cache area of ​​the data is the coherent cache area; Index meta An index representing a cache group in the coherent cache region; The processing unit receives the tag in the address meta、 Index meta Determine the cache group in the consistent cache area, and then according to the tag in the address data Searching for a cache line that caches the data in the determined cache group includes: According to the Tag in the address meta The value of the metadata table of the consistent cache area is searched, and each record in the metadata table includes the following fields: Tag meta and cache group offset; where Tag meta The value of indicates that the cache area of ​​the data is the coherent cache area, and the value of the cache group offset indicates the position offset of the cache group in the record in the coherent cache area; According to the Index in the address meta The value of the address is used to find the corresponding record in the metadata table, and then the search range in the consistent cache area is determined according to the cache group offset in the corresponding record; and according to the tag in the address data The corresponding cache line is searched in the search range to determine whether the cache is hit.

26. A processor chip, characterized in that: The method comprises a processor core and a cache, wherein the processor core is configured to execute the method according to any one of claims 15 to 17 and 21 to 25.

27. A non-transitory computer storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 15 to 25 can be implemented.

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