A reconfigurable multi-logic sensitive amplifier for SRAM storage and calculation and its control method

Abstract

The invention discloses a reconfigurable multi-logic sense amplifier for SRAM storage and calculation and a control method thereof, belonging to the technical field of sense amplifiers. The sense amplifier comprises: a BL signal selection circuit connected to a BL bit line, the BL signal selection circuit comprising a read enable signal input terminal, a read output terminal and a calculation output terminal; when the sense amplifier main circuit is connected to the read output terminal, a symmetrical differential sense amplifier is formed to read the stored data; when the sense amplifier main circuit is connected to the calculation output terminal, an asymmetrical differential sense amplifier is formed to perform an OR / NOT logic operation on the stored data and output it; a logic generation circuit is connected to the sense amplifier main circuit, to perform an AND / XOR logic operation on the stored data and output it, thereby realizing the reconstruction of the amplifier structure and the multi-logic operation on the bit line signal, supporting high-speed calculation access and normal read access, and improving the sensing speed and the applicability of the amplifier.

Description

Technical Field

[0001] The invention belongs to the technical field of sensitive amplifiers, and in particular relates to a reconfigurable multi-logic sensitive amplifier for SRAM storage and calculation and a control method thereof. Background Art

[0002] In the existing SRAM-based in-memory computing structure, the sense amplifier is an important circuit, and its main function is to amplify and output the differential data of the bit line pair. Usually, in order to maintain the storage density of the storage array, a pair of differential bit line pairs will carry a large number of storage cells, up to 64 or 128, and some even up to 256, resulting in a load capacitance of the bit line of tens of femtofarads (f F) or even hundreds of femtofarads. However, the read current of SRAM is relatively small. If ordinary logic circuits are used, it is difficult to achieve rail-to-rail output of bit line data in a short time, but the sense amplifier can effectively solve this problem.

[0003] Computational SRAM requires high speed for both computational access and normal read access. However, it exhibits very different bitline discharge behaviors in these two modes, which poses a major challenge to the design of its sense amplifier. The most advanced sense amplifiers, namely symmetrical single-ended sense amplifiers (SS-SA) and asymmetrical differential sense amplifiers (AD-SA), cannot support high-speed computational access and normal read access at the same time. In addition, some traditional sense amplifiers can only implement a single logic operation in the in-memory computation structure, with simple functions and poor applicability. Summary of the invention

[0004] The present invention provides a reconfigurable multi-logic sensitive amplifier for SRAM storage and calculation and a control method thereof. The amplifier structure can be reconfigured through a BL selection circuit, high-speed calculation access and normal read access are supported, different circuit structures are selected for different modes, the sensing speed is improved, and multi-logic operations are realized through a logic generation circuit, thereby improving the applicability of the amplifier.

[0005] To achieve the above object, the present invention is implemented by adopting the following technical solutions.

[0006] In a first aspect, the present invention provides a reconfigurable multi-logic sense amplifier for SRAM storage and calculation, comprising: a BL signal selection circuit, a sense amplifier main circuit, and a logic generation circuit;

[0007] The BL signal selection circuit is connected to the BL bit line and is used to access the BL bit line signal. The BL signal selection circuit includes a read enable signal input terminal, a read output terminal and a calculation output terminal. The read enable signal input terminal is used to input the read enable signal; the read output terminal and the calculation output terminal are respectively connected to the sense amplifier main circuit and are respectively used to control the sense amplifier main circuit to read or calculate the stored data;

[0008] When the SRAM is read, the main circuit of the sense amplifier is connected to the read output end of the BL signal selection circuit to form a symmetrical differential sense amplifier to read the stored data; when the SRAM is calculated, the main circuit of the sense amplifier is connected to the calculation output end of the BL signal selection circuit to form an asymmetrical differential sense amplifier to perform a logical operation of OR / OR on the stored data and output it;

[0009] The logic generation circuit is connected to the main circuit of the sense amplifier, and is used to perform AND / XOR logic operations on the stored data and output the data when performing calculation access to the SRAM.

[0010] Optionally, the BL signal selection circuit includes a fourth NMOS transistor N4 and a seventh PMOS transistor P7;

[0011] The drain of the fourth NMOS tube N4 and the source of the seventh PMOS tube P7 are respectively connected to the BL bit line, the source of the fourth NMOS tube N4 and the drain of the seventh PMOS tube P7 are respectively used as a read output terminal and a calculation output terminal, and are respectively connected to the main circuit of the sensitive amplifier, and the gates of the two are respectively connected to the read enable signal as read enable signal input terminals.

[0012] Optionally, the sense amplifier main circuit includes a precharge unit, a bit line signal latch unit, a bit line signal transmission unit and a sense amplifier enable unit;

[0013] The pre-charging unit is used to pre-charge the bit line signal latch unit;

[0014] The bit line signal transmission unit is used to transmit the bit line signal to the bit line signal latch unit;

[0015] The bit line signal latch unit is used to latch the bit line signal;

[0016] The sense amplifier enabling unit is connected to the bit line signal transmission unit and is used to control the switch of the sense amplifier.

[0017] Optionally, the sense amplifier enabling unit includes a seventh NMOS transistor N7;

[0018] The source of the seventh NMOS transistor N7 is grounded, the gate is connected to the sense amplifier enable signal, and the drain is connected to the bit line signal transmission unit.

[0019] Optionally, the bit line signal transmission unit includes a third NMOS tube N3, a fifth NMOS tube N5 and a sixth NMOS tube N6, and the fifth NMOS tube N5 is a low threshold MOS tube;

[0020] The sources of the third NMOS tube N3, the fifth NMOS tube N5 and the sixth NMOS tube N6 are respectively connected to the drain of the seventh NMOS tube N7;

[0021] The drains of the third NMOS transistor N3, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are respectively connected to the bit line signal latch unit;

[0022] The gate of the third NMOS transistor N3 is connected to the source of the fourth NMOS transistor N4 , the gate of the fifth NMOS transistor N5 is connected to the seventh PMOS transistor P7 , and the gate of the sixth NMOS transistor N6 is connected to the BLB bit line.

[0023] Optionally, the bit line signal latch unit includes a first inverter and a second inverter cross-coupled with a pair of transmission tubes;

[0024] The first inverter includes a third PMOS transistor P3 and a first NMOS transistor N1, and the second inverter includes a fourth PMOS transistor P4 and a second NMOS transistor N2;

[0025] The drains of the third PMOS transistor P3 and the first NMOS transistor N1 are connected to the gates of the fourth PMOS transistor P4 and the second NMOS transistor N2, and the connection point is a node P, which is used to latch the BL bit line information and output the result of the logical OR operation on the stored data;

[0026] The drains of the fourth PMOS transistor P4 and the second NMOS transistor N2 are connected to the gates of the third PMOS transistor P3 and the first NMOS transistor N1, and the connection point is a node OUT1, and the node OUT1 is used to latch the BLB bit line information and output the result of the logic OR operation on the stored data;

[0027] The sources of the third PMOS tube P3 and the fourth PMOS tube P4 are connected to the working voltage, the source of the first NMOS tube N1 is connected to the drain of the third NMOS tube N3 and the drain of the fifth NMOS tube N5 respectively, and the source of the second NMOS tube N2 is connected to the drain of the sixth NMOS tube N6.

[0028] Optionally, the pre-charging unit includes a first PMOS tube P1 and a second PMOS tube P2;

[0029] The gates of the first PMOS transistor P1 and the second PMOS transistor P2 are respectively connected to the precharge signal, the sources are respectively connected to the working voltage, the drain of the first PMOS transistor P1 is connected to the node P, and the drain of the second PMOS transistor P2 is connected to the node OUT1.

[0030] Optionally, the logic generation circuit includes a fifth PMOS tube P5, a sixth PMOS tube P6, an eighth NMOS tube N8 and a ninth NMOS tube N9;

[0031] The fifth PMOS transistor P5, the eighth NMOS transistor N8 and the ninth NMOS transistor N9 are connected in series between the working voltage and the ground line, the gates of the fifth PMOS transistor P5 and the eighth NMOS transistor N8 are respectively connected to the BLB bit line, and the gate of the ninth NMOS transistor N9 is connected to the node OUT1;

[0032] The source of the sixth PMOS transistor P6 is connected to the working voltage, the gate of the sixth PMOS transistor P6 is connected to the node OUT1, the drain of the sixth PMOS transistor P6 is the output node OUT2, and the node OUT2 outputs the result of performing a logical XOR operation on the stored data;

[0033] The drain of the sixth PMOS transistor P6 is connected to the drain of the fifth PMOS transistor P5 and the drain of the eighth NMOS transistor N8 , and the connection point of the three is an output node Q, and the node Q outputs the result of the logic and operation on the stored data.

[0034] In a second aspect, the present invention provides a control method, which is applied to the reconfigurable multi-logic sense amplifier for SRAM storage and calculation described in the first aspect, comprising:

[0035] The precharge signal is set to a low level, so that the node P and the node OUT1 are precharged to 1, and then the read enable signal is set to a high level, so that the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 form a symmetrical differential sensitive amplifier, and the stored data is read out through the node P and the node OUT1;

[0036] And / or, the precharge signal is set to a low level, so that the node P and the node OUT1 are precharged to 1, and then the read enable signal is set to a low level, so that the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the first NMOS tube N1, the second NMOS tube N2, the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7 form an asymmetric differential sensitive amplifier, and the logical or non-true value of the stored data is calculated through the node P, the logical or true value of the stored data is calculated through the node OUT1, the logical and true value of the stored data is calculated through the node Q, and the logical exclusive or true value of the stored data is calculated through the node OUT2.

[0037] Compared with the prior art, the present invention has the following beneficial effects: the selectivity of the BL bit line signal input to the main circuit of the sense amplifier is realized through the BL signal selection circuit, so that the main circuit of the sense amplifier can be reconstructed into a symmetrical differential sense amplifier for read access, and an asymmetrical differential sense amplifier for calculation access. Different structures are selected for different applicable scenarios to improve the overall sensing speed. In addition, the present invention increases the logic generation circuit and uses fewer transistors to enable the sense amplifier to realize multiple logic operations in the calculation mode, thereby improving the applicability of the sense amplifier. Compared with traditional sensing methods, the delay time and power consumption of the sensing design are greatly reduced in multiple logic operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 FIG. 1 is a connection diagram of a reconfigurable multi-logic sense amplifier in an embodiment of the present invention.

[0039] In the figure: 1. BL signal selection circuit; 2. Sensitive amplifier main circuit; 3. Logic generation circuit. DETAILED DESCRIPTION

[0040] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0041] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", and the like may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0043] Example 1

[0044] like Figure 1 As shown, this embodiment provides a reconfigurable multi-logic sense amplifier for SRAM storage and calculation, including: a BL signal selection circuit 1, a sense amplifier main circuit 2 and a logic generation circuit 3;

[0045] The BL signal selection circuit 1 has a BL bit line signal input terminal, an enable signal input terminal, a read output terminal and a calculation output terminal, wherein the BL bit line signal input terminal is connected to the BL bit line and is used to input a BL bit line signal, the enable signal input terminal is used to input a sense amplifier enable signal, the read output terminal is used to output a read access signal, and the calculation output terminal is used to output a calculation access signal, and the read output terminal and the calculation output terminal cannot output signals at the same time;

[0046] The sense amplifier main circuit 2 is respectively connected to the read output terminal and the calculation output terminal of the BL signal selection circuit 1, and is used to receive a read access signal and form a symmetrical differential sense amplifier to read the stored data, and is used to receive a calculation access signal and form an asymmetrical differential sense amplifier to perform a non-OR logic operation on the stored data;

[0047] The logic generation circuit 3 is connected to the sense amplifier main circuit 2. When the sense amplifier main circuit 2 is connected to the calculation output terminal, the logic generation circuit 3 is used to perform AND / XOR logic operations on the stored data.

[0048] By connecting the BL selection circuit to the input end of the sense amplifier main circuit 2, the SRAM can realize two different working modes, namely, reading and calculating. Combined with the design of the logic generation circuit 3, the SRAM can realize a variety of logical operations, greatly improving the applicability of the SRAM storage and calculation unit.

[0049] Example 2

[0050] Based on Example 1, this example also makes the following design.

[0051] The BL signal selection circuit 1 includes a fourth NMOS tube N4 and a seventh PMOS tube P7. The BL signal selection circuit 1 inputs a BL bit line signal to the drain of the fourth NMOS tube N4 and the source of the seventh PMOS tube P7, respectively, and inputs a read enable signal REN through the gates of the fourth NMOS tube N4 and the seventh PMOS tube P7. The source of the fourth NMOS tube N4 and the drain of the seventh PMOS tube P7 are respectively connected to the sense amplifier main circuit 2.

[0052] The sense amplifier main circuit 2 includes a sense amplifier enabling unit, a bit line signal receiving unit, a bit line signal latching unit and a pre-charging unit.

[0053] The sense amplifier enabling unit comprises a seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7 is connected to the sense amplifier enabling signal SAE-Com as the sense amplifier enabling signal input terminal, the source of the seventh NMOS transistor N7 is grounded, and the drain is connected to the bit line signal receiving unit.

[0054] The bit line signal receiving unit includes a BL bit line signal input terminal and a BLB bit line signal input terminal. The BL bit line signal input terminal includes a third NMOS tube N3 and a fifth NMOS tube N5, wherein the fifth NMOS tube N5 is a low threshold MOS tube, the gate of the third NMOS tube N3 is connected to the source of the fourth NMOS tube N4, the gate of the fifth NMOS tube N5 is connected to the drain of the seventh PMOS tube P7, and the BL bit line signal selected by the BL signal selection circuit 1 is input to the sense amplifier main circuit 2, the sources of the third NMOS tube N3 and the fifth NMOS tube N5 are respectively connected to the drain of the seventh NMOS tube N7, and the drains of the two are respectively connected to the bit line signal latch unit; the BLB bit line signal input terminal includes a sixth NMOS tube N6, the gate of the sixth NMOS tube N6 is connected to the BLB bit line, the BLB bit line signal is input to the sense amplifier main circuit 2, the source of the sixth NMOS tube N6 is connected to the drain of the seventh NMOS tube N7, and the drain of the sixth NMOS tube N6 is connected to the bit line signal latch unit.

[0055] The bit line signal latch unit includes a third PMOS tube P3, a fourth PMOS tube P4, a first NMOS tube N1 and a second NMOS tube N2. The sources of the third PMOS tube P3 and the fourth PMOS tube P4 are respectively connected to the working voltage, the sources of the first NMOS tube N1 and the second NMOS tube N2 are respectively connected to the drains of the fifth NMOS tube N5 and the sixth NMOS tube N6, the drains of the third PMOS tube P3 and the first NMOS tube N1 are connected to the gates of the fourth PMOS tube P4 and the second NMOS tube N2, and the connection point of the four is a node P, which is used to latch the BL bit line information and output the OR logic operation result of the stored data, the drains of the fourth PMOS tube P4 and the second NMOS tube N2 are connected to the gates of the third PMOS tube P3 and the first NMOS tube N1, and the connection point of the four is a node OUT1, which is used to latch the BLB bit line information and output the OR logic operation result of the stored data.

[0056] The pre-charge unit includes a first PMOS tube P1, a second PMOS tube P2 and the pre-charge signal input end, the gates of the first PMOS tube P1 and the second PMOS tube P2 are both connected to the pre-charge signal input end, the pre-charge signal input end receives the pre-charge signal Enable, the sources of the first PMOS tube P1 and the second PMOS tube P2 are both connected to the working voltage, and the drains of the first PMOS tube P1 and the second PMOS tube P2 are respectively connected to the node P and the node OUT1.

[0057] The logic generation circuit 3 includes a fifth PMOS tube P5, a sixth PMOS tube P6, an eighth NMOS tube N8 and a ninth NMOS tube N9. The sources of the fifth PMOS tube P5 and the sixth PMOS tube P6 are connected to the working voltage, the gate of the sixth PMOS tube P6 is connected to the node OUT1, the drain of the fifth PMOS tube P5 and the drain of the eighth NMOS tube N8 are connected to the drain of the sixth PMOS tube P6, and the connection point of the three is a node Q for outputting an AND logic operation result of the stored data. The drain of the sixth PMOS tube P6 is a node OUT2 for outputting an XENO logic operation result of the stored data. The gates of the fifth PMOS tube P5 and the eighth NMOS tube N8 are connected to the BLB bit line, the source of the eighth NMOS tube N8 is connected to the drain of the ninth NMOS tube N9, the gate of the ninth NMOS tube N9 is connected to the node OUT1, and the source is grounded.

[0058] In this embodiment, the working principle of the sense amplifier is as follows.

[0059] Read mode: When the Enable signal is set to a high level, the node P and the node OUT1 are precharged to 1, and the read enable signal REN is set to 1, then the fourth NMOS tube N4 is turned on, and the seventh PMOS tube P7 and the fifth NMOS tube N5 are turned off. At this time, the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3, the sixth NMOS tube N6 and the seventh NMOS tube N7 form a symmetrical differential sense amplifier SDSA.

[0060] The word line WL connected to the bit line BL and the bit line BLB is set to a high level, the third NMOS tube N3 and the sixth NMOS tube N6 are turned on, a voltage difference appears between the bit line BL and the bit line BLB, the sense amplifier enable signal SAE-Com is turned on, and the symmetrical differential sense amplifier SDSA starts to work. The voltage difference between the bit line BL and the bit line BLB makes the V GS Different, and thus make the current passing through the third NMOS tube N3 and the sixth NMOS tube N6 different, so that there is a current difference between the current path N1-N3 and the current path N2-N6, the current difference makes the discharge speed of the node P and the node OUT1 different, and a voltage difference is formed between the node P and the node OUT1, and the voltage difference is amplified through the positive feedback loop composed of the first NMOS tube N1, the second NMOS tube N2, the third PMOS tube P3 and the fourth PMOS tube P4, so as to realize the output of the differential voltage rail-to-rail, so as to quickly read the stored data.

[0061] Calculation mode: When the Enable signal is set to a high level, the P point and OUT1 are precharged to 1, and the read enable signal REN is set to 0, then the seventh PMOS tube P7 is turned on, and the fourth NMOS tube N4 and the third NMOS tube N3 are turned off. At this time, the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the first NMOS tube N1, the second NMOS tube N2, the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7 form an asymmetric differential sense amplifier ADSA.

[0062] When the storage data in the storage node A / B in the SRAM is 0 / 0, the potential of the bit line BL is low, the potential of the bit line BLB remains at VDD, and the asymmetric differential sense amplifier ADSA pulls the potential of the node OUT1 to logic 0, the potential of the node P is logic 1, and the potential of the node Q is logic 0, and the potential of the node OUT2 is logic 1.

[0063] When the storage data in the storage node A / B in the SRAM is 0 / 1, the bit line BL and the bit line BLB have the same potential. Since the fifth NMOS tube N5 has a strong driving strength, the asymmetric differential sense amplifier ADSA pulls the node P potential to logic 0, and the node OUT1 potential is logic 0. At this time, the node Q potential is logic 0, and the node OUT2 potential is logic 0.

[0064] When the storage data in the storage node A / B in the SRAM is 1 / 0, the bit line BL and the bit line BLB have the same potential. Since the fifth NMOS tube N5 has a strong driving strength, the asymmetric differential sense amplifier ADSA pulls the node P potential to logic 0, and the node OUT1 potential is logic 0. At this time, the node Q potential is logic 0, and the node OUT2 potential is logic 0.

[0065] When the storage data in the storage node A / B in the SRAM is 1 / 1, the potential of the bit line BLB is low, the potential of the bit line BL remains at VDD, the asymmetric differential sense amplifier ADSA pulls the potential of the node P to logic 0, the potential of the node OUT1 is logic 1, at this time the potential of the node Q is logic 1, and the potential of the node OUT2 is logic 1.

[0066] The following table shows the logic operation truth table of each node under different cases of BL and BLB potential combinations:

[0067] Table 1

[0068] A B P(NOR) OUT1(OR) Q(AND) OUT2(XNOR) 0 0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1

[0069] Example 3

[0070] This embodiment provides a control method, which is applied to a reconfigurable multi-logic sense amplifier for SRAM storage and calculation described in Embodiment 2, including:

[0071] The precharge signal Enable is set to a low level, so that the node P and the node OUT1 are precharged to 1, and then the read enable signal REN is set to a high level, so that the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 form a symmetrical differential sensitive amplifier, and the stored data is read out through the node P and the node OUT1;

[0072] And / or, the precharge signal Enable is set to a low level, so that the node P and the node OUT1 are precharged to 1, and then the read enable signal REN is set to a low level, so that the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the first NMOS tube N1, the second NMOS tube N2, the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7 form an asymmetric differential sensitive amplifier, and the logical or non-true value of the stored data is calculated through the node P, the logical or true value of the stored data is calculated through the node OUT1, the logical and true value of the stored data is calculated through the node Q, and the logical exclusive or true value of the stored data is calculated through the node OUT2.

[0073] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A reconfigurable multi-logic sense amplifier for SRAM storage and calculation, characterized in that: include: BL signal selection circuit (1), sense amplifier main circuit (2) and logic generation circuit (3); The BL signal selection circuit (1) is connected to the BL bit line and is used to receive the BL bit line signal. The BL signal selection circuit (1) comprises a read enable signal input terminal, a read output terminal and a calculation output terminal. The read enable signal input terminal is used to input the read enable signal. The read output terminal and the calculation output terminal are respectively connected to the sense amplifier main circuit (2) and are respectively used to control the sense amplifier main circuit (2) to read or calculate the stored data. When the SRAM is read, the sense amplifier main circuit (2) is connected to the read output end of the BL signal selection circuit (1) to form a symmetrical differential sense amplifier to read the stored data; when the SRAM is calculated, the sense amplifier main circuit (2) is connected to the calculation output end of the BL signal selection circuit (1) to form an asymmetrical differential sense amplifier to perform a non-OR logic operation on the stored data and output it; The logic generation circuit (3) is connected to the sense amplifier main circuit (2) and is used to perform AND / XOR logic operations on the stored data and output the data when performing calculation access to the SRAM.

2. The reconfigurable multi-logic sense amplifier for SRAM storage and calculation according to claim 1, characterized in that: The BL signal selection circuit (1) comprises a fourth NMOS transistor N4 and a seventh PMOS transistor P7; The drain of the fourth NMOS transistor N4 and the source of the seventh PMOS transistor P7 are respectively connected to the BL bit line; the source of the fourth NMOS transistor N4 and the drain of the seventh PMOS transistor P7 serve as a read output terminal and a calculation output terminal respectively, and are respectively connected to the sense amplifier main circuit (2); the gates of the two serve as read enable signal input terminals and are respectively connected to the read enable signal.

3. The reconfigurable multi-logic sense amplifier for SRAM storage and calculation according to claim 2, characterized in that: The sense amplifier main circuit (2) comprises a pre-charge unit, a bit line signal latch unit, a bit line signal transmission unit and a sense amplifier enabling unit; The pre-charging unit is used to pre-charge the bit line signal latch unit; The bit line signal transmission unit is used to transmit the bit line signal to the bit line signal latch unit; The bit line signal latch unit is used to latch the bit line signal; The sense amplifier enabling unit is connected to the bit line signal transmission unit and is used to control the switch of the sense amplifier.

4. The reconfigurable multi-logic sense amplifier for SRAM storage and calculation according to claim 3, characterized in that: The sense amplifier enabling unit comprises a seventh NMOS tube N7; The source of the seventh NMOS transistor N7 is grounded, the gate is connected to the sense amplifier enable signal, and the drain is connected to the bit line signal transmission unit.

5. The reconfigurable multi-logic sense amplifier for SRAM storage and calculation according to claim 4, characterized in that: The bit line signal transmission unit includes a third NMOS tube N3, a fifth NMOS tube N5 and a sixth NMOS tube N6, wherein the fifth NMOS tube N5 is a low threshold MOS tube; The sources of the third NMOS tube N3, the fifth NMOS tube N5 and the sixth NMOS tube N6 are respectively connected to the drain of the seventh NMOS tube N7; The drains of the third NMOS transistor N3, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are respectively connected to the bit line signal latch unit; The gate of the third NMOS transistor N3 is connected to the source of the fourth NMOS transistor N4 , the gate of the fifth NMOS transistor N5 is connected to the seventh PMOS transistor P7 , and the gate of the sixth NMOS transistor N6 is connected to the BLB bit line.

6. The reconfigurable multi-logic sense amplifier for SRAM storage and calculation according to claim 5, characterized in that: The bit line signal latch unit includes a first inverter and a second inverter which are cross-coupled with a pair of transmission tubes; The first inverter includes a third PMOS transistor P3 and a first NMOS transistor N1, and the second inverter includes a fourth PMOS transistor P4 and a second NMOS transistor N2; The drains of the third PMOS transistor P3 and the first NMOS transistor N1 are connected to the gates of the fourth PMOS transistor P4 and the second NMOS transistor N2, and the connection point is a node P, which is used to latch the BL bit line information and output the result of the logical OR operation on the stored data; The drains of the fourth PMOS transistor P4 and the second NMOS transistor N2 are connected to the gates of the third PMOS transistor P3 and the first NMOS transistor N1, and the connection point is a node OUT1, and the node OUT1 is used to latch the BLB bit line information and output the result of the logic OR operation on the stored data; The sources of the third PMOS tube P3 and the fourth PMOS tube P4 are connected to the working voltage, the source of the first NMOS tube N1 is connected to the drain of the third NMOS tube N3 and the drain of the fifth NMOS tube N5 respectively, and the source of the second NMOS tube N2 is connected to the drain of the sixth NMOS tube N6.

7. The reconfigurable multi-logic sense amplifier for SRAM storage and calculation according to claim 6, characterized in that: The pre-charging unit includes a first PMOS tube P1 and a second PMOS tube P2; The gates of the first PMOS transistor P1 and the second PMOS transistor P2 are respectively connected to the precharge signal, the sources are respectively connected to the working voltage, the drain of the first PMOS transistor P1 is connected to the node P, and the drain of the second PMOS transistor P2 is connected to the node OUT1.

8. The reconfigurable multi-logic sense amplifier for SRAM storage and calculation according to claim 7, characterized in that: The logic generation circuit includes a fifth PMOS tube P5, a sixth PMOS tube P6, an eighth NMOS tube N8 and a ninth NMOS tube N9; The fifth PMOS transistor P5, the eighth NMOS transistor N8 and the ninth NMOS transistor N9 are connected in series between the working voltage and the ground line, the gates of the fifth PMOS transistor P5 and the eighth NMOS transistor N8 are respectively connected to the BLB bit line, and the gate of the ninth NMOS transistor N9 is connected to the node OUT1; The source of the sixth PMOS transistor P6 is connected to the working voltage, the gate of the sixth PMOS transistor P6 is connected to the node OUT1, the drain of the sixth PMOS transistor P6 is the output node OUT2, and the node OUT2 outputs the result of performing a logical XOR operation on the stored data; The drain of the sixth PMOS transistor P6 is connected to the drain of the fifth PMOS transistor P5 and the drain of the eighth NMOS transistor N8 , and the connection point of the three is an output node Q, and the node Q outputs the result of the logic AND operation on the stored data.

9. A control method, applied to the reconfigurable multi-logic sense amplifier for SRAM storage and calculation as claimed in claim 8, characterized in that: include: The precharge signal is set to a low level, so that the node P and the node OUT1 are precharged to 1, and then the read enable signal is set to a high level, so that the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 form a symmetrical differential sensitive amplifier, and the stored data is read out through the node P and the node OUT1; And / or, the precharge signal is set to a low level, so that the node P and the node OUT1 are precharged to 1, and then the read enable signal is set to a low level, so that the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the first NMOS tube N1, the second NMOS tube N2, the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7 form an asymmetric differential sensitive amplifier, and the logical or non-true value of the stored data is calculated through the node P, the logical or true value of the stored data is calculated through the node OUT1, the logical and true value of the stored data is calculated through the node Q, and the logical exclusive or true value of the stored data is calculated through the node OUT2.

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