A packaging method and system for implementing a memory chip

Abstract

The present invention relates to the field of electronic packaging, and proposes a packaging method and system for realizing memory chips, the method comprising: first obtaining a chip to be packaged, performing an appearance inspection to select a chip with qualified appearance, then conducting an electrical performance test on the chip, classifying the chips according to the storage type to obtain a classified chip group, querying the packaging material, using a substrate to build a packaging infrastructure, installing the chip, bonding and fixing it, and sealing it to obtain a preliminary package, monitoring the packaging state after drying it, detecting potential defects and marking it to obtain a marked package, detecting performance indicators after repair, grading it to obtain a graded package, querying the grading process and generating a packaging report for the chip to be packaged, and realizing a complete process from chip detection to packaging, repair and report generation. The present invention can improve the packaging level of memory chip packaging.

Description

Technical Field

[0001] The present invention relates to the field of electronic packaging, and in particular to a packaging method and system for implementing a memory chip. Background Art

[0002] In today's science and technology field, memory chips are increasingly used in electronic devices, covering many terminal products such as computers, smart phones, and the Internet of Things. Ensuring the stable performance and reliable operation of memory chips is a key factor in improving the quality of electronic equipment. Timely and effective packaging of memory chips is of great significance to improving the storage capacity, transmission speed and stability of chips.

[0003] At present, the traditional memory chip packaging method mainly relies on manual operation and simple mechanical devices. This method not only has low production efficiency, but also makes it difficult to ensure packaging accuracy and quality. In addition, some conventional packaging processes and technologies are difficult to meet the growing demand for high performance and miniaturization. Furthermore, although some companies have adopted some automated packaging equipment, due to the continuous updating of memory chip technology, product specifications and performance requirements are becoming increasingly complex and changeable. These methods often cannot accurately adapt to the packaging requirements of new memory chips. Therefore, a packaging method and system for memory chips is needed to improve the packaging level of memory chip packaging. Summary of the invention

[0004] The present invention provides a packaging method and system for implementing a memory chip, the main purpose of which is to improve the packaging level of the memory chip.

[0005] Obtaining a chip to be packaged, performing an appearance inspection on the chip to be packaged to obtain chip appearance parameters, screening a qualified appearance chip corresponding to the chip to be packaged according to the chip appearance parameters, performing an electrical performance test on the qualified appearance chip to obtain performance test data;

[0006] Based on the performance test data, query the storage type corresponding to the chip to be packaged, classify the chip to be packaged based on the storage type to obtain a classified chipset, query the packaging material corresponding to the classified chipset, the packaging material includes: a substrate, an adhesive and a sealing material;

[0007] Using the substrate to construct a packaging basic structure corresponding to the chip to be packaged, installing the chip to be packaged in the packaging basic structure to obtain a basic packaged chip, using the adhesive to bond and fix the basic packaged chip, and using the sealing material to seal the bonded and fixed basic packaged chip to obtain a preliminary package body;

[0008] Drying the preliminary package to obtain a dried package, monitoring the package state of the dried package in real time, performing defect detection on the dried package based on the package state to obtain potential package defects, and marking the package with the potential package defect in the dried package to obtain a marked package;

[0009] The marked package is repaired to obtain a repaired package, performance indicators corresponding to the repaired package are detected, and based on the performance indicators, the repaired package is graded to obtain a graded package, a grading process corresponding to the graded package is queried, and a packaging report corresponding to the chip to be packaged is generated based on the grading process.

[0010] Optionally, performing an electrical performance test on the chip with qualified appearance to obtain performance test data includes:

[0011] Applying a preset electrical test signal to the chip with qualified appearance to obtain chip response data;

[0012] Based on the response data, calculating the electrical response value corresponding to the chip with qualified appearance;

[0013] Based on the electrical parameter values ​​and a preset electrical performance model, a performance simulation is performed on the chip with qualified appearance to obtain simulated performance data;

[0014] Analyze the difference between the simulated performance data and the preset standard performance data;

[0015] Based on the difference index, an electrical performance test is performed on the chip with qualified appearance to obtain performance test data.

[0016] Optionally, the calculating, based on the response data, an electrical response value corresponding to the chip with qualified appearance includes:

[0017] The electrical response value corresponding to the qualified chip is calculated using the following formula:

[0018]

[0019] in, Indicates the electrical response value corresponding to the qualified appearance chip, Indicates at time The current response value when Indicates at time The voltage response value when and Respectively represent the response start time and response end time corresponding to the response data, Represents the time variable " "The differential element for integration is time of small increments.

[0020] Optionally, querying the storage type corresponding to the chip to be packaged based on the performance test data includes:

[0021] Classifying and arranging the performance test data to obtain performance classification data;

[0022] extracting key performance characteristics from the performance classification data;

[0023] Matching the key performance features with features in a preset chip feature library to obtain matching parameters;

[0024] Based on the matching parameters, determining a storage type range corresponding to the chip to be packaged;

[0025] Based on the storage type range, the storage type corresponding to the chip to be packaged is queried.

[0026] Optionally, the classifying the chips to be packaged based on the storage type to obtain a classified chipset includes:

[0027] Subdividing and defining the storage type to obtain a subdivided type;

[0028] Based on the subdivision type, setting a classification standard corresponding to the chip to be packaged;

[0029] Based on the classification standard, evaluating the group parameters corresponding to the chip to be packaged;

[0030] Based on the group parameters, determining the preliminary classification group corresponding to the chip to be packaged;

[0031] Based on the preliminary classification groups, the chips to be packaged are classified to obtain a classified chip group.

[0032] Optionally, using the substrate to construct a packaging infrastructure corresponding to the chip to be packaged includes:

[0033] Measuring the size of the substrate to obtain size data;

[0034] Based on the size data, designing a layout plan corresponding to the substrate;

[0035] Determining the connection point positions of the substrate according to the layout plan;

[0036] Performing preliminary connection on the connection point positions to obtain a preliminary connection structure;

[0037] Performing a stability test on the preliminary connection structure to obtain stability test parameters;

[0038] Based on the stable test parameters, basic packaging adjustments are performed on the preliminary connection structure to obtain a packaging basic structure.

[0039] Optionally, the performing defect detection on the dried package body to obtain potential package defects includes:

[0040] Performing appearance inspection on the dry package body to obtain appearance inspection features;

[0041] Based on the appearance detection features, querying the potential defects corresponding to the dry package body;

[0042] Performing microscopic inspection on the potential defects to obtain microscopic inspection data;

[0043] Calculating a defect index corresponding to the microscopic inspection data;

[0044] Based on the defect index, defect detection is performed on the dried package body to obtain potential package defects.

[0045] Optionally, the calculating the defect index corresponding to the microscopic detection data includes:

[0046] The defect index corresponding to the microscopic inspection data is calculated using the following formula:

[0047]

[0048] in, represents the defect index corresponding to the microscopic inspection data, represents the microscopic monitoring point index corresponding to the microscopic detection data, represents the number of microscopic monitoring points corresponding to the microscopic detection data, Indicates The defect degree value of each microscopic inspection point, represents the average defect degree corresponding to the microscopic inspection data, represents the number of defect types corresponding to the microscopic inspection data, represents the defect type index corresponding to the microscopic inspection data, Indicates The severity value of each defect type.

[0049] Optionally, marking a package having the potential packaging defect in the dried package to obtain a marked package includes:

[0050] Generate a defect code corresponding to the potential packaging defect;

[0051] Based on the defect code, setting a marking symbol corresponding to the dry package;

[0052] Based on the marking symbol, construct a marking label template corresponding to the dry package;

[0053] Based on the marking label template, determining the position to be attached corresponding to the dry package body;

[0054] Based on the position to be attached, the package with the potential packaging defect in the dried package is marked with a label to obtain a marked package.

[0055] Optionally, in order to solve the above problem, the present invention provides a packaging system for implementing a memory chip, the system comprising:

[0056] A performance detection module is used to obtain a chip to be packaged, perform an appearance detection on the chip to be packaged, obtain chip appearance parameters, screen a qualified appearance chip corresponding to the chip to be packaged according to the chip appearance parameters, perform an electrical performance test on the qualified appearance chip, and obtain performance test data;

[0057] A chip classification module, used for querying the storage type corresponding to the chip to be packaged based on the performance test data, classifying the chip to be packaged based on the storage type to obtain a classified chip group, and querying the packaging material corresponding to the classified chip group, wherein the packaging material includes: a substrate, an adhesive and a sealing material;

[0058] A sealing processing module, used to construct a packaging basic structure corresponding to the chip to be packaged using the substrate, install the chip to be packaged in the packaging basic structure to obtain a basic packaged chip, use the adhesive to bond and fix the basic packaged chip, and use the sealing material to seal the bonded and fixed basic packaged chip to obtain a preliminary package body;

[0059] a label marking module, used for performing a drying process on the preliminary package to obtain a dried package, monitoring the packaging state corresponding to the dried package in real time, performing defect detection on the dried package based on the packaging state to obtain potential packaging defects, and marking a package with the potential packaging defects in the dried package to obtain a marked package;

[0060] The report generation module is used to repair the marked package to obtain a repaired package, detect performance indicators corresponding to the repaired package, grade the repaired package based on the performance indicators to obtain a graded package, query the graded process corresponding to the graded package, and generate a packaging report corresponding to the chip to be packaged based on the graded process.

[0061] Firstly, the present invention obtains the chip to be packaged, performs appearance inspection on the chip to be packaged, and obtains the chip appearance parameters, so as to timely discover the defects, scratches, stains and other problems on the chip surface, ensure that the appearance quality of the chip meets the requirements, thereby improving the reliability and stability of the chip. Secondly, it can provide an important reference basis for the subsequent packaging process, help optimize the packaging process, and improve the packaging efficiency and quality. At the same time, the present invention queries the storage type corresponding to the chip to be packaged based on the performance test data, and can more accurately determine the applicable scenarios and functional positioning of the chip. Different storage types have their own characteristics in terms of data storage speed, capacity, durability, etc. Clarifying the storage type through analysis of performance test data is helpful to apply the chip to the field where its advantages can be best exerted, and to achieve the optimal allocation of resources. The present invention constructs a packaging substrate corresponding to the chip to be packaged by using the substrate The basic structure provides a stable physical support and protection for the chip, can carry the chip, and disperse the stress it bears, preventing the chip from being damaged by external pressure or vibration during use, and ensuring a reliable connection between the chip and the external circuit, ensuring the stability and accuracy of signal transmission. The present invention obtains a dry package by drying the preliminary package, effectively removing the moisture that may remain inside the package, which may cause problems such as circuit short circuit, chip or packaging material corrosion during subsequent use. These risks can be greatly reduced by drying, ensuring the normal operation and service life of the chip. Furthermore, the present invention can restore the value of products with potential packaging defects to the greatest extent by repairing the marking package to obtain a repaired package, which can make the package that may have been discarded have a use function again, reducing resource waste and cost loss. Therefore, the packaging method and system for realizing storage chips proposed by the present invention can improve the packaging level of storage chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic diagram of a process for implementing a packaging method of a memory chip provided by an embodiment of the present invention;

[0063] Figure 2 A schematic diagram of a module for implementing a packaging system for a memory chip provided by an embodiment of the present invention.

[0064] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0065] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0066] The embodiment of the present application provides a packaging method for implementing a storage chip. The execution subject of the packaging method for implementing a storage chip includes but is not limited to at least one of the electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiment of the present application. In other words, the packaging method for implementing a storage chip can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc. The server can be an independent server, or it can be a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and basic cloud computing services such as big data and artificial intelligence platforms.

[0067] Reference Figure 1 FIG. 1 is a flow chart of a method for packaging a memory chip according to an embodiment of the present invention. In this embodiment, the method for packaging a memory chip includes:

[0068] S1. Obtain a chip to be packaged, perform appearance inspection on the chip to be packaged to obtain chip appearance parameters, screen qualified appearance chips corresponding to the chip to be packaged according to the chip appearance parameters, perform electrical performance test on the qualified appearance chips, and obtain performance test data.

[0069] The present invention obtains the chip to be packaged, performs appearance inspection on the chip to be packaged, and obtains the chip appearance parameters, so as to timely discover defects, scratches, stains and other problems on the chip surface, ensure that the appearance quality of the chip meets the requirements, thereby improving the reliability and stability of the chip. Secondly, it can provide an important reference basis for the subsequent packaging process, help optimize the packaging process, and improve packaging efficiency and quality.

[0070] Among them, the chip to be packaged refers to a chip that has not yet been packaged, which is usually produced in the semiconductor manufacturing process and needs to be packaged to become a final product and is used in various electronic devices; the chip appearance parameters refer to various data used to describe the appearance characteristics of the chip, such as the chip's size, shape, surface flatness, color, logo, etc. Optionally, the appearance inspection of the chip to be packaged can be achieved through image processing methods, such as: using image processing libraries such as Halcon and OpenCV to implement image preprocessing, feature extraction and defect detection functions.

[0071] Furthermore, the present invention screens the qualified-appearance chips corresponding to the chips to be packaged according to the chip appearance parameters, which can reduce performance problems caused by surface defects, reduce the risk of product failure during use, and ensure that only chips with no defects in appearance enter the subsequent packaging process, thereby improving the quality and reliability of the final product.

[0072] Among them, the qualified appearance chip refers to a chip that has no obvious defects, scratches, stains, breakage and other problems in appearance, and its appearance parameters such as size, shape, color, etc. meet the relevant standards and requirements. These chips have good surface flatness, clear and readable markings, and the overall appearance quality can meet the requirements of subsequent packaging and use. Optionally, the screening of the qualified appearance chips corresponding to the chips to be packaged can be achieved through a machine vision algorithm, such as: an edge detection algorithm can be used to detect whether the edge of the chip is complete, an image segmentation algorithm can be used to distinguish different parts of the chip, and a feature extraction algorithm can be used to extract the key features of the chip, and then the chip is judged whether it is qualified according to preset standards.

[0073] The present invention obtains performance test data by performing electrical performance tests on the chip with qualified appearance, and can accurately evaluate the actual electrical performance of the chip to ensure that it meets the expected performance standards. It can also help discover potential performance defects or unstable factors, make adjustments and optimizations in advance, and avoid failures in subsequent use, thereby improving the reliability and stability of the chip.

[0074] Among them, the performance test data refers to the comprehensive data that can comprehensively and accurately reflect the electrical performance status of the chip, which is finally obtained after a series of electrical performance tests and analyses are performed on chips with qualified appearance, including actual measured values, simulated values ​​and differences from standard values ​​of various electrical parameters.

[0075] As an embodiment of the present invention, the electrical performance test of the qualified appearance chip to obtain performance test data includes: applying a preset electrical test signal to the qualified appearance chip to obtain chip response data; calculating the electrical response value corresponding to the qualified appearance chip based on the response data; performing performance simulation on the qualified appearance chip based on the electrical parameter value combined with a preset electrical performance model to obtain simulated performance data; analyzing the difference index between the simulated performance data and preset standard performance data; and performing an electrical performance test on the qualified appearance chip based on the difference index to obtain performance test data.

[0076] Among them, the preset electrical test signal refers to an electrical signal with specific frequency, amplitude, waveform and other characteristics that is preset in order to comprehensively detect the electrical performance of the chip with qualified appearance, for example, including sinusoidal signals and pulse signals of different frequencies; the chip response data refers to the output signal or related feedback information generated by the chip with qualified appearance after receiving the preset electrical test signal, such as current change, voltage fluctuation, frequency response and other data; the electrical response value refers to the specific value extracted and calculated from the chip response data that can reflect the electrical performance of the chip, such as resistance value, capacitance value, inductance value, on-state voltage, off-state current, etc.; the preset electrical performance model refers to a mathematical or physical model established in advance to simulate the electrical performance of the chip under different working conditions; the simulated performance data refers to the performance-related data of the chip under specific working conditions simulated by the model by inputting the calculated electrical parameter values ​​into the preset electrical performance model; the difference index refers to the quantitative value of the degree of deviation between the simulated performance data and the preset standard performance data in various key parameters.

[0077] Furthermore, applying a preset electrical test signal to the chip with qualified appearance can be achieved through a signal generation library, such as a Python-based signal generation library, such as a combination of numpy and matplotlib libraries to customize the required test signal; calculating the electrical parameter values ​​of the chip with qualified appearance under different working conditions can be achieved through the following calculation formula; performing performance simulation on the chip with qualified appearance can be achieved through performance simulation tools, such as Spice, LTspice and other tools; analyzing the difference index between the simulated performance data and the preset standard performance data can be achieved through statistical analysis tools, such as SPSS and other tools; performing electrical performance testing on the chip with qualified appearance can be achieved through automatic testing equipment, such as ATE and other tools.

[0078] As an embodiment of the present invention, the calculating, based on the response data, the electrical response value corresponding to the chip with qualified appearance includes:

[0079] The electrical response value corresponding to the qualified chip is calculated using the following formula:

[0080]

[0081] in, Indicates the electrical response value corresponding to the qualified appearance chip, Indicates at time The current response value when Indicates at time The voltage response value when and Respectively represent the response start time and response end time corresponding to the response data, Represents the time variable " "The differential element for integration is time of small increments.

[0082] In detail, the current response value refers to the specific value of the current generated by the chip at different time points t, which reflects the change of the current over time during the operation of the chip; the voltage response value refers to the specific size of the voltage borne or output by the chip at a specific time t, and its value can reflect the dynamic change of the voltage of the chip during operation; the response start time refers to the initial moment when the collection of chip current and voltage and other response data begins; the response end time refers to the final moment when the collection of chip-related response data stops; the small increment of time t refers to dividing the time interval [t1, t2] into countless tiny parts when performing integral calculations, and dt represents each tiny time interval therein, which is used to accurately calculate the integral value within the entire time range.

[0083] S2. Based on the performance test data, query the storage type corresponding to the chip to be packaged, classify the chips to be packaged based on the storage type to obtain a classified chipset, query the packaging materials corresponding to the classified chipset, and the packaging materials include: a substrate, an adhesive and a sealing material.

[0084] The present invention queries the storage type corresponding to the chip to be packaged based on the performance test data, and can more accurately determine the applicable scenarios and functional positioning of the chip. Different storage types have their own characteristics in terms of data storage speed, capacity, durability, etc. Clarifying the storage type through analysis of performance test data helps to apply the chip to the field where its advantages can be best exerted, thereby achieving optimal resource allocation.

[0085] The storage type refers to a specific storage category to which the chip belongs, such as DRAM (dynamic random access memory), SRAM (static random access memory), Flash (flash memory), etc.

[0086] As an embodiment of the present invention, querying the storage type corresponding to the chip to be packaged based on the performance test data includes: classifying and organizing the performance test data to obtain performance classification data; extracting key performance features in the performance classification data; matching the key performance features with features in a preset chip feature library to obtain matching parameters; determining the storage type range corresponding to the chip to be packaged based on the matching parameters; and querying the storage type corresponding to the chip to be packaged based on the storage type range.

[0087] Among them, the performance classification data refers to the data set obtained after dividing the performance test data according to certain rules and standards, such as data classified according to different aspects such as electrical parameters, read and write speeds, and storage capacity; the key performance characteristics refer to important indicators or characteristics extracted from the performance classification data that can significantly reflect the performance characteristics and differences of the chip, such as the current size and maximum read and write speed under a specific operating voltage; the preset chip feature library refers to a pre-established database containing typical performance characteristics of various known storage type chips, which is used to compare and match with the characteristics of the chip to be packaged; the matching parameter refers to the value or indicator used to measure the degree of matching when matching the key performance characteristics with the characteristics in the preset chip feature library; the storage type range refers to the set of storage types to which the chip to be packaged belongs, which is preliminarily determined according to the matching parameters.

[0088] Furthermore, the classification and organization of the performance test data can be achieved through a clustering analysis algorithm, such as K-Means and other algorithms; the extraction of key performance features in the performance classification data can be achieved through feature selection tools, such as the SelectKBest method in the sklearn library, selecting the most important features according to specific evaluation criteria; the matching of the key performance features with the features in the preset chip feature library can be achieved through a pattern matching algorithm, such as regular expression matching and other algorithms; the determination of the storage type range corresponding to the chip to be packaged can be achieved through a decision tree algorithm, such as setting decision nodes according to different matching parameters to divide the storage type range; the query of the storage type corresponding to the chip to be packaged can be achieved through a classification model in deep learning, such as a convolutional neural network (CNN), to classify the chip and determine the storage type.

[0089] The present invention classifies the chips to be packaged based on the storage type to obtain classified chipsets, which helps to improve the accuracy of the production process. A special packaging plan and process can be formulated for each classified chipset, avoiding confusion and errors, thereby improving packaging efficiency and quality.

[0090] The classified chipset refers to the accurate and clear classification combination of chips to be packaged that is finally determined after further review and adjustment of the preliminary classification groups.

[0091] As an embodiment of the present invention, the chips to be packaged are classified based on the storage type to obtain a classified chipset, including: subdividing the storage type to obtain a subdivided type; setting a classification standard corresponding to the chips to be packaged based on the subdivided type; evaluating the group parameters corresponding to the chips to be packaged based on the classification standard; determining a preliminary classification group corresponding to the chips to be packaged based on the group parameters; and classifying the chips to be packaged based on the preliminary classification group to obtain a classified chipset.

[0092] Among them, the subdivision type refers to a more detailed and specific division of storage types, such as further subdividing flash memory storage types into SLC flash memory, MLC flash memory, TLC flash memory, etc.; the classification standard refers to the specific rules and conditions for classifying the chips to be packaged formulated according to the subdivision type, such as standards set according to storage capacity, read and write speed, operating voltage range, etc.; the group parameter refers to the specific indicators and values ​​used to evaluate which group the chip to be packaged should belong to, such as the specific storage capacity value of a certain storage type chip, the specific value of the read and write speed, etc.; the preliminary classification group refers to the category set to which the chip to be packaged may belong, which is preliminarily determined according to the group parameters.

[0093] Furthermore, the subdivision definition of the storage type can be achieved through a classification algorithm in data mining, such as a decision tree algorithm, which performs subdivision according to the characteristics of the storage type; the setting of the classification criteria corresponding to the chip to be packaged can be achieved through statistical analysis methods, such as mean, standard deviation, etc., to determine the threshold of key indicators as classification criteria; the evaluation of the group parameters corresponding to the chip to be packaged can be achieved through a performance testing tool, such as professional storage performance testing software to obtain accurate parameter values; the determination of the preliminary classification group corresponding to the chip to be packaged can be achieved through a fuzzy clustering algorithm, such as determining the preliminary group based on the fuzzy characteristics of the parameters; the classification of the chip to be packaged can be achieved through data visualization tools, such as Tableau and other tools.

[0094] By querying the packaging materials corresponding to the classified chipsets, the present invention can improve the quality and reliability of the product, and can effectively protect the chipsets from the influence of the external environment, such as electromagnetic interference, physical shock, humidity changes, etc., thereby extending the service life of the chipsets and improving the overall quality and reliability of the product.

[0095] Among them, the packaging material refers to various substances used to protect, fix, connect, dissipate heat, and insulate the packaged chip, including substrates (such as PCB substrates), adhesives (used to fix chips), sealing materials (such as epoxy resins, etc., used to provide waterproof, dustproof and corrosion protection), heat dissipation materials (such as thermal grease, metal heat sinks, etc.) and insulating materials (such as ceramics, plastics, etc.), etc. Optionally, the query of the packaging material corresponding to the classified chipset can be achieved through a database query system, such as: SQL Server or Oracle database, by establishing an association table between chipsets and packaging materials, and entering relevant information of the classified chipset for query.

[0096] S3. Use the substrate to construct a packaging basic structure corresponding to the chip to be packaged, install the chip to be packaged in the packaging basic structure to obtain a basic packaging chip, use the adhesive to bond and fix the basic packaging chip, and use the sealing material to seal the bonded and fixed basic packaging chip to obtain a preliminary packaging body.

[0097] The present invention utilizes the substrate to construct a packaging infrastructure corresponding to the chip to be packaged, thereby providing stable physical support and protection for the chip, being able to carry the chip and disperse the stress it bears, preventing the chip from being damaged due to external pressure or vibration during use, and ensuring a reliable connection between the chip and the external circuit, thereby guaranteeing the stability and accuracy of signal transmission.

[0098] The packaging infrastructure refers to a basic packaging architecture that is formed after stability testing of the preliminary connection structure and adjustment and optimization based on the test parameters, and can provide stable support and good electrical connection for the chip to be packaged.

[0099] As an embodiment of the present invention, the method of using the substrate to construct a packaging infrastructure corresponding to the chip to be packaged includes: measuring the size of the substrate to obtain size data; designing a layout plan corresponding to the substrate based on the size data; determining the connection point positions of the substrate according to the layout plan; performing preliminary connections on the connection point positions to obtain a preliminary connection structure; performing stability testing on the preliminary connection structure to obtain stability test parameters; and performing basic packaging adjustments on the preliminary connection structure based on the stability test parameters to obtain a packaging infrastructure.

[0100] Among them, the dimensional data refers to the measured values ​​of the linear dimensions of the substrate such as length, width, thickness, and related geometric parameters such as aperture and pin spacing; the layout plan refers to the design plan for the placement of components on the substrate, the connection direction between the substrate and the chip, etc., which is formulated based on the dimensional data of the substrate and, as well as the functions and performance requirements of the chip to be packaged; the connection point position refers to the specific position on the substrate and for mutual connection and fixation, which are usually carefully designed to ensure the stability of the connection and good electrical performance; the preliminary connection structure refers to the structure formed by the preliminary connection operation on the substrate after the connection point position is determined, and the connection at this time may not have been fully processed and tested; the stability test parameter refers to the relevant numerical value or index that can reflect its stability obtained during the stability test of the preliminary connection structure, such as vibration resistance, temperature resistance, connection resistance change, etc.

[0101] Furthermore, the dimension measurement of the substrate can be achieved by a laser measuring instrument, such as: accurately measuring the dimension by emitting laser and receiving reflected light; the layout planning corresponding to the design of the substrate can be achieved by a simulation algorithm, such as: finite element analysis (FEA), to simulate the electrical performance and thermal performance under different layouts; the determination of the connection point position of the substrate can be achieved by a computer-aided design tool, such as: the automatic wiring function of the CAD tool to recommend the connection point position; the preliminary connection of the connection point position can be achieved by thermal compression bonding technology, such as: using high temperature and pressure to achieve connection; the stability test of the preliminary connection structure can be achieved by a thermal cycle test box, such as: performing multiple temperature change cycles to observe the performance of the structure under temperature changes; the basic packaging adjustment of the preliminary connection structure can be achieved by an optimization algorithm, such as: a genetic algorithm, which automatically searches for the optimal packaging adjustment solution.

[0102] The present invention obtains a basic packaged chip by installing the chip to be packaged in the packaging basic structure, which can provide good physical protection for the chip, promote heat conduction and dissipation, and ensure that the chip works within a suitable temperature range, thereby maintaining stable performance and a long service life.

[0103] Among them, the basic packaged chip refers to the chip to be packaged that is successfully installed in the packaging basic structure to form a chip assembly that initially has certain protection, connection and heat dissipation functions. Optionally, the installation of the chip to be packaged in the packaging basic structure can be achieved by an automated placement machine, such as: using a high-speed and high-precision SMT placement machine to accurately place the chip at a specified position of the packaging basic structure.

[0104] Furthermore, the present invention obtains a preliminary package body by bonding and fixing the basic package chip with the adhesive and sealing the basic package chip after bonding and fixing with the sealing material, thereby ensuring the position stability of the chip in the package structure and avoiding displacement or loosening during subsequent use, transportation or external impact, thereby ensuring good connection and electrical performance between the chip and the package structure.

[0105] Among them, the preliminary packaging body refers to the one formed after the basic packaging chip is bonded and fixed with an adhesive and sealed with a sealing material. It has certain physical protection, connection stability and preliminary sealing, but may not have undergone subsequent more refined processing or optimized packaging form. Optionally, the bonding and fixing of the basic packaging chip can be achieved by an adhesive, such as: epoxy resin adhesive, silicone adhesive, etc.; the sealing of the basic packaging chip after bonding and fixing can be achieved by a sealing material, such as: rubber sealing material, silicone sealing material, etc.

[0106] S4, drying the preliminary package to obtain a dried package, monitoring the packaging state of the dried package in real time, performing defect detection on the dried package based on the packaging state to obtain potential packaging defects, and marking the package with the potential packaging defects in the dried package to obtain a marked package.

[0107] The present invention obtains a dry package by drying the preliminary package, thereby effectively removing moisture that may remain inside the package, which may cause problems such as circuit short circuit, chip or packaging material corrosion during subsequent use. The drying process can greatly reduce these risks and ensure the normal operation and service life of the chip.

[0108] Among them, the dried package body refers to a preliminary package body that has undergone a special drying process to remove most of the internal moisture, thereby achieving a certain degree of dryness and standard of dryness. Optionally, the drying of the preliminary package body can be achieved through a hot air circulation oven, such as: heating the package body through hot air circulation, setting the temperature within the range of 50-80 degrees Celsius, and drying for a certain period of time.

[0109] Furthermore, the present invention can timely discover potential packaging defects or abnormalities by real-time monitoring of the packaging state corresponding to the dry packaging body. For example, if there are tiny cracks in the packaging, poor sealing or material aging, the problem can be detected as soon as it occurs through real-time monitoring, so that timely repair measures can be taken to avoid further deterioration of the problem and affect chip performance.

[0110] Among them, the packaging state refers to the various characteristics and conditions presented by the dry packaging body at a specific moment, including but not limited to the integrity of the packaging body (whether there are cracks or damage), sealing (whether there is leakage or air permeability), physical and chemical properties of the material (such as hardness, degree of aging, whether there is corrosion), internal humidity and temperature distribution, bonding strength between the chip and the packaging material, etc. Optionally, the real-time monitoring of the packaging state corresponding to the dry packaging body can be achieved by X-ray detection equipment, such as: through X-ray imaging equipment, it can be clearly seen whether there are defects in the internal structure of the packaging body, such as chip displacement, voids, etc.

[0111] The present invention performs defect detection on the dry package body based on the package state to obtain potential package defects, thereby preventing potential quality problems in advance, tracing back to the links and factors in the production process, improving the process in a targeted manner, and improving the quality of subsequent packaged products.

[0112] The potential packaging defects refer to packaging deficiencies or problems that are ultimately determined through a series of testing and analysis steps, which may exist in the dry package and affect its performance and reliability.

[0113] As an embodiment of the present invention, the defect detection on the dry package body to obtain potential package defects includes: performing appearance detection on the dry package body to obtain appearance detection features; based on the appearance detection features, querying the potential defects corresponding to the dry package body; performing microscopic detection on the potential defects to obtain microscopic detection data; calculating the defect index corresponding to the microscopic detection data; and performing defect detection on the dry package body based on the defect index to obtain potential package defects.

[0114] Among them, the appearance inspection features refer to various characteristic information obtained by directly observing the appearance of the dry package, including the surface flatness, color consistency, presence of scratches, protrusions, depressions, foreign matter attachment, etc. of the package; the potential defects refer to the packaging problems or deficiencies that may be preliminarily speculated or suspected to exist in the dry package based on the appearance inspection features, such as signs of fine cracks on the surface, suspected uneven distribution of packaging materials, etc.; the microscopic inspection data refers to the detailed data obtained by more in-depth and subtle observation of potential defective parts through high-resolution inspection means, such as electron microscopes, atomic force microscopes, etc., such as the morphology, size, composition and other information of the microstructure; the defect index refers to a numerical indicator for quantifying the degree of defects of the package, which is obtained based on the microscopic inspection data through a specific calculation method or evaluation model.

[0115] Furthermore, the appearance inspection of the dry package body can be achieved through a machine vision system, such as: collecting images through a camera and automatically analyzing them using an image recognition algorithm; the query of the potential defects corresponding to the dry package body can be achieved through a machine learning classification algorithm, such as: training a large number of known appearance inspection features and corresponding potential defect data, and then classifying and predicting new appearance inspection features; the microscopic inspection of the potential defects can be achieved through an EDS method, such as: analyzing the elemental composition of the microscopic area on the basis of a scanning electron microscope to determine whether there is an abnormal component distribution; the calculation of the defect index corresponding to the microscopic inspection data can be achieved through the following formula; the defect inspection of the dry package body can be achieved through a ray inspection method, such as: X-ray tomography (CT), which can non-destructively obtain the three-dimensional structural information inside the package and detect hidden defects.

[0116] As an embodiment of the present invention, the calculating the defect index corresponding to the microscopic inspection data includes:

[0117] The defect index corresponding to the microscopic inspection data is calculated using the following formula:

[0118]

[0119] in, represents the defect index corresponding to the microscopic inspection data, represents the microscopic monitoring point index corresponding to the microscopic detection data, represents the number of microscopic monitoring points corresponding to the microscopic detection data, Indicates The defect degree value of each microscopic inspection point, represents the average defect degree corresponding to the microscopic inspection data, represents the number of defect types corresponding to the microscopic inspection data, represents the defect type index corresponding to the microscopic inspection data, Indicates The severity value of each defect type.

[0120] In detail, the microscopic monitoring points refer to specific positions or areas selected when performing microscopic inspection on the dry package, and information about the defects of the package is obtained by detecting these points; the defect degree value refers to a numerical representation of the quantified severity of the defect detected at each microscopic monitoring point, and the value is usually determined based on the characteristics of the defect, such as size, depth, shape and other factors; the defect degree average value refers to the arithmetic mean of the defect degree values ​​of all microscopic monitoring points, which is used to reflect the overall defect level; the number of defect types refers to the total number of different types of defects that may occur in the dry package; the defect type refers to specific defect manifestations such as cracks on the surface of the package, internal voids, uneven distribution of materials, looseness of the package joints, etc.; the severity value refers to a score that quantifies the severity of each defect type, which is usually determined based on the degree of influence of this type of defect on the performance and reliability of the package.

[0121] The present invention obtains marked packages by marking labels on the packages with potential package defects in the dry packages, thereby achieving effective classification and management, and can quickly distinguish products with potential defects from those without defects, facilitating subsequent processing and tracking, and improving work efficiency.

[0122] The marked package refers to a package obtained by marking a dry package with potential packaging defects, and the package has a clear mark.

[0123] As an embodiment of the present invention, the step of marking a package body having the potential packaging defect in the dry package body to obtain a marked package body includes: generating a defect code corresponding to the potential packaging defect; setting a marking symbol corresponding to the dry package body based on the defect code; constructing a marking label template corresponding to the dry package body based on the marking symbol; determining a position to be attached corresponding to the dry package body based on the marking label template; and marking a package body having the potential packaging defect in the dry package body based on the position to be attached to obtain a marked package body.

[0124] Among them, the defect code refers to a specific code set for a potential packaging defect in a dry package, which code usually includes a combination of numbers or letters about the defect type, severity, location, etc.; the marking symbol refers to a specific graphic, color or character or other identification determined based on the defect code for marking on the dry package; the marking label template refers to a pre-designed template containing the marking symbol and possible other relevant information (such as defect description, date, etc.), which is used to uniformly and standardizedly mark dry packages with potential packaging defects; the position to be attached refers to the position on the dry package that is determined to be most suitable for pasting the marking label after evaluation.

[0125] Furthermore, the generation of defect codes corresponding to the potential packaging defects can be achieved through a classification and coding system, such as: classification and coding according to characteristics such as the type, severity and location of the defect; the setting of the marking symbol corresponding to the dry package body can be achieved through marking symbol rules, such as: using circles, triangles and other graphics of different colors to represent different types of defects; the construction of the marking label template corresponding to the dry package body can be achieved through a label design tool, such as: integrating marking symbols, defect descriptions, dates and other information into one template; the determination of the position to be attached corresponding to the dry package body can be achieved through computer vision technology methods, such as: analyzing the surface features of the package body and automatically determining the best attachment position; the marking of the package body with the potential packaging defect in the dry package body can be achieved through an automatic labeling machine, such as: using an automatic labeling machine and quickly and accurately attaching the label to the package body according to a preset attachment position and label template.

[0126] S5. Repair the marked package to obtain a repaired package, detect performance indicators corresponding to the repaired package, grade the repaired package based on the performance indicators to obtain a graded package, query a grading process corresponding to the graded package, and generate a packaging report corresponding to the chip to be packaged based on the grading process.

[0127] The present invention repairs the marking package to obtain a repaired package, which can restore the value of products with potential packaging defects to the greatest extent, and can make the package that may have been discarded have a usable function again, thereby reducing resource waste and cost loss.

[0128] Among them, the repaired package refers to a package obtained after a series of targeted repair operations are performed on the marked package. On the basis of the original potential packaging defects, it undergoes defect repair, material reinforcement, performance optimization and other processing processes to make it reach or approach the standards of a normal package in terms of structural integrity, sealing, electrical performance, etc. Optionally, the repair treatment of the marked package can be achieved by a hot pressing repair method, such as: using a hot press to heat and pressurize specific parts of the package to reintegrate the packaging material and repair defects such as cracks or delamination.

[0129] Furthermore, by detecting the performance indicators corresponding to the repaired package, the present invention can ensure that the repaired package truly meets the expected quality standards, accurately determine whether the repair is successful, ensure that the repaired package can operate normally in various working environments, and reduce the risk of failure caused by poor performance.

[0130] Among them, the performance indicators refer to specific parameters used to measure the performance and capabilities of the repaired package in different aspects, including but not limited to the sealing of the package (such as whether it can effectively prevent moisture, dust, etc. from entering the interior), electrical properties (such as whether parameters such as resistance, capacitance, inductance, etc. meet the design requirements, the stability and accuracy of signal transmission), mechanical strength (such as pressure resistance, impact resistance, hardness and toughness of packaging materials), thermal properties (such as heat dissipation capacity, heat resistance, stability under different temperature environments) and appearance quality (such as surface flatness, no obvious defects, etc.) and other specific values ​​or characteristic descriptions. Optionally, the detection of the performance indicators corresponding to the repaired package can be achieved through performance measuring instruments, such as: multimeter, oscilloscope, LCR tester and other instruments.

[0131] The present invention performs a graded treatment on the repair package based on the performance index to obtain a graded package, which can clearly distinguish repair packages with different performance levels, facilitate accurate selection according to specific application requirements, and ensure the stability and reliability of the system.

[0132] The graded package refers to a package that is classified into a specific performance grade after the performance index analysis and grading processing are performed on the repaired package.

[0133] As an embodiment of the present invention, the repaired package is graded based on the performance indicator to obtain a graded package, including: analyzing an indicator parameter value corresponding to the performance indicator; determining a performance grade standard corresponding to the repaired package based on the indicator parameter value; dividing the grade interval corresponding to the repaired package according to the performance grade standard; generating a grade label corresponding to the repaired package based on the grade interval; and grading the repaired package based on the grade label to obtain a graded package.

[0134] Among them, the indicator parameter value refers to the numerical value corresponding to each indicator that specifically measures the performance of the repaired package. For example, the sealing performance indicator may correspond to the leakage rate value, and the electrical performance indicator may correspond to specific values ​​such as the resistance value and the capacitance value; the performance grade standard refers to the criterion for dividing different performance grades set for the repaired package according to different performance requirements and application scenarios; the grade interval refers to dividing the performance of the repaired package into different range intervals according to the performance grade standard, and each interval corresponds to a specific performance grade; the grade label refers to a specific symbol or name used to identify the performance grade of the repaired package. For example, labels such as "Grade A", "Grade B", and "Grade C" can be used to distinguish repaired packages of different performance grades.

[0135] Further, the analysis of the index parameter values ​​corresponding to the performance index can be implemented by a data analysis tool, such as using a statistical analysis tool to analyze a large amount of electrical performance test data, and calculating the average value, standard deviation, etc. of parameters such as resistance and capacitance as the electrical performance index parameter value; the determination of the performance grade standard corresponding to the repaired package can be implemented by referring to industry standards and specifications, such as for electronic packaging products, the relevant electronic industry standards can be referred to, and different performance grade requirements can be determined according to different application fields (such as consumer electronics, industrial control, aerospace, etc.); the division of the grade intervals corresponding to the repaired package can be implemented by an interval division algorithm, such as using an equidistant division method or a statistically based clustering algorithm to divide the parameter values ​​into different grade intervals such as high, medium, and low; the generation of the grade label corresponding to the repaired package can be implemented by a predefined label generation rule, such as using "Grade A", "Grade B", "Grade C" and other labels to correspond to different performance grade intervals respectively; the grading of the repaired package can be implemented by an automated grading device, such as using a conveyor belt and a sensor system to classify, transport and store the repaired package according to different grades.

[0136] The present invention helps to improve the transparency and traceability of the production process by querying the grading process corresponding to the graded package, and can clearly understand how each graded package is determined to be a specific grade through various links, so as to make targeted improvements and improve the accuracy and efficiency of grading.

[0137] The grading process refers to an ordered combination of a series of operation steps such as performance indicator analysis, grade determination, interval division, label generation and final grading processing of the repaired package, which covers the complete process from obtaining the performance indicator parameter value of the repaired package, through multiple links of judgment and processing, and finally classifying the package into a specific grade. Optionally, the query of the grading process corresponding to the graded package can be implemented through a process management tool, such as using a BPM tool to manage and query the grading process.

[0138] Furthermore, the present invention generates a packaging report corresponding to the chip to be packaged based on the grading process, which can clearly understand the performance of each chip to be packaged in the grading process, including the evaluation results of performance indicators, the basis for grading and the processing status of each link, which helps to achieve traceability of the packaging process.

[0139] Among them, the packaging report refers to a document that records in detail various information of the chip to be packaged during the entire packaging process, including basic information of the chip, such as model, specifications, etc.; test results and analysis of chip performance indicators in the grading process; chip grading status and corresponding grade description; process, method and technical parameters used in the packaging process; possible problems and solutions; as well as suggestions and precautions for the future use of the chip, etc. Optionally, the generation of the packaging report corresponding to the chip to be packaged can be achieved through a report generation tool, such as: Crystal Reports, JasperReports and other tools.

[0140] Firstly, the present invention obtains the chip to be packaged, performs appearance inspection on the chip to be packaged, and obtains the chip appearance parameters, so as to timely discover the defects, scratches, stains and other problems on the chip surface, ensure that the appearance quality of the chip meets the requirements, thereby improving the reliability and stability of the chip. Secondly, it can provide an important reference basis for the subsequent packaging process, help optimize the packaging process, and improve the packaging efficiency and quality. At the same time, the present invention queries the storage type corresponding to the chip to be packaged based on the performance test data, and can more accurately determine the applicable scenarios and functional positioning of the chip. Different storage types have their own characteristics in terms of data storage speed, capacity, durability, etc. Clarifying the storage type through analysis of performance test data is helpful to apply the chip to the field where its advantages can be best exerted, and to achieve the optimal allocation of resources. The present invention constructs a packaging substrate corresponding to the chip to be packaged by using the substrate The basic structure provides a stable physical support and protection for the chip, can carry the chip, and disperse the stress it bears, preventing the chip from being damaged by external pressure or vibration during use, and ensuring a reliable connection between the chip and the external circuit, ensuring the stability and accuracy of signal transmission. The present invention obtains a dry package by drying the preliminary package, effectively removing the moisture that may remain inside the package, which may cause problems such as circuit short circuit, chip or packaging material corrosion during subsequent use. These risks can be greatly reduced by drying, ensuring the normal operation and service life of the chip. Furthermore, the present invention can restore the value of products with potential packaging defects to the greatest extent by repairing the marking package to obtain a repaired package, which can make the package that may have been discarded have a use function again, reducing resource waste and cost loss. Therefore, the packaging method and system for realizing storage chips proposed by the present invention can improve the packaging level of storage chip packaging.

[0141] like Figure 2 1 is a functional module diagram of a packaging system for implementing a memory chip provided by an embodiment of the present invention.

[0142] The packaging system 200 for implementing a memory chip according to the present invention can be installed in an electronic device. According to the functions implemented, the packaging system 200 for implementing a memory chip can include a performance detection module 201, a chip classification module 202, a sealing processing module 203, a label marking module 204, and a report generation module 205. The module according to the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0143] In this embodiment, the functions of each module / unit are as follows:

[0144] The performance detection module 201 is used to obtain the chip to be packaged, perform appearance detection on the chip to be packaged, obtain chip appearance parameters, screen the qualified appearance chips corresponding to the chip to be packaged according to the chip appearance parameters, perform electrical performance test on the qualified appearance chips, and obtain performance test data;

[0145] The chip classification module 202 is used to query the storage type corresponding to the chip to be packaged based on the performance test data, classify the chip to be packaged based on the storage type to obtain a classified chip group, and query the packaging material corresponding to the classified chip group, wherein the packaging material includes: a substrate, an adhesive and a sealing material;

[0146] The sealing processing module 203 is used to construct a packaging basic structure corresponding to the chip to be packaged by using the substrate, install the chip to be packaged in the packaging basic structure to obtain a basic packaged chip, use the adhesive to bond and fix the basic packaged chip, and use the sealing material to seal the bonded and fixed basic packaged chip to obtain a preliminary package body;

[0147] The label marking module 204 is used to dry the preliminary package to obtain a dried package, monitor the packaging state of the dried package in real time, perform defect detection on the dried package based on the packaging state to obtain potential packaging defects, and mark the package with the potential packaging defects in the dried package to obtain a marked package;

[0148] The report generation module 205 is used to repair the marked package to obtain a repaired package, detect the performance indicators corresponding to the repaired package, grade the repaired package based on the performance indicators to obtain a graded package, query the grading process corresponding to the graded package, and generate a packaging report corresponding to the chip to be packaged based on the grading process.

[0149] In detail, the modules described in a packaging system 200 for implementing a memory chip described in an embodiment of the present invention adopt the same technical means as a packaging method for implementing a memory chip described in the accompanying drawings when used, and can produce the same technical effects, which will not be repeated here.

[0150] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A packaging method for a memory chip, characterized in that: The method comprises: Acquire a chip to be packaged, perform appearance inspection on the chip to be packaged to obtain chip appearance parameters, screen appearance-qualified chips corresponding to the chip to be packaged according to the chip appearance parameters, perform electrical performance test on the appearance-qualified chips to obtain performance test data, wherein the electrical performance test on the appearance-qualified chips to obtain performance test data includes: Applying a preset electrical test signal to the chip with qualified appearance to obtain chip response data; Calculating the electrical response value corresponding to the chip with qualified appearance based on the response data, wherein calculating the electrical response value corresponding to the chip with qualified appearance based on the response data includes: The electrical response value corresponding to the qualified chip is calculated using the following formula: in, Indicates the electrical response value corresponding to the qualified appearance chip, Indicates at time The current response value when Indicates at time The voltage response value when and Respectively represent the response start time and response end time corresponding to the response data, Represents the time variable" "The differential element for integration is time small increments of Based on the electrical response value and a preset electrical performance model, a performance simulation is performed on the chip with qualified appearance to obtain simulated performance data; Analyze the difference between the simulated performance data and the preset standard performance data; Based on the difference index, performing an electrical performance test on the chip with qualified appearance to obtain performance test data; Based on the performance test data, query the storage type corresponding to the chip to be packaged, classify the chip to be packaged based on the storage type to obtain a classified chipset, query the packaging material corresponding to the classified chipset, the packaging material includes: a substrate, an adhesive and a sealing material; Using the substrate to construct a packaging basic structure corresponding to the chip to be packaged, installing the chip to be packaged in the packaging basic structure to obtain a basic packaged chip, using the adhesive to bond and fix the basic packaged chip, and using the sealing material to seal the bonded and fixed basic packaged chip to obtain a preliminary package body; The preliminary package body is dried to obtain a dried package body, a packaging state corresponding to the dried package body is monitored in real time, and based on the packaging state, a defect detection is performed on the dried package body to obtain a potential packaging defect, wherein the defect detection on the dried package body to obtain a potential packaging defect includes: Performing appearance inspection on the dry package body to obtain appearance inspection features; Based on the appearance detection features, querying the potential defects corresponding to the dry package body; Performing microscopic inspection on the potential defects to obtain microscopic inspection data; Calculating the defect index corresponding to the microscopic inspection data, wherein calculating the defect index corresponding to the microscopic inspection data comprises: The defect index corresponding to the microscopic inspection data is calculated using the following formula: in, represents the defect index corresponding to the microscopic inspection data, represents the microscopic monitoring point index corresponding to the microscopic detection data, represents the number of microscopic monitoring points corresponding to the microscopic detection data, Indicates The defect degree value of each microscopic inspection point, represents the average defect degree corresponding to the microscopic inspection data, represents the number of defect types corresponding to the microscopic inspection data, represents the defect type index corresponding to the microscopic inspection data, Indicates Severity value of each defect type; Based on the defect index, defect detection is performed on the dried package to obtain potential package defects, and a package with the potential package defects in the dried package is marked with a label to obtain a marked package; The marked package is repaired to obtain a repaired package, performance indicators corresponding to the repaired package are detected, and based on the performance indicators, the repaired package is graded to obtain a graded package, a grading process corresponding to the graded package is queried, and a packaging report corresponding to the chip to be packaged is generated based on the grading process.

2. A packaging method for implementing a memory chip according to claim 1, characterized in that: The querying, based on the performance test data, of the storage type corresponding to the chip to be packaged includes: Classifying and arranging the performance test data to obtain performance classification data; extracting key performance characteristics from the performance classification data; Matching the key performance features with features in a preset chip feature library to obtain matching parameters; Based on the matching parameters, determining a storage type range corresponding to the chip to be packaged; Based on the storage type range, the storage type corresponding to the chip to be packaged is queried.

3. A packaging method for implementing a memory chip according to claim 1, characterized in that: The step of classifying the chips to be packaged based on the storage type to obtain a classified chipset includes: Subdividing and defining the storage type to obtain a subdivided type; Based on the subdivision type, setting a classification standard corresponding to the chip to be packaged; Based on the classification standard, evaluating the group parameters corresponding to the chip to be packaged; Based on the group parameters, determining the preliminary classification group corresponding to the chip to be packaged; Based on the preliminary classification groups, the chips to be packaged are classified to obtain a classified chip group.

4. A packaging method for implementing a memory chip according to claim 1, characterized in that: The step of using the substrate to construct a packaging infrastructure corresponding to the chip to be packaged includes: Measuring the size of the substrate to obtain size data; Based on the size data, designing a layout plan corresponding to the substrate; Determining the connection point positions of the substrate according to the layout plan; Performing preliminary connection on the connection point positions to obtain a preliminary connection structure; Performing a stability test on the preliminary connection structure to obtain stability test parameters; Based on the stable test parameters, basic packaging adjustments are performed on the preliminary connection structure to obtain a packaging basic structure.

5. A packaging method for implementing a memory chip as claimed in claim 1, characterized in that: The step of marking a package having the potential packaging defect in the dried package to obtain a marked package includes: Generate a defect code corresponding to the potential packaging defect; Based on the defect code, setting a marking symbol corresponding to the dry package; Based on the marking symbol, construct a marking label template corresponding to the dry package; Based on the marking label template, determining the position to be attached corresponding to the dry package body; Based on the position to be attached, the package with the potential packaging defect in the dried package is marked with a label to obtain a marked package.

6. A packaging system for implementing a memory chip, characterized in that: A system for executing a packaging method for a memory chip as claimed in any one of claims 1 to 5, the system comprising: The performance detection module is used to obtain the chip to be packaged, perform appearance detection on the chip to be packaged, obtain chip appearance parameters, screen the qualified appearance chips corresponding to the chip to be packaged according to the chip appearance parameters, perform electrical performance test on the qualified appearance chips, and obtain performance test data, wherein the electrical performance test on the qualified appearance chips to obtain performance test data includes: Applying a preset electrical test signal to the chip with qualified appearance to obtain chip response data; Calculating the electrical response value corresponding to the chip with qualified appearance based on the response data, wherein calculating the electrical response value corresponding to the chip with qualified appearance based on the response data includes: The electrical response value corresponding to the qualified chip is calculated using the following formula: in, Indicates the electrical response value corresponding to the qualified appearance chip, Indicates at time The current response value when Indicates at time The voltage response value when and Respectively represent the response start time and response end time corresponding to the response data, Represents the time variable" "The differential element for integration is time small increments of Based on the electrical response value and a preset electrical performance model, a performance simulation is performed on the chip with qualified appearance to obtain simulated performance data; Analyze the difference between the simulated performance data and the preset standard performance data; Based on the difference index, performing an electrical performance test on the chip with qualified appearance to obtain performance test data; A chip classification module, used for querying the storage type corresponding to the chip to be packaged based on the performance test data, classifying the chip to be packaged based on the storage type to obtain a classified chip group, and querying the packaging material corresponding to the classified chip group, wherein the packaging material includes: a substrate, an adhesive and a sealing material; A sealing processing module, used to construct a packaging basic structure corresponding to the chip to be packaged using the substrate, install the chip to be packaged in the packaging basic structure to obtain a basic packaged chip, use the adhesive to bond and fix the basic packaged chip, and use the sealing material to seal the bonded and fixed basic packaged chip to obtain a preliminary package body; The label marking module is used to dry the preliminary package to obtain a dried package, monitor the packaging state corresponding to the dried package in real time, and perform defect detection on the dried package based on the packaging state to obtain potential packaging defects, wherein the defect detection on the dried package to obtain potential packaging defects includes: Performing appearance inspection on the dry package body to obtain appearance inspection features; Based on the appearance detection features, querying the potential defects corresponding to the dry package body; Performing microscopic inspection on the potential defects to obtain microscopic inspection data; Calculating the defect index corresponding to the microscopic inspection data, wherein calculating the defect index corresponding to the microscopic inspection data comprises: The defect index corresponding to the microscopic inspection data is calculated using the following formula: in, represents the defect index corresponding to the microscopic inspection data, represents the microscopic monitoring point index corresponding to the microscopic detection data, represents the number of microscopic monitoring points corresponding to the microscopic detection data, Indicates The defect degree value of each microscopic inspection point, represents the average defect degree corresponding to the microscopic inspection data, represents the number of defect types corresponding to the microscopic inspection data, represents the defect type index corresponding to the microscopic inspection data, Indicates Severity value of each defect type; Based on the defect index, defect detection is performed on the dried package to obtain potential package defects, and a package with the potential package defects in the dried package is marked with a label to obtain a marked package; The report generation module is used to repair the marked package to obtain a repaired package, detect performance indicators corresponding to the repaired package, grade the repaired package based on the performance indicators to obtain a graded package, query the graded process corresponding to the graded package, and generate a packaging report corresponding to the chip to be packaged based on the graded process.

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