Heterojunction battery and its manufacturing method and photovoltaic module

Abstract

The present application discloses a heterojunction battery and a manufacturing method thereof and a photovoltaic module, and relates to the field of photovoltaic technology. The heterojunction battery provided by the present application includes a silicon wafer layer, a first intrinsic amorphous silicon layer, an n-type doped microcrystalline silicon layer, a first transparent conductive layer, a second intrinsic amorphous silicon layer, a p-type doped microcrystalline silicon layer, a second transparent conductive layer and an auxiliary layer. Among them, the front side of the silicon wafer layer is a velvet surface, the back side of the silicon wafer layer is a polished surface, the first intrinsic amorphous silicon layer, the n-type doped microcrystalline silicon layer and the first transparent conductive layer are sequentially stacked on the front side of the silicon wafer layer, the second intrinsic amorphous silicon layer, the p-type doped microcrystalline silicon layer, the second transparent conductive layer and the auxiliary layer are sequentially stacked on the back side of the silicon wafer layer, the second transparent conductive layer includes a first ITO layer, an IZrO layer and a second ITO layer stacked in sequence, and the material of the auxiliary layer is IZrO. The heterojunction battery has better reliability and packaging performance.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a heterojunction battery and a manufacturing method thereof and a photovoltaic module. Background Art

[0002] With the development of high-efficiency battery component technology, heterojunction cells (HJT) have become the mainstream development trend of the photovoltaic industry. At the same time, due to its many advantages such as no light decay, high bifaciality, low-temperature process, high conversion efficiency and low temperature coefficient, it has been recognized by the industry as the next generation of mass-produced photovoltaic cell technology with great market prospects. The silicon heterojunction cell in the related technology includes a silicon wafer layer and an intrinsic silicon layer, a doped silicon layer and a transparent conductive layer deposited on both sides of the silicon wafer layer in sequence. The transparent conductive layer is used to collect photogenerated carriers and transport them to the metal electrode. Indium tin oxide (ITO) is a common material for the transparent conductive layer, which can play the role of light transmission and conductivity.

[0003] The inventors have found that the existing transparent conductive layer has poor thermal stability and corrosion resistance, so its service life is short. In addition, due to the hydrophobicity of the ITO layer, its adhesion with conventional adhesive films is poor, resulting in poor reliability of the packaged product. Summary of the invention

[0004] The purpose of the present application includes providing a heterojunction cell and a method for manufacturing the same, and a photovoltaic module, which can have better thermal stability and corrosion resistance, and can be well bonded to an adhesive film, and thus have better reliability.

[0005] The embodiments of the present application can be implemented as follows:

[0006] In a first aspect, the present application provides a heterojunction battery, comprising a silicon wafer layer, a first intrinsic amorphous silicon layer, an n-type doped microcrystalline silicon layer, a first transparent conductive layer, a second intrinsic amorphous silicon layer, a p-type doped microcrystalline silicon layer, a second transparent conductive layer and an auxiliary layer, wherein the front side of the silicon wafer layer is a velvet surface, and the back side of the silicon wafer layer is a polished surface, the first intrinsic amorphous silicon layer, the n-type doped microcrystalline silicon layer and the first transparent conductive layer are sequentially stacked on the front side of the silicon wafer layer, the second intrinsic amorphous silicon layer, the p-type doped microcrystalline silicon layer, the second transparent conductive layer and the auxiliary layer are sequentially stacked on the back side of the silicon wafer layer, the second transparent conductive layer comprises a first ITO layer, an IZrO layer and a second ITO layer which are sequentially stacked, and the material of the auxiliary layer is IZrO.

[0007] In an optional embodiment, the heterojunction battery further includes a first electrode and a second electrode, the first electrode is connected to the first transparent conductive layer, and the second electrode is connected to the second transparent conductive layer.

[0008] In an optional embodiment, the thickness of the silicon wafer layer is 80-180 μm;

[0009] and / or, the thickness of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 5-15 nm;

[0010] and / or, the thickness of the n-type doped microcrystalline silicon layer is 20-60 nm, and the thickness of the p-type doped microcrystalline silicon layer is 15-50 nm;

[0011] And / or, the thickness of the first transparent conductive layer is 70-150 nm, the thickness of the second transparent conductive layer is 80-180 nm, and the thickness of the second transparent conductive layer is greater than the thickness of the first transparent conductive layer;

[0012] And / or, the thickness of the auxiliary layer is 1-15 nm.

[0013] In an optional embodiment, the thickness of the first ITO layer is 45~80nm, the thickness of the IZrO layer is 0.8~1.2 times the difference between the thickness of the first ITO layer and the thickness of the p-type doped microcrystalline silicon layer, and the thickness of the second ITO layer is 0.55~0.85 times the thickness of the IZrO layer.

[0014] In an optional embodiment, the back side of the silicon wafer layer is obtained by polishing the suede surface, and the pyramid base angle of the suede surface after polishing is 10° to 25°.

[0015] In a second aspect, the present application provides a method for manufacturing a heterojunction battery, comprising:

[0016] Texturing is performed on both sides of the silicon wafer, and polishing is performed on the back side of the silicon wafer to obtain a silicon wafer layer;

[0017] A first intrinsic amorphous silicon layer and an n-type doped microcrystalline silicon layer are sequentially deposited on the front side of the silicon wafer layer, and a second intrinsic amorphous silicon layer and a p-type doped microcrystalline silicon layer are sequentially deposited on the back side of the silicon wafer layer;

[0018] Depositing a first transparent conductive layer on the n-type doped microcrystalline silicon layer, and sequentially depositing a first ITO layer, an IZrO layer, and a second ITO layer on the p-type doped microcrystalline silicon layer to form a second transparent conductive layer;

[0019] IZrO is deposited on the second ITO layer using an atomic layer deposition process to form an auxiliary layer.

[0020] In an optional embodiment, the step of depositing IZrO on the second ITO layer by an atomic layer deposition process to form an auxiliary layer includes:

[0021] On the second ITO layer, an indium precursor and a zirconium precursor are alternately used with an oxidant for reaction deposition to form an auxiliary layer formed by alternately stacking indium oxide thin films and zirconium oxide thin films;

[0022] The reaction temperature of depositing the auxiliary layer is below 160°C.

[0023] In an optional embodiment, the step of sequentially depositing a first ITO layer, an IZrO layer, and a second ITO layer on the p-type doped microcrystalline silicon layer to form a second transparent conductive layer includes:

[0024] Depositing a first ITO layer using a physical vapor deposition process or a rapid plasma deposition process;

[0025] The IZrO layer and the second ITO layer were deposited using an atomic layer deposition process.

[0026] In an optional embodiment, the step of depositing the first ITO layer by a physical vapor deposition process or a rapid plasma deposition process includes:

[0027] The first ITO sublayer is obtained by sputtering an ITO target, wherein the mass ratio of In2O3 to Sn is 90:10-98:2, the sputtering temperature is 180-280°C, the sputtering power is 0.1-10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%-5%, the gas flow rate Ar:O2 is 1:25-1:100, and water vapor is introduced to control the pressure in the reaction chamber to be 0.3-0.6 torr;

[0028] The second ITO sublayer is obtained by sputtering an ITO target, wherein the mass ratio of In2O3 to Sn is 90:10-98:2, the sputtering temperature is 180-280°C, the sputtering power is 0.1-10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%-5%, the gas flow rate Ar:O2 is 1:80-1:250, and water vapor is introduced to control the pressure in the reaction chamber to be 0.6-0.8 torr;

[0029] The third ITO sublayer is obtained by sputtering an ITO target, wherein the mass ratio of In2O3 and Sn is 90:10~98:2, the sputtering temperature is 180~280℃, the sputtering power is 0.1~10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%~5%, the gas flow rate Ar:O2 is 1:150~1:350, and water vapor is introduced to control the pressure in the reaction chamber to 0.8~1.2torr.

[0030] In an optional embodiment, the step of depositing the IZrO layer and the second ITO layer by an atomic layer deposition process comprises:

[0031] An indium precursor and a zirconium precursor are alternately used with an oxidant for reaction deposition to form an IZrO layer formed by alternating indium oxide films and zirconium oxide films;

[0032] Alternately using an indium precursor and a tin precursor with an oxidant for reaction deposition to form a second ITO layer formed by alternately stacking an indium oxide film and a tin oxide film;

[0033] The reaction temperature for depositing the IZrO layer and the second ITO layer is below 160°C.

[0034] In an optional embodiment, the step of texturing both sides of the silicon wafer and polishing the back side of the silicon wafer to obtain a silicon wafer layer includes:

[0035] Pre-cleaning the silicon wafer using a pre-cleaning solution comprising an alkaline solution and hydrogen peroxide;

[0036] The front and back sides of the silicon wafer are textured with a texturing liquid, wherein the texturing liquid contains 2% to 8% potassium hydroxide solution, 0.2% to 2% texturing additive, and the balance is deionized water, the texturing temperature is 70°C to 90°C, and the texturing time is 400s to 800s.

[0037] The back side of the silicon wafer is flattened by a polishing liquid, so that the base angle of the pyramid of the velvet surface on the back side of the silicon wafer is reduced to 10°~25°, wherein the polishing liquid contains hydrofluoric acid and nitric acid, the polishing temperature is 20℃~50℃, and the polishing time is 45s~150s.

[0038] In an optional embodiment, the texturing additive comprises, by volume, 0.05% to 2.5% potassium polyacrylate, 0.05% to 2.5% potassium sorbate, 2% to 7% polyethylene glycol, 0.05% to 2.5% potassium hydroxide, and the remainder is deionized water.

[0039] In an optional embodiment, the method for manufacturing a heterojunction battery further includes:

[0040] forming a first electrode on the first transparent conductive layer;

[0041] A second electrode is formed on the second transparent conductive layer. The second electrode penetrates the auxiliary layer and protrudes from a side of the auxiliary layer away from the second transparent conductive layer.

[0042] In a third aspect, the present application provides a photovoltaic module, comprising the heterojunction cell of any one of the aforementioned embodiments, or a heterojunction cell manufactured by the method for manufacturing the heterojunction cell of any one of the aforementioned embodiments.

[0043] The beneficial effects of the heterojunction battery and its manufacturing method and photovoltaic module provided in the embodiments of the present application include:

[0044] The heterojunction cell provided in the present application includes a silicon wafer layer, a first intrinsic amorphous silicon layer, an n-type doped microcrystalline silicon layer, a first transparent conductive layer, a second intrinsic amorphous silicon layer, a p-type doped microcrystalline silicon layer, a second transparent conductive layer and an auxiliary layer. The front side of the silicon wafer layer is a velvet surface, the back side of the silicon wafer layer is a polished surface, the first intrinsic amorphous silicon layer, the n-type doped microcrystalline silicon layer and the first transparent conductive layer are sequentially stacked on the front side of the silicon wafer layer, the second intrinsic amorphous silicon layer, the p-type doped microcrystalline silicon layer, the second transparent conductive layer and the auxiliary layer are sequentially stacked on the back side of the silicon wafer layer, the second transparent conductive layer includes a first ITO layer, an IZrO layer and a second ITO layer stacked in sequence, and the material of the auxiliary layer is IZrO. The second transparent conductive layer on the back of the heterojunction battery consists of a first ITO layer, an IZrO layer and a second ITO layer. The middle part of the second transparent conductive layer uses an IZrO layer to replace the original ITO. IZrO (indium zirconium oxide) has better thermal stability than ITO, making it more suitable for high-temperature application scenarios of solar cells. IZrO also has better mechanical strength, can withstand more physical stress, and is not easily damaged. Therefore, the second transparent conductive layer has better reliability and can increase the service life of the heterojunction battery. In addition, an auxiliary layer is provided on the second transparent conductive layer, and the material of the auxiliary layer is IZrO. IZrO has better corrosion resistance and is more resistant to acids, alkalis and organic solvents. The auxiliary layer can protect the second transparent conductive layer, so that the heterojunction battery can maintain reliable performance in harsh environments. By setting an auxiliary layer of IZrO, it is also beneficial to bond the adhesive film on the back of the heterojunction battery. Compared with ITO, IZrO can maintain better adhesion with the adhesive film, which is beneficial to the reliability of the product. Furthermore, the back side of the silicon wafer layer is a polished surface, which can significantly broaden the optimization upper limit of the back side passivation process of the heterojunction battery, facilitate the passivation at the interface of each film layer on the back side, improve the work function of the second transparent conductive layer on the back side, optimize the hole transport performance on the back side, improve the carrier mobility, and improve the battery efficiency.

[0045] The manufacturing method of the heterojunction battery provided in the embodiment of the present application is used to manufacture the above-mentioned heterojunction battery. Among them, the auxiliary layer is made by atomic layer deposition process, has a dense and flat surface, and has fewer surface defects, so that the auxiliary layer has better mechanical properties and corrosion resistance, and can play a better protective role on the second transparent conductive layer.

[0046] The photovoltaic module provided in the embodiment of the present application includes the above-mentioned heterojunction battery or the heterojunction battery manufactured by the above-mentioned manufacturing method, and therefore has the advantages of better reliability and long service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 This is a schematic diagram of a heterojunction battery in one embodiment of the present application;

[0049] Figure 2 This is a flow chart of a method for manufacturing a heterojunction battery in one embodiment of the present application.

[0050] Icon: 100-silicon wafer layer; 110-first intrinsic amorphous silicon layer; 120-second intrinsic amorphous silicon layer; 200-n-type doped microcrystalline silicon layer; 300-first transparent conductive layer; 400-p-type doped microcrystalline silicon layer; 500-second transparent conductive layer; 510-first ITO layer; 520-IZrO layer; 530-second ITO layer; 600-auxiliary layer; 710-first electrode; 720-second electrode. DETAILED DESCRIPTION

[0051] In the related technology, the transparent conductive layer of silicon heterojunction cells is mainly made of indium tin oxide (ITO), but ITO has poor heat resistance and it is difficult to maintain stable performance in a high temperature environment for a long time. In addition, ITO is also susceptible to corrosion by acids and alkalis and has poor weather resistance. Regarding the packaging problem of heterojunction cells, the hydrophobicity of the ITO layer makes it poorly bonded to conventional adhesive films, and this problem is more obvious in heterojunction cells with polished back sides.

[0052] In order to improve at least one of the problems in the above-mentioned related technologies, an embodiment of the present application provides a heterojunction battery and a method for manufacturing the same, by adding an IZrO layer to the transparent conductive layer on the back side and adding an auxiliary layer outside the transparent conductive layer on the back side, so as to improve the reliability, service life and packaging performance of the heterojunction battery.

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0055] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0056] In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, it is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the invention is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0057] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0058] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0059] Figure 1 Schematic diagram of a heterojunction battery in one embodiment of the present application. Figure 1 As shown, the heterojunction cell provided in the embodiment of the present application includes a silicon wafer layer 100, a first intrinsic amorphous silicon layer 110, an n-type doped microcrystalline silicon layer 200, a first transparent conductive layer 300, a second intrinsic amorphous silicon layer 120, a p-type doped microcrystalline silicon layer 400, a second transparent conductive layer 500 and an auxiliary layer 600. Among them, the front side of the silicon wafer layer 100 is a velvet surface, the back side of the silicon wafer layer 100 is a polished surface, the first intrinsic amorphous silicon layer 110, the n-type doped microcrystalline silicon layer 200 and the first transparent conductive layer 300 are sequentially stacked on the front side of the silicon wafer layer 100, the second intrinsic amorphous silicon layer 120, the p-type doped microcrystalline silicon layer 400, the second transparent conductive layer 500 and the auxiliary layer 600 are sequentially stacked on the back side of the silicon wafer layer 100, the second transparent conductive layer 500 includes a first ITO layer 510, an IZrO layer 520 and a second ITO layer 530 which are sequentially stacked, and the material of the auxiliary layer 600 is IZrO.

[0060] Furthermore, the heterojunction battery further includes a first electrode 710 and a second electrode 720, wherein the first electrode 710 is connected to the first transparent conductive layer 300, and the second electrode 720 is connected to the second transparent conductive layer 500. In this embodiment, the second electrode 720 penetrates the auxiliary layer 600 and extends to the side of the auxiliary layer 600 away from the second transparent conductive layer 500.

[0061] In this embodiment, the pyramid base angle of the velvet surface on the front side of the silicon wafer layer 100 is 45° to 55°. The velvet surface can reduce light reflection, improve light capture efficiency, and thus improve light utilization. In addition, the velvet surface structure can improve contact with the first electrode 710.

[0062] In the present embodiment, the back side of the silicon wafer layer 100 is a polished surface. It should be understood that the polished surface does not mean that it is a completely flat mirror surface; in the present embodiment, the back side of the silicon wafer layer 100 is obtained by polishing the velvet surface, that is, the polished surface is the polished velvet surface. Specifically, the pyramid base angle of the velvet surface after polishing is 25°~10°. The inventors found that there are a series of problems on the P side (back side) of the heterojunction battery at present, which will directly affect the battery efficiency, namely: the overall crystallization rate is lower than that of the N side (front side); there is room for optimization in matching the work function of the transparent conductive layer. After the back side of the silicon wafer layer 100 is flattened, the stress of the pyramid tip on the back side is reduced, and the phenomenon of different pyramid sizes is eliminated, which releases the window of the passivation process of each contact surface. The treatment at the interface is more likely to achieve the effect of both high open circuit voltage and high short circuit current. While ensuring uniformity, the film quality is better and the thickness is thinner, which brings obvious efficiency improvement.

[0063] In this embodiment, the silicon wafer layer 100 is n-type single crystal silicon. The first intrinsic amorphous silicon layer 110 and the second intrinsic amorphous silicon layer 120 are hydrogenated amorphous silicon, which can effectively passivate the dangling bonds on the surface of crystalline silicon and reduce the surface recombination centers, thereby increasing the life of carriers and the open circuit voltage (Voc) of the battery. This is due to the presence of hydrogen atoms in the intrinsic amorphous silicon layer, which can terminate the dangling bonds of silicon atoms, reduce defects, and improve the transmission efficiency of charge carriers. The n-type doped microcrystalline silicon layer 200 and the p-type doped microcrystalline silicon layer 400 are hydrogenated microcrystalline silicon, and the grain size of microcrystalline silicon is smaller than that of polycrystalline silicon, but larger than the disordered region in amorphous silicon. Microcrystalline silicon generally has a wide spectral absorption range, can absorb short-wavelength light, supplement the insufficient absorption of single crystal silicon in certain wavelength ranges, and improve the total light absorption efficiency of the battery.

[0064] In this embodiment, the thickness of the silicon wafer layer 100 is 80-180 μm, for example, any one of 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, or an intermediate value between any two values.

[0065] The thickness of the first intrinsic amorphous silicon layer 110 and the second intrinsic amorphous silicon layer 120 are both 5-15 nm, for example, any value among 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm or an intermediate value between any two points.

[0066] The thickness of the n-type doped microcrystalline silicon layer 200 is 20~60nm, for example, any one of 20nm, 30nm, 40nm, 50nm, 60nm or an intermediate value between any two point values; the thickness of the p-type doped microcrystalline silicon layer 400 is 15~50nm, for example, any one of 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm or an intermediate value between any two point values.

[0067] The thickness of the first transparent conductive layer 300 is 70-150 nm, the thickness of the second transparent conductive layer 500 is 80-180 nm, and the thickness of the second transparent conductive layer 500 is greater than that of the first transparent conductive layer 300 .

[0068] Optionally, the thickness of the first ITO layer is 45-80 nm, the thickness of the IZrO layer is 0.8-1.2 times the difference between the thickness of the first ITO layer and the thickness of the p-type doped microcrystalline silicon layer, and the thickness of the second ITO layer is 0.55-0.85 times the thickness of the IZrO layer.

[0069] The thickness of the auxiliary layer 600 is 1-15 nm, for example, any value among 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm or an intermediate value between any two points.

[0070] Optionally, the material of the first transparent conductive layer 300 can be at least one of AZO, ITO, ITO:H, IWO, ICO, SnO2, IZrO, and GaIO. For example, the first transparent conductive layer 300 can be made of ITO material, or a similar ITO / IZrO / ITO structure as the second transparent conductive layer 500.

[0071] The material of the first electrode 710 and the second electrode 720 can be at least one of gold, silver, copper, aluminum, molybdenum, tin, and nickel.

[0072] In the embodiment of the present application, an IZrO layer 520 is added to the second transparent conductive layer 500. IZrO has better thermal stability than ITO, making it more suitable for high-temperature application scenarios of solar cells. IZrO also has better mechanical strength, can withstand more physical stress, and is not easily damaged. Therefore, the second transparent conductive layer 500 has better reliability and can improve the service life of the heterojunction battery. In addition, an auxiliary layer 600 is provided on the second transparent conductive layer 500, and the material of the auxiliary layer 600 is IZrO. IZrO has better corrosion resistance and is more resistant to acid, alkali and organic solvents. The auxiliary layer 600 can protect the second transparent conductive layer 500, so that the heterojunction battery can maintain reliable performance in harsh environments. By providing an auxiliary layer 600 made of IZrO material, it is also beneficial to the adhesive film on the back of the heterojunction battery. Compared with ITO, IZrO can maintain better adhesion with the adhesive film, so it is beneficial to the reliability of the product. In addition, IZrO itself has good light transmittance, which can also ensure the optical performance of heterojunction batteries.

[0073] Figure 2 Flow chart of a method for manufacturing a heterojunction battery in one embodiment of the present application. The method for manufacturing a heterojunction battery provided in the embodiment of the present application can be used to manufacture the above-mentioned heterojunction battery. Figure 2 As shown, the method for manufacturing a heterojunction battery provided in the embodiment of the present application includes:

[0074] Step S100 , texturing is performed on both sides of the silicon wafer, and polishing is performed on the back side of the silicon wafer to obtain a silicon wafer layer 100 .

[0075] In the embodiment of the present application, step S100 may specifically include:

[0076] Step S110, pre-cleaning the silicon wafer using a pre-cleaning solution containing an alkaline solution and hydrogen peroxide;

[0077] Step S120, texturing the front and back sides of the silicon wafer with a texturing liquid, wherein the texturing liquid comprises, by volume, 2% to 8% potassium hydroxide solution, 0.2% to 2% texturing additive, and the remainder is deionized water, the texturing temperature is 70° C. to 90° C., and the texturing time is 400s to 800s;

[0078] Step S130, using a polishing liquid to flatten the back side of the silicon wafer, so that the base angle of the pyramid of the velvet surface on the back side of the silicon wafer is reduced to 10°~25°, wherein the polishing liquid contains hydrofluoric acid and nitric acid, the polishing temperature is 20°C~50°C, and the polishing time is 45s~150s.

[0079] In this embodiment, the pre-cleaning step can effectively remove organic dirt, metal impurities and surface damage layers on the surface of the silicon wafer. The alkaline solution in the pre-cleaning solution can be one of a potassium hydroxide solution or a sodium hydroxide solution. For example, the volume proportion of the alkaline solution in the pre-cleaning solution is 5%, and the volume proportion of hydrogen peroxide is 8%. Optionally, the concentration range of the alkaline solution (such as potassium hydroxide solution or sodium hydroxide solution) is 15 mol / L~25mol / L, and the concentration range of hydrogen peroxide in hydrogen peroxide is 5mol / L~12mol / L. The temperature of the pre-cleaning process is 45℃~85℃, and the process time is 40s~150s.

[0080] In the embodiment of the present application, the concentration range of potassium hydroxide solution for preparing the texturing liquid is 15 mol / L~25 mol / L. The texturing additive comprises 0.05%~2.5% potassium polyacrylate, 0.05%~2.5% potassium sorbate, 2%~7% polyethylene glycol, 0.05%~2.5% potassium hydroxide, and the balance is deionized water.

[0081] The equipment used in the texturing step is a texturing tank. Optionally, the circulation flow rate during the texturing process is 50L / m, and the discharge factor is 0.065~0.095.

[0082] After the texturing step S120, the silicon wafer may be cleaned first and then polished; the cleaning method may be the same as the pre-cleaning method of step S110.

[0083] In step S130, the polishing liquid is a mixture of hydrofluoric acid and nitric acid, wherein the concentration of the hydrofluoric acid solution is 20mol / L~30mol / L, and the concentration of the nitric acid solution is 10mol / L~15mol / L. The temperature range of the polishing process is preferably 20℃~50℃, without specific restrictions. The time of the polishing process is 45s~150s. The polishing process uses a polishing etcher, and the initial HF:HNO3 volume ratio in the etching tank is 1:4~8; the circulating liquid replenishment volume is 1:2~6 for every 1000pcs of liquid replenishment HF:HNO3 volume ratio, and the etching tank opens the water film protection; the silicon wafer passes through the polishing etcher at a belt speed of 0.5~2.5 m / min to complete the polishing.

[0084] Step S200 , depositing a first intrinsic amorphous silicon layer 110 and an n-type doped microcrystalline silicon layer 200 on the front side of the silicon wafer layer 100 , and depositing a second intrinsic amorphous silicon layer 120 and a p-type doped microcrystalline silicon layer 400 on the back side of the silicon wafer layer 100 .

[0085] In this embodiment, the first intrinsic amorphous silicon layer 110 , the n-type doped microcrystalline silicon layer 200 , the second intrinsic amorphous silicon layer 120 and the p-type doped microcrystalline silicon layer 400 may be deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0086] In step S300 , a first transparent conductive layer 300 is deposited on the n-type doped microcrystalline silicon layer 200 , and a first ITO layer 510 , an IZrO layer 520 and a second ITO layer 530 are sequentially deposited on the p-type doped microcrystalline silicon layer 400 to form a second transparent conductive layer 500 .

[0087] The second transparent conductive layer 500 can be prepared in the following manner:

[0088] Step S310, depositing a first ITO layer 510 by using a physical vapor deposition process or a rapid plasma deposition process;

[0089] Step S320 , depositing an IZrO layer 520 and a second ITO layer 530 by using an atomic layer deposition process.

[0090] In this embodiment, the first ITO layer 510 can be manufactured by magnetron sputtering. Optionally, step S310 specifically includes:

[0091] The first ITO sublayer is obtained by sputtering an ITO target, wherein the mass ratio of In2O3 to Sn is 90:10-98:2, the sputtering temperature is 180-280°C (e.g., 200°C), the sputtering power is 0.1-10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%-5%, the gas flow rate Ar:O2 is 1:25-1:100 (e.g., 1:50-1:80), and water vapor is introduced to control the pressure in the reaction chamber to be 0.3-0.6 torr;

[0092] The second ITO sublayer is obtained by sputtering an ITO target, wherein the mass ratio of In2O3 to Sn is 90:10-98:2, the sputtering temperature is 180-280°C (e.g., 220°C), the sputtering power is 0.1-10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%-5%, the gas flow rate Ar:O2 is 1:80-1:250 (e.g., 1:100-1:200), and water vapor is introduced to control the pressure in the reaction chamber to be 0.6-0.8 torr;

[0093] The third ITO sublayer is obtained by sputtering an ITO target, wherein the mass ratio of In2O3 to Sn is 90:10-98:2, the sputtering temperature is 180-280°C (e.g., 200°C), the sputtering power is 0.1-10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%-5%, the gas flow rate Ar:O2 is 1:150-1:350 (e.g., 1:200-1:300), and water vapor is introduced to control the pressure in the reaction chamber to be 0.8-1.2 torr.

[0094] In this embodiment, the production of the first ITO layer 510 is carried out in three sub-steps. In the process of producing the first ITO sub-layer, the second ITO sub-layer and the third ITO sub-layer, the proportion of O2 in the sputtering atmosphere gradually increases, and the reaction pressure also gradually increases. The higher the oxygen content, the lower the refractive index, the higher the light transmission effect, which is conducive to making a high-refractive structure of the bottom layer (close to the p-type doped microcrystalline silicon layer 400) to improve the optical performance. Less oxygen in the contact surface with the microcrystal can reduce the interface state defect density and reduce composite defects. Optionally, the thickness of the first ITO sub-layer is 15~25nm, the thickness of the second ITO sub-layer is 20~35nm, and the thickness of the third ITO sub-layer is 10~20nm.

[0095] Furthermore, step S320 specifically includes:

[0096] Alternately using an indium precursor and a zirconium precursor with an oxidant for reaction deposition to form an IZrO layer 520 formed by alternately stacking indium oxide thin films and zirconium oxide thin films;

[0097] Alternately using an indium precursor and a tin precursor with an oxidant for reaction deposition to form a second ITO layer 530 formed by alternately stacking indium oxide thin films and tin oxide thin films;

[0098] The reaction temperature for depositing the IZrO layer 520 and the second ITO layer 530 is below 160°C.

[0099] The IZrO layer 520 and the second ITO layer 530 prepared by the atomic layer deposition process have a denser structure and better bonding with adjacent layer structures. Compared with physical vapor deposition methods such as magnetron sputtering, the atomic layer deposition process has a lower reaction temperature and reduces the impact of high-energy particles on the substrate, which can protect the substrate from damage, thereby improving battery performance.

[0100] Optionally, in step S320, the indium precursor may be at least one of trimethyl indium, triethyl indium, and cyclopentadienyl indium; the tin precursor may be at least one of tetrakis(dimethylamino)tin and tetrabutyltin; the zirconium precursor may be at least one of tetrabutyl zirconium, tetraethyl zirconium, tetramethyl zirconium, tetraisopropyl zirconium, and zirconium chloride. The oxidant may be at least one of water, ozone, oxygen, and hydrogen peroxide.

[0101] In this embodiment, the manufacturing method of the first transparent conductive layer 300 can be the same as the manufacturing method of the first ITO layer 510, and the manufactured first transparent conductive layer 300 is made of ITO material. Alternatively, the manufacturing method of the first transparent conductive layer 300 can be the same as the manufacturing method of the second transparent conductive layer 500, and the manufactured first transparent conductive layer 300 is a three-layer structure of ITO / IZrO / ITO.

[0102] In step S400 , IZrO is deposited on the second ITO layer 530 by using an atomic layer deposition process to form an auxiliary layer 600 .

[0103] In an embodiment of the present application, step S400 specifically includes: alternately using an indium precursor and a zirconium precursor to react with an oxidant on the second ITO layer 530 to form an auxiliary layer 600 formed by alternating stacking of indium oxide films and zirconium oxide films; wherein the reaction temperature for depositing the auxiliary layer 600 is below 160°C.

[0104] The auxiliary layer 600 formed by the atomic layer deposition process has a high density and can effectively protect the second transparent conductive layer 500, and the optical and electrical properties of IZrO are not inferior to those of the ITO film. In this embodiment, the auxiliary layer 600 is deposited by the atomic layer deposition process, which can avoid the impact of high-energy particles and high temperature on the second transparent conductive layer 500 and protect the performance of the second transparent conductive layer 500 from being affected. In addition, the bonding strength between IZrO and the packaging film is significantly improved compared to ITO, which can significantly reduce the material cost of component packaging.

[0105] In step S500 , a first electrode 710 is formed on the first transparent conductive layer 300 , and a second electrode 720 is formed on the second transparent conductive layer 500 . The second electrode 720 penetrates the auxiliary layer 600 and protrudes from a side of the auxiliary layer 600 away from the second transparent conductive layer 500 .

[0106] In the embodiment of the present application, the first electrode 710 and the second electrode 720 can be made by screen printing technology. The printing paste is a low-temperature paste, and the second electrode 720 on the back is made by low-temperature burning through the auxiliary layer 600 and contacting the second transparent conductive layer 500. The curing temperature of the electrode is 195°C to 245°C. In this embodiment, the pattern of the heterojunction battery can adopt a multi-busbar or no busbar solution.

[0107] An embodiment of the present application also provides a photovoltaic module, comprising the above-mentioned heterojunction cell.

[0108] The beneficial effects of the heterojunction battery and the manufacturing method thereof provided in the embodiments of the present application are as follows:

[0109] The transparent conductive layer of ITO material used in mass production needs to be at a certain thickness to ensure the compactness of the film layer; at the same time, in the existing deposition process, the impact of high-energy particles and the heat generated will damage the deposited film layer. Since the optical and electrical properties of IZrO are not inferior to ITO, and the conductivity of IZrO thin film is better than that of ITO layer at low Zr doping concentration, the IZrO layer 520 and the second ITO layer 530 are deposited using the atomic layer deposition process, which can significantly increase the density of the second transparent conductive layer 500 under the same thickness conditions, reduce the film thickness of the second transparent conductive layer 500, and improve the conductivity. The auxiliary layer 600 of IZrO material arranged outside the second transparent conductive layer 500 can prevent the inner second transparent conductive layer 500 from being damaged by heat or water vapor. At the same time, the bonding strength between the auxiliary layer 600 and the packaging film is significantly improved compared with ITO, which greatly reduces the material cost of component packaging.

[0110] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a heterojunction battery, characterized in that: include: Texturing both sides of the silicon wafer and polishing the back side of the silicon wafer to obtain a silicon wafer layer; Depositing a first intrinsic amorphous silicon layer and an n-type doped microcrystalline silicon layer in sequence on the front side of the silicon wafer layer, and depositing a second intrinsic amorphous silicon layer and a p-type doped microcrystalline silicon layer in sequence on the back side of the silicon wafer layer; Depositing a first transparent conductive layer on the n-type doped microcrystalline silicon layer, and sequentially depositing a first ITO layer, an IZrO layer, and a second ITO layer on the p-type doped microcrystalline silicon layer to form a second transparent conductive layer; Depositing IZrO on the second ITO layer by an atomic layer deposition process to form an auxiliary layer; The step of sequentially depositing a first ITO layer, an IZrO layer, and a second ITO layer on the p-type doped microcrystalline silicon layer to form a second transparent conductive layer comprises: Depositing the first ITO layer by a physical vapor deposition process or a rapid plasma deposition process; Depositing the IZrO layer and the second ITO layer using an atomic layer deposition process; The step of depositing the first ITO layer by using a physical vapor deposition process or a rapid plasma deposition process comprises: The first ITO sublayer is obtained by sputtering an ITO target, wherein the mass ratio of In2O3 to Sn is 90:10-98:2, the sputtering temperature is 180-280°C, the sputtering power is 0.1-10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%-5%, the gas flow rate Ar:O2 is 1:25-1:100, and water vapor is introduced to control the pressure in the reaction chamber to be 0.3-0.6 torr; The second ITO sublayer is obtained by sputtering an ITO target, wherein the mass ratio of In2O3 to Sn is 90:10-98:2, the sputtering temperature is 180-280°C, the sputtering power is 0.1-10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%-5%, the gas flow rate Ar:O2 is 1:80-1:250, and water vapor is introduced to control the pressure in the reaction chamber to be 0.6-0.8 torr; The third ITO sublayer is obtained by sputtering using an ITO target, wherein the mass ratio of In2O3 and Sn is 90:10~98:2, the sputtering temperature is 180~280°C, the sputtering power is 0.1~10kW, the sputtering atmosphere is Ar / H2 mixed gas and O2, the hydrogen content in the Ar / H2 mixed gas is 1%~5%, the gas flow rate Ar:O2 is 1:150~1:350, and water vapor is introduced to control the pressure in the reaction chamber to be 0.8~1.2torr.

2. The method for manufacturing a heterojunction battery according to claim 1, characterized in that: The step of depositing IZrO on the second ITO layer by an atomic layer deposition process to form an auxiliary layer comprises: Alternately using an indium precursor and a zirconium precursor with an oxidant to react and deposit on the second ITO layer to form the auxiliary layer formed by alternately stacking indium oxide thin films and zirconium oxide thin films; Wherein, the reaction temperature for depositing the auxiliary layer is below 160°C.

3. The method for manufacturing a heterojunction battery according to claim 1, characterized in that: The step of depositing the IZrO layer and the second ITO layer by using an atomic layer deposition process comprises: Alternately using an indium precursor and a zirconium precursor with an oxidant for reaction deposition to form the IZrO layer formed by alternately stacking indium oxide thin films and zirconium oxide thin films; Alternately using an indium precursor and a tin precursor with an oxidant for reaction deposition to form the second ITO layer formed by alternately stacking indium oxide thin films and tin oxide thin films; Wherein, the reaction temperature for depositing the IZrO layer and the second ITO layer is below 160°C.

4. The method for manufacturing a heterojunction battery according to claim 1, characterized in that: The steps of texturing both sides of a silicon wafer and polishing the back side of the silicon wafer to obtain a silicon wafer layer include: Pre-cleaning the silicon wafer using a pre-cleaning solution comprising an alkaline solution and hydrogen peroxide; The front and back sides of the silicon wafer are textured with a texturing liquid, wherein the texturing liquid comprises, by volume, 2% to 8% potassium hydroxide solution, 0.2% to 2% texturing additive, and the remainder is deionized water, the texturing temperature is 70° C. to 90° C., and the texturing time is 400s to 800s; The back side of the silicon wafer is flattened by using a polishing liquid, so that the base angle of the pyramid of the velvet surface on the back side of the silicon wafer is reduced from 10° to 25°, wherein the polishing liquid contains hydrofluoric acid and nitric acid, the polishing temperature is 20°C to 50°C, and the polishing time is 45s to 150s.

5. The method for manufacturing a heterojunction battery according to claim 4, characterized in that: The texturing additive comprises, by volume, 0.05% to 2.5% potassium polyacrylate, 0.05% to 2.5% potassium sorbate, 2% to 7% polyethylene glycol, 0.05% to 2.5% potassium hydroxide, and the remainder is deionized water.

6. The method for manufacturing a heterojunction battery according to any one of claims 1 to 5, characterized in that: The method for manufacturing the heterojunction battery also includes: forming a first electrode on the first transparent conductive layer; A second electrode is formed on the second transparent conductive layer. The second electrode penetrates the auxiliary layer and protrudes from a side of the auxiliary layer away from the second transparent conductive layer.

7. A photovoltaic module, characterized in that: A heterojunction battery made by the method for making a heterojunction battery according to any one of claims 1 to 6.

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