Method for manufacturing packaging substrate

Abstract

A method for manufacturing a packaging substrate includes forming a first circuit layer and a first build-up layer circuit on the first surface and the second surface opposite to each other of a first dielectric layer, respectively, and after forming a plurality of first conductive blind holes electrically connecting the first circuit and the first build-up layer circuit from the second surface, a plurality of second conductive blind holes electrically connecting the first build-up layer circuit are formed from the first surface, thereby solving the problem that the prior art cannot meet the requirements of high-density and fine-pitch circuits.

Description

Technical Field

[0001] The invention relates to a semiconductor device, and in particular to a method for manufacturing a packaging substrate with corresponding conductive blind holes formed on two sides of a dielectric layer. Background Art

[0002] With the advancement of electronic manufacturing technology, electronic products have been developing towards being thinner, lighter and smaller in appearance, and towards high performance, high functionality and high speed in function in recent years. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] like Figure 1 As shown, the existing packaging substrate 1 includes a dielectric layer 11 having a first surface 111 and a second surface 112 opposite to each other, a first circuit layer 12 formed on the first surface 111, a second circuit layer 13 formed on the second surface 112, and a plurality of conductive blind holes 14 formed in the dielectric layer 11 and electrically connecting the first circuit layer 12 and the second circuit layer 13. Thereafter, an insulating protection layer 15 having openings for exposing portions of the first circuit layer 12 and the second circuit layer 13 may be formed on the first surface 111 and the second surface 112, respectively, and a plurality of conductive blocks 16, 16' may be formed in each of the openings, so that the chip 9 may be electrically connected to the second circuit layer 13 through the plurality of conductive blocks 16' in the openings of the insulating protection layer 15 on the second circuit layer 13, and the packaging substrate 1 may also be disposed on a printed circuit board (PCB) 8 through each of the conductive blocks 16 located on the first circuit layer 12.

[0004] However, in the conventional packaging substrate 1, a hole is formed from the first surface 111 to the second surface 112 through the dielectric layer 11, and then a conductive material is filled in the hole to form each of the conductive blind vias 14. Therefore, as shown in the figure, each of the conductive blind vias 14 is usually limited by the wider line diameter at the first surface 111, so that adjacent conductive blind vias 14 usually have to maintain a wider distance between them, and thus cannot meet the requirements of high-density and fine-pitch circuits.

[0005] Therefore, how to overcome the various problems of the above-mentioned existing manufacturing methods has become a topic that is urgently needed to be solved. Summary of the invention

[0006] In view of the various deficiencies of the above-mentioned prior art, the present invention provides a method for manufacturing a packaging substrate, comprising: forming a first circuit layer on a first metal layer; forming a first dielectric layer on the first metal layer and the first circuit layer, wherein the first dielectric layer has a first surface and a second surface opposite to each other, and the first surface contacts the first metal layer; forming a first build-up layer circuit on the second surface of the first dielectric layer, and forming a plurality of first conductive blind holes in the first dielectric layer to electrically connect the first circuit layer and the first build-up layer circuit; forming a plurality of second conductive blind holes in the first dielectric layer from the first surface to electrically connect the first build-up layer circuit; and removing the first metal layer to expose the first surface of the first dielectric layer, each of the first conductive blind holes, and each of the second conductive blind holes.

[0007] In a specific embodiment of the aforementioned method for manufacturing the package substrate, the first metal layer is bonded to a carrier plate.

[0008] In a specific embodiment of the aforementioned method for manufacturing a packaging substrate, the carrier board is a copper foil substrate.

[0009] In a specific embodiment of the aforementioned method for manufacturing the packaging substrate, the production of the first conductive blind hole includes forming a second metal layer on the second surface of the first dielectric layer; forming a plurality of first holes penetrating the first dielectric layer from the second metal layer and the second surface of the first dielectric layer by laser; and filling the plurality of first holes with conductive material to form the first conductive blind hole.

[0010] In a specific embodiment of the manufacturing method of the aforementioned packaging substrate, the formation of the first build-up layer circuit includes forming a patterned resist layer on the second metal layer after forming a plurality of first holes penetrating the first dielectric layer to expose a portion of the second metal layer and the plurality of first holes; forming the conductive material on the exposed portion of the second metal layer and filling the conductive material into the plurality of first holes to form the first build-up layer circuit, and forming the plurality of first conductive blind holes electrically connecting the first circuit layer and the first build-up layer circuit.

[0011] In a specific embodiment of the aforementioned method for manufacturing the packaging substrate, the production of the second conductive blind hole includes forming a plurality of second holes penetrating the first dielectric layer from the first surface of the first metal layer and the first dielectric layer by laser; and filling the plurality of second holes with conductive material to form the second conductive blind hole.

[0012] In a specific embodiment of the aforementioned method for manufacturing the package substrate, the first conductive blind via and the second conductive blind via exposed on the first surface of the first dielectric layer have the same line width.

[0013] In a specific embodiment of the manufacturing method of the aforementioned packaging substrate, it also includes forming a second dielectric layer on the second surface of the first dielectric layer, forming a second build-up layer circuit on the surface of the second dielectric layer, and forming a plurality of third conductive blind holes in the second dielectric layer to electrically connect the first build-up layer circuit and the second build-up layer circuit.

[0014] A specific embodiment of the manufacturing method of the aforementioned packaging substrate also includes forming an insulating protective layer on the first surface of the first dielectric layer and the surface of the second dielectric layer, respectively, wherein the insulating protective layer has a plurality of openings to expose a portion of the second build-up layer circuit and each of the first conductive blind holes and each of the second conductive blind holes.

[0015] The aforementioned method for manufacturing the packaging substrate further includes forming a conductive block in each of the openings.

[0016] As can be seen from the above, in the method for manufacturing the package substrate of the present invention, the second conductive blind via and the first conductive blind via are respectively formed on the first surface and the second surface of the first dielectric layer to achieve the purpose of improving the circuit density. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a cross-sectional schematic diagram of an existing packaging substrate.

[0018] Figures 2A to 2M It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0019] Figure 3 It is a schematic diagram of the practical application of the packaging substrate of the present invention.

[0020] Description of reference numerals:

[0021] 1,2 Package substrate

[0022] 11 Dielectric layer

[0023] 111,221 First surface

[0024] 112,222 Second surface

[0025] 12 First circuit layer

[0026] 13 Second circuit layer

[0027] 14 Conductive blind vias

[0028] 15 Insulation protective layer

[0029] 16,16' conductive block

[0030] 20 Loading plate

[0031] 200 Insulation board

[0032] 201 Copper Foil

[0033] 202 First Metal Layer

[0034] 21 First circuit layer

[0035] 22. First dielectric layer

[0036] 223 First Hole

[0037] 224 First conductive blind via

[0038] 225 Second Hole

[0039] 226 Second conductive blind via

[0040] 23 Second Metal Layer

[0041] 24 Patterned resist layer

[0042] 241 Opening

[0043] 25 The first layer of circuit

[0044] 26 Second dielectric layer

[0045] 261 The third conductive blind hole

[0046] 27 Second layer increase line

[0047] 28 Insulation protection layer

[0048] 281,281' opening

[0049] 29,29' conductive block

[0050] 8. Printed Circuit Board

[0051] 9 Chip

[0052] Φ1, Φ2 line width. DETAILED DESCRIPTION

[0053] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0054] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0055] Figures 2A to 2M It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0056] like Figure 2A As shown, a carrier board 20 is provided, wherein the carrier board can be a copper foil substrate.

[0057] Specifically, the carrier board 20 includes an insulating board 200 and copper foils 201 formed on two opposite surfaces of the insulating board 200. In addition, at least one first metal layer 202 is bonded to the copper foil 201 on at least one side of the insulating board 200.

[0058] In this embodiment, as shown in the figure, the first metal layer 202 is formed on the upper side and the lower side of the insulating plate body 200, wherein the process performed on each of the first metal layers 202 is the same, and therefore, only one side of the first metal layer 202 is used as an example for description below.

[0059] like Figure 2B As shown, a first circuit layer 21 is formed on the first metal layer 202 .

[0060] like Figure 2C As shown, a first dielectric layer 22 is formed on the first metal layer 202 and the first circuit layer 21 to cover the first metal layer 202 and the first circuit layer 21, wherein the first dielectric layer 22 has a first surface 221 and a second surface 222 opposite to each other, thereby making the first surface 221 contact the first metal layer 202, and making the first circuit layer 21 buried in the first dielectric layer 22, and making the first circuit layer 21 flush with the first surface 221 of the first dielectric layer 22, and at the same time, a portion of the first circuit layer 21 is exposed outside the first dielectric layer 22.

[0061] Then, if Figures 2C to 2FAs shown, a first build-up circuit 25 is formed on the second surface 222 of the first dielectric layer 22, and a plurality of first conductive blind vias 224 are formed in the first dielectric layer 22 to electrically connect the first circuit layer 21 and the first build-up circuit 25, as described in detail below.

[0062] like Figure 2C As shown, a second metal layer 23 is formed on the second surface 222 of the first dielectric layer 22 .

[0063] like Figure 2D As shown, a first hole 223 is formed in the second metal layer 23 and the first dielectric layer 22 to expose the first metal layer 202 and the first circuit layer 21 .

[0064] like Figure 2E As shown, after forming a plurality of first holes 223 penetrating the first dielectric layer 22 , a patterned resist layer 24 is formed on the second metal layer 23 . The patterned resist layer 24 has an opening 241 exposing the second metal layer 23 , thereby exposing a portion of the second metal layer 23 and the plurality of first holes 223 .

[0065] like Figure 2F As shown, the conductive material is formed on the exposed portion of the second metal layer 23 and the conductive material is filled into the plurality of first holes 223 to form a first build-up circuit 25 on the second metal layer 23 (eg Figure 2E ), and forming a plurality of first conductive blind holes 224 in the first dielectric layer 22 to electrically connect the first circuit layer 21 (as shown in FIG. Figure 2D ) and the first build-up circuit 25. Afterwards, the patterned resist layer 24 is removed.

[0066] In this embodiment, a first hole 223 (eg, a hole 223) penetrating the first dielectric layer 22 can be formed from the second metal layer 23 and the second surface 222 of the first dielectric layer 22 by a laser process. Figure 2D As shown), a conductive material is electroplated in the first hole 223 to form the first conductive blind hole 224.

[0067] like Figure 2G As shown, a second dielectric layer 26 is also formed on the second surface 222 of the first dielectric layer 22, and a second build-up layer circuit 27 is formed on the surface of the second dielectric layer 26. In addition, a plurality of third conductive blind holes 261 can be formed in the second dielectric layer 26 to electrically connect the first build-up layer circuit 25 and the second build-up layer circuit 27.

[0068] In other embodiments, multiple dielectric layers and build-up circuits may be omitted or added according to needs, such as a third dielectric layer and a third build-up circuit (not shown).

[0069] like Figure 2H As shown, the insulating plate 200 and the copper foil 201 are removed to expose the first metal layer 202 .

[0070] like Fig.2I As shown, a plurality of second holes 225 are opened from the first metal layer 202 and the first surface 221 of the first dielectric layer 22 to the second surface 222 .

[0071] like Figure 2J As shown, in each of the second holes 225 (such as Figure 2H , that is, a plurality of second conductive blind vias 226 are formed in the first dielectric layer 22 from the first surface 221 to electrically connect the second circuit layer 25.

[0072] In this embodiment, a reverse laser process can be used to form the second hole 225 penetrating the first dielectric layer 22 from the first metal layer 202 and the first surface 221 of the first dielectric layer 22, and a conductive material is filled in the second hole 225 to form the second conductive blind hole 226. Accordingly, the present invention further forms the second conductive blind hole 226 between two adjacent first conductive blind holes 224 by performing a reverse laser process on the first surface 221 to achieve the purpose of increasing the circuit density.

[0073] like Figure 2K As shown, the first metal layer 202 is removed to expose the first surface 221 of the first dielectric layer 22 , each of the first conductive blind vias 224 , and each of the second conductive blind vias 226 .

[0074] In one embodiment, the first conductive blind via 224 and the second conductive blind via 226 exposed on the first surface 221 of the first dielectric layer 22 have the same line width, that is, the line width Φ1 of the first conductive blind via 224 is equal to the line width Φ2 of the second conductive blind via 226. In addition, the end width of each of the second conductive blind vias 226 on the second surface 222 is thinner than the end width of the first conductive blind via 224 on the second surface 222.

[0075] like Figure 2LAs shown, an insulating protective layer 28 is formed on the first surface 221 of the first dielectric layer 22 and the surface of the second dielectric layer 26 to form the package substrate 2 of the present invention, wherein the insulating protective layer 28 on the first surface 221 has a plurality of openings 281 to expose each of the first conductive blind vias 224 and each of the second conductive blind vias 226. The insulating protective layer 28 on the surface of the second dielectric layer 26 has a plurality of openings 281' to expose the second build-up layer circuit 27. In one embodiment, the package substrate 2 of the present invention may also choose not to form the insulating protective layer 28. In addition, in a specific embodiment, the insulating protective layer 28 may be formed of a solder mask material of photosensitive polyimide (PSPI).

[0076] like Figure 2M As shown, after forming each of the openings 281 , 281 ′, a conductive block 29 , 29 ′ may be formed in each of the openings 281 , 281 ′.

[0077] like Figure 3 As shown, in actual application, the packaging substrate 2 prepared by the above process can allow the chip 9 to be set on the first surface 221 through each of the conductive blocks 29, and to be set on a printed circuit board (PCB) 8 with each of the conductive blocks 29' on the third circuit layer 27. Accordingly, since the packaging substrate 2 of the present invention provides dense circuits through each of the first conductive blind holes 224 and each of the second conductive blind holes 226, it can cope with a higher density solder ball arrangement design on the chip 9, and in combination with the use of an insulating protective layer 28 with a high-resolution opening, it can also achieve the purpose of being suitable for packaging substrate requirements such as chiplets.

[0078] In summary, after forming the first conductive blind hole from the second surface of the first dielectric layer, the present invention further opens a second hole from the first surface and forms the second conductive blind hole, thereby providing a finer circuit, so that a high-density circuit design can be formed on the die side (such as the first surface). Therefore, the present invention can form a high-density circuit through a simple process technology, thereby achieving the purpose of forming a high-density and fine-pitch circuit. In addition, the present invention forms each of the second conductive blind holes from the first surface through a reverse laser process, thereby achieving the purpose of forming a pad with a uniform size and a higher density on the die side.

[0079] The above embodiments are only used to illustrate the principles and technical effects of the present invention, and are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the concept and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A method for manufacturing a packaging substrate, comprising: forming a first circuit layer on the first metal layer; Forming a first dielectric layer on the first metal layer and the first circuit layer, wherein the first dielectric layer has a first surface and a second surface opposite to each other, and the first surface contacts the first metal layer; Forming a first build-up layer circuit on the second surface of the first dielectric layer, and forming a plurality of first conductive blind vias in the first dielectric layer to electrically connect the first circuit layer and the first build-up layer circuit; Forming a plurality of second conductive blind vias from the first surface in the first dielectric layer to electrically connect the first build-up layer circuit; and The first metal layer is removed to expose the first surface of the first dielectric layer, each of the first conductive blind vias and each of the second conductive blind vias.

2. The method for manufacturing a packaging substrate according to claim 1, wherein: The first metal layer is combined on at least one side of an insulating plate body so that the first metal layer and the insulating plate body form a supporting plate.

3. The method for manufacturing a packaging substrate according to claim 2, wherein: The carrier board is a copper foil substrate.

4. The method for manufacturing a packaging substrate according to claim 1, wherein: The production of the first conductive blind hole includes forming a second metal layer on the second surface of the first dielectric layer; forming a plurality of first holes penetrating the first dielectric layer from the second metal layer and the second surface of the first dielectric layer by laser; and filling the plurality of first holes with conductive material to form the first conductive blind hole.

5. The method for manufacturing a packaging substrate according to claim 4, wherein: The formation of the first build-up layer circuit includes forming a patterned resist layer on the second metal layer after forming a plurality of first holes penetrating the first dielectric layer to expose a portion of the second metal layer and the plurality of first holes; forming the conductive material on the exposed portion of the second metal layer and filling the conductive material into the plurality of first holes to form the first build-up layer circuit, and forming the plurality of first conductive blind holes electrically connecting the first circuit layer and the first build-up layer circuit.

6. The method for manufacturing a packaging substrate according to claim 1, wherein: The production of the second conductive blind hole includes forming a plurality of second holes penetrating the first dielectric layer from the first metal layer and the first surface of the first dielectric layer by laser; and filling the plurality of second holes with conductive material to form the second conductive blind hole.

7. The method for manufacturing a packaging substrate according to claim 1, wherein: The first conductive blind via and the second conductive blind via exposed on the first surface of the first dielectric layer have the same line width.

8. The method for manufacturing a packaging substrate according to claim 1, wherein: The method also includes forming a second dielectric layer on the second surface of the first dielectric layer, forming a second build-up layer circuit on the surface of the second dielectric layer, and forming a plurality of third conductive blind vias in the second dielectric layer to electrically connect the first build-up layer circuit and the second build-up layer circuit.

9. The method for manufacturing a packaging substrate according to claim 8, wherein: The manufacturing method also includes forming an insulating protection layer on the first surface of the first dielectric layer and the surface of the second dielectric layer, respectively, wherein the insulating protection layer has a plurality of openings to expose a portion of the second build-up layer circuit and each of the first conductive blind vias and each of the second conductive blind vias.

10. The method for manufacturing a packaging substrate according to claim 9, wherein: The manufacturing method also includes forming a conductive block in each of the openings.

Images