Isolation structure forming method, semiconductor device manufacturing method and semiconductor device

Abstract

The present application discloses a method for forming an isolation structure, a method for preparing a semiconductor device, and a semiconductor device, and relates to the field of semiconductor preparation technology. The method comprises: etching a medium-depth isolation trench on the front side of a wafer; depositing polysilicon in the medium-depth isolation trench through a furnace tube process and forming a polysilicon film layer on the back side of the wafer; removing the polysilicon film layer on the back side of the wafer; growing a silicon nitride film layer on the front and back sides of the wafer through a furnace tube process; etching a deep trench isolation trench on the front side of the wafer; and growing an oxide layer in the deep trench isolation trench. The above-mentioned technical means solve the problem of collapse of the silicon nitride film layer on the surface of the wafer in the prior art, so as to improve the performance and yield of semiconductor devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an isolation structure forming method, a semiconductor device manufacturing method and a semiconductor device. Background Art

[0002] DTI (Deep Trench Isolation) and MTI (Middle Trench Isolation) are two different technologies used to achieve electrical isolation in semiconductor devices. In the high-voltage semiconductor manufacturing process, the semiconductor device structures of DTI and MTI can effectively play the role of electrical isolation.

[0003] In the prior art, in the process of forming the DTI and MTI structures of semiconductor devices, a relatively shallow MTI structure is first formed on a wafer. In order to prevent the N-type polysilicon filled in the MTI channel from being etched during the formation of the DTI structure and from being contaminated by the P-type polysilicon filled in the DTI channel, silicon nitride is used to form a silicon nitride film layer on the MTI channel before etching the DTI channel. After the silicon nitride film layer is formed, the DTI channel is etched on the wafer and an oxide layer is grown in the DTI channel. The oxide layer grows at a temperature above 1000 degrees Celsius, and then stress release occurs in the wafer during the high-temperature generation process, resulting in the collapse of the silicon nitride film layer formed on the wafer surface, which seriously affects the performance and yield of the semiconductor device. Summary of the invention

[0004] The present application provides an isolation structure forming method, a semiconductor device manufacturing method and a semiconductor device, which solves the problem of collapse of the silicon nitride film layer on the surface of the wafer in the prior art, so as to improve the performance and yield of the semiconductor device.

[0005] In a first aspect, the present application provides a method for forming an isolation structure, comprising:

[0006] Etching a medium-depth isolation trench on the front side of the wafer;

[0007] Depositing polysilicon in the medium-depth isolation trench and forming a polysilicon film layer on the back side of the wafer by a furnace process;

[0008] removing the polysilicon film layer on the back side of the wafer;

[0009] growing silicon nitride film layers on the front and back sides of the wafer by a furnace tube process;

[0010] Etching deep trench isolation trenches on the front side of the wafer;

[0011] An oxide layer is grown in the deep trench isolation trench.

[0012] Optionally, the step of removing the polysilicon film layer on the back side of the wafer includes:

[0013] The polysilicon film layer on the back side of the wafer is removed by a mixed solution of hydrofluoric acid and nitric acid.

[0014] Optionally, the growth temperature of the silicon nitride film layer is 600° C. to 800° C.

[0015] Optionally, the medium-depth isolation trench and the deep trench isolation trench are formed by dry etching.

[0016] Optionally, the oxide layer is formed by wet oxidation.

[0017] Optionally, before etching the medium-depth isolation trench on the front side of the wafer, the method further includes:

[0018] Growing an N-type doped buried layer on the front side of the P-type substrate;

[0019] A P-type doped epitaxial layer is generated on the front side of the buried layer.

[0020] Optionally, a bottom of the medium-depth isolation trench contacts the deep buried layer.

[0021] Optionally, the bottom of the deep trench isolation trench contacts the P-type substrate.

[0022] In a second aspect, the present application provides a method for preparing a semiconductor device, including the method for forming an isolation structure as described in the first aspect.

[0023] In a third aspect, the present application provides a semiconductor device manufactured using the semiconductor device manufacturing method described in the second aspect.

[0024] In the present application, a medium-depth isolation trench is etched on the front of the wafer; polysilicon is deposited in the medium-depth isolation trench and a polysilicon film layer is formed on the back of the wafer by a furnace tube process; the polysilicon film layer on the back of the wafer is removed; a silicon nitride film layer is grown on the front and back of the wafer by a furnace tube process; a deep trench isolation trench is etched on the front of the wafer; and an oxide layer is grown in the deep trench isolation trench. Through the above-mentioned technical means, the stress of the wafer can be released by removing the polysilicon film layer on the back of the wafer. The silicon nitride film layer can be grown on the front and back of the wafer simultaneously by a furnace tube process to increase the density of the silicon nitride film layer and balance the stress distribution inside the wafer. The release and balance of wafer stress effectively reduces the influence of stress changes on the bending degree of the wafer during the subsequent high-temperature growth of the oxide layer, thereby reducing the probability of a large bending of the wafer. In addition, the increase in the density of the silicon nitride film layer can avoid the problem of the silicon nitride film layer peeling off the wafer due to wafer bending, thereby avoiding the phenomenon of silicon nitride film layer collapse, solving the problem of silicon nitride film layer collapse on the wafer surface in the prior art, and improving the performance and yield of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a flow chart of a method for forming an isolation structure provided in an embodiment of the present application;

[0026] Figure 2 It is one of the structural schematic diagrams of the wafer provided in the embodiment of the present application;

[0027] Figure 3 This is the second structural schematic diagram of the wafer provided in the embodiment of the present application;

[0028] Figure 4 This is the third structural schematic diagram of the wafer provided in the embodiment of the present application;

[0029] Figure 5 This is the fourth structural schematic diagram of the wafer provided in the embodiment of the present application;

[0030] Figure 6 This is the fifth structural schematic diagram of the wafer provided in the embodiment of the present application;

[0031] Figure 7 This is the sixth structural schematic diagram of the wafer provided in the embodiment of the present application;

[0032] Figure 8 This is the seventh structural schematic diagram of the wafer provided in the embodiment of the present application;

[0033] Fig. 9 It is a schematic diagram of the BOW value of the wafer surface in each process before and after the improvement provided in the embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical scheme and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. It is understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for the convenience of description, only part of the present application is shown in the accompanying drawings, but not all of the content. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow chart describes each operation (or step) as a sequential process, many of the operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0035] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0036] In the more common existing implementation method, in the process of forming the DTI and MTI structures of the semiconductor device, a relatively shallow MTI structure is first formed on the wafer. In order to prevent the N-type polysilicon filled in the MTI channel from being etched during the formation of the DTI structure and being contaminated by the P-type polysilicon filled in the DTI channel, a silicon nitride material is used to form a silicon nitride film layer on the MTI channel before etching the DTI channel. After the silicon nitride film layer is formed, the DTI channel is etched on the wafer and an oxide layer is grown in the DTI channel. After the oxide layer is grown at a temperature above 1000 degrees Celsius, collapse defects appear on the wafer surface. EDC elemental analysis shows that the elements of the defects on the wafer surface are mainly silicon and nitrogen. In this regard, after analysis, it was found that since the silicon nitride film layer is formed through a plasma enhanced process, the density of the silicon nitride film layer is low and the structure of the silicon nitride film layer is relatively loose. When the oxide layer is grown at a temperature above 1000 degrees Celsius, the stress of the wafer increases significantly, resulting in a large degree of bending of the wafer. The silicon nitride film layer peels off from the wafer and collapses, seriously affecting the performance and yield of semiconductor devices.

[0037] To solve the above problems, the present embodiment provides an isolation structure forming method, a semiconductor device preparation method and a semiconductor device, so as to remove the polysilicon film layer on the back of the wafer and grow a silicon nitride film layer on the front and back of the wafer through a furnace tube process, release and balance the stress of the wafer, increase the density of the silicon nitride film layer, reduce the degree of bending of the wafer and reduce the probability of cracking of the silicon nitride film layer, thereby avoiding the problem of collapse of the silicon nitride film layer and improving the performance and yield of the semiconductor device.

[0038] Figure 1 A flow chart of a method for forming an isolation structure provided in an embodiment of the present application is given. Figure 1 As shown, the isolation structure forming method includes:

[0039] S110, etching a medium-depth isolation trench on the front side of the wafer.

[0040] Among them, after the polysilicon material is filled in the medium-depth isolation trench, it becomes a medium-depth isolation structure (MTI structure). Exemplarily, a photoresist is coated on the front side of the wafer, and the photoresist is exposed through a photolithography mask with a medium-depth isolation trench pattern. The exposed photoresist is removed through a development process to leave a pattern corresponding to the medium-depth isolation trench pattern on the wafer, so as to expose the area on the front side of the wafer where the medium-depth isolation trench needs to be formed. The exposed area on the front side of the wafer is etched through an etching process to etch a medium-depth isolation trench on the front side of the wafer. Thereafter, the residual photoresist on the wafer is cleaned.

[0041] In this embodiment, the medium-depth isolation trench is formed by dry etching, that is, after exposing the area on the front side of the wafer where the medium-depth isolation trench needs to be formed, the exposed area on the front side of the wafer is etched by a dry etching process to etch a medium-depth isolation trench on the front side of the wafer.

[0042] Figure 2 This is one of the schematic diagrams of the structure of the wafer provided in the embodiment of the present application. Figure 2 As shown, after the process of etching the medium-depth isolation trench, a medium-depth isolation trench 14 is formed on the front side of the wafer.

[0043] refer to Figure 2, the wafer also includes a substrate 11, a buried layer 12 and an epitaxial layer 13. The buried layer 12 is located above the substrate 11, the epitaxial layer 13 is located in the buried layer 12, and the bottom of the medium-depth isolation trench 14 contacts the buried layer 12. In this embodiment, before etching the medium-depth isolation trench, an N-type doped buried layer may be grown on the front side of the P-type substrate; and a P-type doped epitaxial layer is generated on the front side of the buried layer. Exemplarily, N-type impurities are implanted into the P-type substrate of the wafer by an ion implantation process and annealing is performed to form an N-type buried layer. Afterwards, a P-type epitaxial layer is grown on the buried layer by a vapor phase epitaxial process such as chemical vapor deposition, molecular beam epitaxy, and the like.

[0044] After forming the epitaxial layer, a medium-depth isolation trench is etched on the front side of the epitaxial layer, wherein the medium-depth isolation trench passes through the entire epitaxial layer and contacts the deep buried layer.

[0045] In one embodiment, after etching the medium-depth isolation trench, silicon oxide material may be deposited on the front and back sides of the wafer through a furnace process, so that oxide layers are formed on both the front and back sides of the wafer. Figure 3 This is the second schematic diagram of the structure of the wafer provided in the embodiment of the present application. Figure 3 As shown, after the silicon oxide material is deposited by the furnace process, an oxide layer 15 is formed in the medium-depth isolation trench 14 and on the epitaxial layer 13 , and an oxide layer 15 is also formed on the back side of the wafer, that is, the back side of the substrate 11 .

[0046] S120, depositing polysilicon in the medium-depth isolation trench through a furnace tube process and forming a polysilicon film layer on the back side of the wafer.

[0047] Exemplarily, polysilicon material is deposited in the medium-depth isolation trench using a chemical vapor deposition process in a furnace tube. Due to the characteristics of the furnace tube process, polysilicon material is deposited on both the front and back sides of the wafer at the same time. Therefore, when polysilicon material is deposited in the medium-depth isolation trench by a chemical vapor deposition process in the furnace tube, a polysilicon film layer is simultaneously formed on the back side of the wafer. Afterwards, in order to eliminate the surface imbalance and residues generated on the front side of the wafer during the deposition process, excess polysilicon on the front side of the wafer can be removed by chemical mechanical polishing to ensure that the front side of the wafer is flat. Figure 4 This is the third schematic diagram of the structure of the wafer provided in the embodiment of the present application. Figure 4 As shown, after the polysilicon material 16 is deposited in the medium depth isolation trench 14 through the furnace process, the medium depth isolation trench 14 and the corresponding deposited polysilicon material 16 form a medium depth isolation structure. At the same time, a polysilicon film layer 17 is formed on the back side of the wafer, that is, on the back side of the oxide layer 15 on the back side of the substrate 11.

[0048] S130, clearing the polysilicon film layer on the back side of the wafer.

[0049] In this embodiment, after analysis, it is found that the problem of silicon nitride film collapse occurs in the oxide layer in the deep trench isolation trench grown at high temperature. This is because the stress of the wafer increases at high temperature, resulting in an increase in the degree of curvature of the wafer, which causes the silicon nitride film to peel off the wafer. The silicon nitride film breaks due to excessive force during the peeling process, and then collapses on the wafer. In this regard, in order to reduce the increased stress of the wafer during the high-temperature growth of the oxide layer, the polysilicon film layer deposited on the back of the wafer can be removed before the growth of the silicon nitride film layer to release the stress of the wafer in advance. After releasing the stress of the wafer, the increased stress of the wafer during the high-temperature growth of the oxide layer can be effectively reduced, thereby reducing the degree of curvature of the wafer, thereby reducing the probability of the silicon nitride film peeling off the wafer.

[0050] In this embodiment, the polysilicon film layer on the back of the wafer can be removed by a mixed solution of hydrofluoric acid and nitric acid. Exemplarily, the volume ratio of the mixed solution is 1:50, the mass fraction of hydrofluoric acid is 49%, and the mass fraction of nitric acid is 60%. The mixed solution of hydrofluoric acid and nitric acid can achieve an etching rate of 800A / sec for the polysilicon film layer. The etching time can be set according to the etching rate and the thickness of the polysilicon film layer, so as to etch the polysilicon film layer on the back of the wafer cleanly by the etching time. After using the mixed solution of hydrofluoric acid and nitric acid to clean and remove the polysilicon film layer on the back of the wafer, the residual etching solution on the wafer can be cleaned with deionized water.

[0051] Figure 5 This is the fourth structural diagram of the wafer provided in the embodiment of the present application. Figure 5 As shown, after etching the polysilicon film layer 17, the polysilicon film layer 17 on the back side of the wafer is etched cleanly, and the oxide layer 15 is retained on the back side of the wafer.

[0052] S140, growing a silicon nitride film layer on the front and back sides of the wafer through a furnace tube process.

[0053] Exemplarily, a silicon nitride material is deposited on the front side of the wafer using a chemical vapor deposition process in a furnace tube to grow a silicon nitride film layer (FUR-SIN) on the front side of the wafer. Due to the characteristics of the furnace tube process, silicon nitride material is deposited on both the front and back sides of the wafer at the same time. Therefore, when silicon nitride material is deposited on the front side of the wafer by a chemical vapor deposition process in the furnace tube, a silicon nitride film layer is simultaneously formed on the back side of the wafer. Figure 6 This is the fifth structural diagram of the wafer provided in the embodiment of the present application. Figure 6 As shown, after silicon nitride material is deposited on the front and back sides of the wafer through a furnace process, a silicon nitride film layer 18 is formed on the oxide layer 15 on the front side of the wafer and the medium-depth isolation structure, and a silicon nitride film layer 18 is also formed on the oxide layer 15 on the back side of the wafer.

[0054] It should be noted that the existing method of growing silicon nitride film layers is generated by a plasma enhanced process (PE-SIN). The growth temperature of the silicon nitride film layer in the plasma enhanced process is 400°C, while the growth temperature of the silicon nitride film layer in the furnace tube process is 600°C~800°C. Compared with the plasma enhanced process, the density of the silicon nitride film layer formed by the furnace tube process is higher, and the furnace tube process can grow a denser silicon nitride film layer. In the subsequent high-temperature growth of the oxide layer, the silicon nitride film layer is not easy to be peeled off from the wafer due to the bending of the wafer, and the probability of the silicon nitride film layer breaking is also low, which can effectively avoid the collapse of the silicon nitride film layer due to peeling and breaking. Moreover, the furnace tube process can grow silicon nitride film layers on the front and back of the wafer at the same time, balancing the stress of the wafer, which is conducive to reducing the increased stress of the wafer during the high-temperature growth of the oxide layer, thereby reducing the degree of bending of the wafer and avoiding the peeling of the silicon nitride film layer on the front of the wafer.

[0055] S150, etching a deep trench isolation trench on the front side of the wafer.

[0056] Among them, after the oxide layer is grown in the deep trench isolation channel, it is a deep trench isolation structure (DTI structure). Exemplarily, a photoresist is coated on the front side of the wafer, and the photoresist is exposed through a photolithography mask with a deep trench isolation channel pattern. The exposed photoresist is removed through a development process to leave a pattern corresponding to the deep trench isolation channel pattern on the wafer, so as to expose the area on the front side of the wafer where the deep trench isolation channel needs to be formed. The exposed area on the front side of the wafer is etched through an etching process to etch a deep trench isolation channel on the front side of the wafer. Thereafter, the residual photoresist on the wafer is cleaned.

[0057] In this embodiment, the deep trench isolation channel is formed by dry etching, that is, after exposing the area on the front side of the wafer where the deep trench isolation channel needs to be formed, the exposed area on the front side of the wafer is etched by a dry etching process to etch a deep trench isolation channel on the front side of the wafer.

[0058] Figure 7 This is the sixth structural diagram of the wafer provided in the embodiment of the present application. Figure 7 As shown, after the deep trench isolation trench etching process, a deep trench isolation trench 19 is formed on the front side of the wafer, and the bottom of the deep trench isolation trench 19 contacts the substrate 11, that is, the deep trench isolation trench 19 passes through the silicon nitride film layer 18, the oxide layer 15, the epitaxial layer 13, the buried layer 12 and contacts the substrate 11.

[0059] S160, growing an oxide layer in the deep trench isolation trench.

[0060] For example, Figure 8 This is the seventh structural diagram of the wafer provided in the embodiment of the present application. Figure 8As shown, after the process of growing the oxide layer, an oxide layer 15 is formed on the inner wall of the deep trench isolation trench 19 , and the oxide layer 15 in the deep trench isolation trench 19 is connected to the oxide layer 15 under the silicon nitride film layer 18 .

[0061] In this embodiment, the oxide layer in the deep trench isolation trench is formed by wet oxidation, that is, the oxide layer is grown in the deep trench isolation trench by a wet oxidation process at a temperature above 1000° C. Although the growth temperature of the oxide layer is as high as 1000° C., after the previous operation of removing the polysilicon film layer on the back of the wafer and depositing the silicon nitride film layer on both sides of the wafer by the furnace tube process, the stress of the wafer will not increase significantly, and the wafer will not bend significantly, thereby avoiding the problem of peeling of the silicon nitride film layer and reducing the probability of collapse of the silicon nitride film layer.

[0062] In one embodiment, Fig. 9 Schematic diagram of the BOW value of the wafer surface in each process before and after the improvement provided in the embodiment of the present application. Among them, the process before the improvement does not remove the polysilicon film layer on the back of the wafer and forms a silicon nitride film layer through a plasma enhanced process; the process after the improvement removes the polysilicon film layer on the back of the wafer and forms a silicon nitride film layer on both sides of the wafer through a furnace tube process. Fig. 9As shown, PE-SIN is a process for growing silicon nitride film layers by plasma enhanced process, so the upper curve BSL represents the BOW (bending degree) value at each position of the wafer surface in the X direction in each process before improvement. FUR-SIN refers to a process for growing silicon nitride film layers by chemical vapor deposition process in a furnace tube, so the lower curve BSL represents the BOW value at each position of the wafer surface in the Y direction in each process before improvement. The upper curve CIP represents the BOW (bending degree) value at each position of the wafer surface in the X direction in each process after improvement, and the lower curve CIP represents the BOW value at each position of the wafer surface in the Y direction in each process after improvement. In the processes of MTI-POLYDEP (process for depositing polysilicon material in medium-depth isolation trenches) and MTI-SIN DEP (process for forming silicon nitride film layers), there is no difference in the BOW value of the wafer surface before and after the improvement, while in DTI-ET (process for etching deep trench isolation trenches) and DTI-LINER OX (process for forming oxide layers in deep trench isolation trenches), the BOW value of the wafer surface before the improvement increased, while the BOW value of the wafer surface after the improvement decreased. Finally, the height of the wafer surface before the improvement increased by about 90um in the X direction, while the height of the wafer surface after the improvement was released by about 20um in the X direction, and the height of the wafer surface before the improvement was released by about 60um in the Y direction. It can be seen that removing the polysilicon film layer on the back of the wafer and forming a silicon nitride film layer on both sides of the wafer through a furnace tube process can effectively reduce the degree of bending of the wafer during the high-temperature growth of the oxide layer in the deep trench isolation trench, thereby avoiding the silicon nitride film layer from peeling off the wafer and preventing the silicon nitride film layer from collapsing.

[0063] On the basis of the above embodiments, the embodiments of the present application also provide a method for preparing a semiconductor device and a semiconductor device prepared by the method for preparing a semiconductor device, wherein the method for preparing a semiconductor device includes the isolation structure forming method described in the above embodiments. In the process of preparing a semiconductor device, the isolation structure forming method provided in the above embodiments is used to remove the polysilicon film layer on the back of the wafer and grow a silicon nitride film layer on the front and back of the wafer through a furnace tube process, thereby releasing and balancing the stress of the wafer, increasing the density of the silicon nitride film layer, reducing the degree of curvature of the wafer and reducing the probability of the silicon nitride film layer breaking, thereby avoiding the problem of silicon nitride film layer collapse and improving the performance and yield of the semiconductor device.

[0064] In summary, the isolation structure formation method, semiconductor device preparation method and semiconductor device provided in the embodiments of the present application are achieved by etching a medium-depth isolation trench on the front of the wafer; depositing polysilicon in the medium-depth isolation trench and forming a polysilicon film layer on the back of the wafer through a furnace tube process; removing the polysilicon film layer on the back of the wafer; growing a silicon nitride film layer on the front and back of the wafer through a furnace tube process; etching a deep trench isolation trench on the front of the wafer; and growing an oxide layer in the deep trench isolation trench. Through the above-mentioned technical means, the stress of the wafer can be released by removing the polysilicon film layer on the back of the wafer. The silicon nitride film layer can be grown simultaneously on the front and back of the wafer through a furnace tube process to increase the density of the silicon nitride film layer and balance the stress distribution inside the wafer. The release and balance of wafer stress effectively reduces the influence of stress changes on the bending degree of the wafer during the subsequent high-temperature growth of the oxide layer, thereby reducing the probability of a large bending of the wafer. In addition, the increase in the density of the silicon nitride film layer can avoid the problem of the silicon nitride film layer peeling off the wafer due to wafer bending, thereby avoiding the phenomenon of silicon nitride film layer collapse, solving the problem of silicon nitride film layer collapse on the wafer surface in the prior art, and improving the performance and yield of semiconductor devices.

[0065] The above are only preferred embodiments of the present application and the technical principles used. The present application is not limited to the specific embodiments herein, and various obvious changes, readjustments and substitutions that can be made by those skilled in the art will not deviate from the protection scope of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A method for forming an isolation structure, characterized in that: include: Etching a medium-depth isolation trench on the front side of the wafer; wherein the wafer further comprises a substrate, a buried layer and an epitaxial layer, the buried layer is located above the substrate, the epitaxial layer is located above the buried layer, and the bottom of the medium-depth isolation trench contacts the buried layer; Depositing silicon oxide material on the front and back sides of the wafer by a furnace process so as to form an oxide layer on both the front and back sides of the wafer; Depositing polysilicon in the medium-depth isolation trench and forming a polysilicon film layer on the back side of the wafer by a furnace process; removing the polysilicon film layer on the back side of the wafer; growing silicon nitride film layers on the front and back sides of the wafer by a furnace tube process; Etching a deep trench isolation channel on the front side of the wafer; wherein the deep trench isolation channel passes through the silicon nitride film layer, the oxide layer, the epitaxial layer and the buried layer and contacts the substrate; An oxide layer is grown in the deep trench isolation trench.

2. The method for forming an isolation structure according to claim 1, wherein: The step of removing the polysilicon film layer on the back side of the wafer comprises: The polysilicon film layer on the back side of the wafer is removed by a mixed solution of hydrofluoric acid and nitric acid.

3. The method for forming an isolation structure according to claim 1, wherein: The growth temperature of the silicon nitride film layer is 600°C to 800°C.

4. The method for forming an isolation structure according to claim 1, wherein: The medium depth isolation trench and the deep trench isolation trench are formed by dry etching.

5. The method for forming an isolation structure according to claim 1, wherein: The oxide layer is formed by wet oxidation.

6. The method for forming an isolation structure according to claim 1, wherein: Before etching the medium-depth isolation trench on the front side of the wafer, the method further includes: Growing an N-type doped buried layer on the front side of the P-type substrate; A P-type doped epitaxial layer is generated on the front side of the buried layer.

7. The method for forming an isolation structure according to claim 6, wherein: The bottom of the deep trench isolation trench contacts the P-type substrate.

8. A method for preparing a semiconductor device, characterized in that: The method comprises the isolation structure forming method as described in any one of claims 1 to 7.

9. A semiconductor device, characterized in that: The semiconductor device is prepared using the method for preparing the semiconductor device as claimed in claim 8.

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