Accelerator device and implementation method thereof, electronic device and storage medium

Abstract

The present invention provides an accelerator device and an implementation method thereof, an electronic device and a storage medium, and relates to the technical field of accelerators. The static area of ​​the accelerator device includes a physical function, multiple virtual functions, a virtual function status information table, an acceleration unit status information table, a mapping table and an acceleration unit configuration table; the dynamic area includes multiple acceleration units; the virtual function status information table stores the status information of each virtual function; the acceleration unit status information table stores the status information of each acceleration unit; the physical function is used to configure the mapping table to store the mapping relationship between the target virtual function and the multiple target acceleration units based on the virtual function status information table and the acceleration unit status information table, and configure the acceleration unit configuration table to store the information of each target acceleration unit; the target virtual function is allocated to the target virtual machine, which can improve the flexibility of the accelerator device architecture, support binding of one virtual function with multiple acceleration units, thereby improving the acceleration efficiency and acceleration effect.

Description

Technical Field

[0001] The present invention relates to the field of accelerator technology, and in particular to an accelerator device and an implementation method thereof, an electronic device and a storage medium. Background Art

[0002] Currently, if Figure 1 As shown in the figure, the overall architecture of the accelerator device is divided into a static area and a dynamic area. The dynamic area includes multiple acceleration units, which can realize functions such as compression, encryption, and decryption. The static area creates a physical function (PF) and multiple virtual functions (VF) through the single root I / O virtualization (SR-IOV) technology, and adds a mapping module to realize the dynamic combination of VF and acceleration units with different functions. In the current architecture, there is a one-to-one correspondence between the acceleration unit and the VF, that is, a VF can only be bound to one acceleration unit.

[0003] However, since the current architecture is not flexible enough, the acceleration efficiency is extremely poor and the acceleration effect is not obvious. Summary of the invention

[0004] The present invention provides an accelerator device and an implementation method thereof, an electronic device and a storage medium, so as to achieve the purpose of improving the flexibility of the accelerator device architecture, supporting the binding of a virtual function with multiple acceleration units, thereby improving the acceleration efficiency and acceleration effect.

[0005] The present invention provides an accelerator device, comprising: a static area and a dynamic area;

[0006] The static area includes a physical function, a plurality of virtual functions, a virtual function status information table, an acceleration unit status information table, a mapping table and an acceleration unit configuration table;

[0007] The dynamic region includes a plurality of acceleration units;

[0008] The virtual function status information table is used to store status information of each virtual function;

[0009] The acceleration unit status information table is used to store the status information of each acceleration unit;

[0010] The physical function is used to configure the mapping table to store the mapping relationship between the target virtual function and multiple target acceleration units, and configure the acceleration unit configuration table to store information of each of the target acceleration units based on the virtual function status information table and the acceleration unit status information table; and allocate the target virtual function to the target virtual machine.

[0011] According to an accelerator device provided by the present invention, the virtual function status information table includes: an identification number of each virtual function, a number of interrupts supported, a register access space size, and a binding status with an acceleration unit;

[0012] The acceleration unit status information table includes: the index number of each acceleration unit, the function identification number, the size of the space occupied by the register, the number of interrupts, and the binding status with the virtual function.

[0013] According to an accelerator device provided by the present invention, the mapping table includes: a basic information area and a plurality of acceleration unit information areas;

[0014] The basic information area includes: the identification number of the target virtual function, the starting address and length of the accessible memory storage space, and the number of bound target acceleration units;

[0015] The acceleration unit information area includes: the index number of the target acceleration unit, the function identification number, the starting address and the ending address of the register space in the register access space of the target virtual function, the number of interrupts, and the interrupt number of the starting interrupt in the interrupt space of the target virtual function;

[0016] The acceleration unit configuration table includes: the index number of each target acceleration unit, the identification number of the target virtual function, the starting address of the register in the register access space of the target virtual function, the starting address and ending address of the accessible memory storage space, and the interrupt number of the starting interrupt in the interrupt space of the target virtual function.

[0017] According to an accelerator device provided by the present invention, each of the acceleration units includes a register access interface;

[0018] The static area also includes:

[0019] A register access routing module, connected to each of the virtual functions and the register access arbitration module, for responding to a read or write request transmitted through the target virtual function, and transmitting a first request carrying an index number of the target acceleration unit requested to be accessed and an address of a target register to the register access arbitration module;

[0020] The register access arbitration module is connected to each of the register access interfaces, and is used to arbitrate and release the first request, and transmit the address of the target register to the target acceleration unit through the register access interface of the target acceleration unit for read and write operations.

[0021] According to an accelerator device provided by the present invention, the register access routing module is specifically used to: obtain the identification number and register address of the target virtual function in the read and write request; query the content of the target virtual function from the mapping table based on the identification number of the target virtual function, and determine the index number of the target acceleration unit requested to be accessed based on the register address and the content of the target virtual function; determine the address of the target register based on the register address.

[0022] According to an accelerator device provided by the present invention, the content of the target virtual function includes a start address and an end address of a register space of each target acceleration unit bound to the target virtual function within a register access space of the target virtual function;

[0023] The register access routing module is specifically used to: determine the register interval of each target acceleration unit based on the starting address and the ending address of the register of each target acceleration unit in the register access space of the target virtual function; for each target acceleration unit, when the register address falls within the register interval of the target acceleration unit, determine that the target acceleration unit is the target acceleration unit requested to be accessed.

[0024] According to an accelerator device provided by the present invention, for a read request, the target acceleration unit is specifically used to: query the identification number of the bound target virtual function from the acceleration unit configuration table based on the index number of the target acceleration unit; read the first data from the address of the target register, and pass the second request carrying the first data and the identification number of the target virtual function to the register access routing module through the register access interface and the register access arbitration module;

[0025] The register access routing module is further used to: respond to the second request and return the first data to the target virtual machine through the target virtual function.

[0026] According to an accelerator device provided by the present invention, for a write request, the register access arbitration module is further used to: transmit the second data carried in the first request to the target acceleration unit through the register access interface of the target acceleration unit;

[0027] The target acceleration unit is specifically used to write the second data into the target register through the address of the target register.

[0028] According to an accelerator device provided by the present invention, the register address is an address obtained by adding a target start address and a target offset address;

[0029] The target start address is a start address of the target register of the target acceleration unit requested to be accessed within the register access space of the target virtual function, determined based on the read-only base address register space of the target virtual function;

[0030] The target offset address is an offset address of the target register relative to the target acceleration unit.

[0031] According to an accelerator device provided by the present invention, the address of the target register is an address obtained by subtracting the target start address from the register address.

[0032] According to an accelerator device provided by the present invention, each of the acceleration units includes an interrupt interface;

[0033] The static area also includes:

[0034] An interrupt interface arbitration module, which is connected to each of the interrupt interfaces and the interrupt routing module respectively, and is used to respond to the interrupt request transmitted by the target acceleration unit through the interrupt interface, arbitrate and release the interrupt request, and transmit the interrupt request to the interrupt routing module;

[0035] The interrupt routing module is connected to each of the virtual functions and is used to respond to the interrupt request and transmit the third request carrying the target interrupt number to the target virtual function;

[0036] The target virtual function is specifically configured to: respond to the third request and trigger an interrupt with the target interrupt number to the target virtual machine.

[0037] According to an accelerator device provided by the present invention, the interrupt routing module is specifically used to: obtain the index number of the target acceleration unit and the first interrupt number of the target acceleration unit carried in the interrupt request, query the identification number of the target virtual function bound to the target acceleration unit and the second interrupt number of the start interrupt of the target acceleration unit in the interrupt space of the target virtual function from the acceleration unit configuration table based on the index number of the target acceleration unit; add the second interrupt number and the first interrupt number to obtain the target interrupt number.

[0038] According to an accelerator device provided by the present invention, the target virtual function is specifically used to: respond to a memory application request sent by the target virtual machine, and return a target start address and a target address length to the target virtual machine;

[0039] The static area also includes:

[0040] a memory data transfer module, which is connected to each of the virtual functions and is used to respond to a memory data transfer request transmitted by the target virtual machine through the target virtual function, and query from the acceleration unit configuration table based on the identification number of the target virtual function in the memory data transfer request whether the target start address and the target address length in the memory data transfer request are within the memory storage space accessible to the target virtual function; if so, write the third data in the memory data transfer request into the memory storage space corresponding to the target start address and the target address length, otherwise report an exception;

[0041] The target virtual function is also used to write the target start address and the target address length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface.

[0042] According to an accelerator device provided by the present invention, each of the acceleration units includes a memory access interface;

[0043] The target virtual function is specifically used to: write the target start address and the target address length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface;

[0044] The target acceleration unit is specifically used to: read the target start address and the target address length from the address register, and initiate a memory access request carrying the index number of the target acceleration unit, the target start address and the target address length to the memory access arbitration module through the memory access interface;

[0045] The static area also includes:

[0046] The memory access arbitration module is connected to each of the memory access interfaces and the memory access module, and is used to arbitrate and release the memory access request, and transmit the memory access request to the memory access module;

[0047] The memory access module is used to respond to the memory access request and query from the acceleration unit configuration table whether the target starting address and the target address length are within the memory storage space accessible to the target virtual function based on the index number of the target acceleration unit; if so, write the data in the memory storage space corresponding to the target starting address and the target address length into the acceleration unit, otherwise report an exception.

[0048] According to an accelerator device provided by the present invention, the physical function is also used to: after configuring the mapping table and the acceleration unit configuration table, set the binding status of the target virtual function and the acceleration unit in the virtual function status information table to a valid identifier, and set the binding status of each target acceleration unit and the virtual function in the acceleration unit status information table to a valid identifier.

[0049] According to an accelerator device provided by the present invention, the physical function is also used for: after the target virtual machine is shut down and the target virtual function is released, setting the binding status of the target virtual function and the acceleration unit in the virtual function status information table to an invalid mark; based on the identification number of the target virtual function, querying the index number of each target acceleration unit bound to the target virtual function from the mapping table; setting the binding status of each target acceleration unit and the virtual function in the acceleration unit status information table to an invalid mark; deleting the information of each target acceleration unit in the acceleration unit configuration table; deleting the information of the target virtual function in the mapping table.

[0050] The present invention also provides a method for implementing the accelerator device as described in any one of the above, comprising:

[0051] Obtaining a virtual function status information table and an acceleration unit status information table through a physical function; the virtual function status information table is used to store status information of each virtual function; the acceleration unit status information table is used to store status information of each acceleration unit;

[0052] Based on the virtual function status information table and the acceleration unit status information table, a mapping table is configured to store mapping relationships between target virtual functions and multiple target acceleration units, and an acceleration unit configuration table is configured to store information of each of the target acceleration units;

[0053] The target virtual function is allocated to a target virtual machine.

[0054] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the implementation method of the accelerator device as described above when executing the computer program.

[0055] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the implementation method of the accelerator device as described above is implemented.

[0056] The present invention also provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, the implementation method of the accelerator device as described above is implemented.

[0057] The accelerator device and its implementation method, electronic device and storage medium provided by the present invention, the accelerator device includes: a static area and a dynamic area; wherein the static area includes a physical function and a plurality of virtual functions, and adds a virtual function status information table, an acceleration unit status information table, a mapping table and an acceleration unit configuration table; the dynamic area includes a plurality of acceleration units; since the virtual function status information table is used to store the status information of each virtual function, and the acceleration unit status information table is used to store the status information of each acceleration unit, the physical function can be based on the virtual function status information table and the acceleration unit status information table, the mapping table is configured to store the mapping relationship between the target virtual function and the plurality of target acceleration units, and the acceleration unit configuration table is configured to store the information of each target acceleration unit; then the target virtual function is assigned to the target virtual machine. In this way, a single target virtual function assigned to the target virtual machine at the user end can be bound to a plurality of target acceleration units. Therefore, the present invention can improve the flexibility of the accelerator device architecture, support the binding of a virtual function to a plurality of acceleration units, thereby improving the acceleration efficiency and the acceleration effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0059] Figure 1 It is a schematic diagram of the architecture of an accelerator device provided by the related technology.

[0060] Figure 2 It is a schematic diagram of the architecture of an accelerator device provided in an embodiment of the present invention.

[0061] Figure 3 It is a flowchart of a method for implementing an accelerator device provided in an embodiment of the present invention.

[0062] Figure 4 It is a schematic diagram of a register access process provided by an embodiment of the present invention.

[0063] Figure 5 It is a schematic diagram of an interruption process provided by an embodiment of the present invention.

[0064] Figure 6 This is one of the schematic diagrams of the memory storage space access process provided by an embodiment of the present invention.

[0065] Figure 7 This is the second schematic diagram of the memory storage space access process provided by the embodiment of the present invention.

[0066] Figure 8It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] Accelerator devices are used to accelerate a variety of applications. To support a single accelerator device to be shared by multiple virtual machines and ensure high performance, SR-IOV technology is usually used to create a PF and multiple VFs for a single accelerator device. Multiple VFs are independent of each other and can be assigned to different virtual machines.

[0069] Currently, if Figure 1 As shown in the figure, the overall architecture of the accelerator device is divided into a static area and a dynamic area. The dynamic area includes multiple acceleration units, which can realize functions such as compression, encryption, and decryption. The static area uses SR-IOV technology to create PF and multiple VFs, and adds a mapping module to realize the dynamic combination of VF and acceleration units with different functions. In the current architecture, there is a one-to-one correspondence between the acceleration unit and the VF, that is, one VF can only be bound to one acceleration unit.

[0070] However, the current architecture is not flexible enough and does not support binding VF to multiple acceleration units. When a user needs two acceleration functions (such as video encoding and encryption), the current architecture can only arrange two VFs for the user. From the user's perspective, the two VFs are independent and have their own accessible memory storage space, and the two VFs cannot see each other's accessible memory storage space. If two VFs need to process data collaboratively, even if the data is in the same accessible memory storage space, it needs to be read from the accessible memory storage space of one VF to the host side, and then written from the host side to the accessible memory storage space of another VF. This will cause extremely poor acceleration efficiency and unclear acceleration effect.

[0071] In order to solve the above technical problems, an embodiment of the present invention provides an accelerator device and an implementation method thereof, an electronic device and a storage medium, which are described in detail below.

[0072] First, combine the following Figure 2 An accelerator device of the present invention is described.

[0073] Please refer to Figure 2 , Figure 2Schematic diagram of the architecture of the accelerator device provided by the embodiment of the present invention. Figure 2 As shown, the accelerator device may include: a static area and a dynamic area.

[0074] Optionally, the accelerator device is an accelerator device based on a Field Programmable Gate Array (FPGA).

[0075] The static area includes a physical function (PF), multiple virtual functions (VFs), a virtual function status information table, an acceleration unit status information table, a mapping table, and an acceleration unit configuration table.

[0076] The dynamic region includes a plurality of acceleration units.

[0077] The virtual function status information table is used to store the status information of each virtual function.

[0078] Optionally, the virtual function status information table includes: an identification number of each virtual function, a number of interrupts supported, a register access space size, and a binding status with an acceleration unit.

[0079] The virtual function status information table may be as shown in Table 1.

[0080] Table 1 Virtual function status information table

[0081]

[0082] Among them, 1) the identification number of the virtual function is used to identify the corresponding virtual function.

[0083] 2) The number of interrupts supported, that is, the number of MSI-X (Message Signaled InterruptseXtended, an extended interrupt mechanism) interrupts supported by the virtual function. The interrupt type supported by the virtual function is MSI-X.

[0084] 3) The size of the register access space, that is, the size of the register access space contained in the virtual function, shall not be less than the sum of the spaces occupied by all acceleration unit registers contained in the virtual function.

[0085] 4) Binding status with the acceleration unit, 0 is an invalid flag, indicating an unbound state; 1 is a valid flag, indicating a bound state.

[0086] The acceleration unit status information table is used to store the status information of each acceleration unit.

[0087] Optionally, the acceleration unit status information table includes: the index number of each acceleration unit, the function identification number, the size of the space occupied by the register, the number of interrupts, and the binding status with the virtual function.

[0088] The acceleration unit status information table may be as shown in Table 2.

[0089] Table 2 Acceleration unit status information table

[0090]

[0091] Among them, 1) the index number of the acceleration unit is used to identify the number of the acceleration unit in the dynamic area.

[0092] 2) Function identification number of the acceleration unit, which is used to identify the function of the acceleration unit and adopts the format of Universally Unique Identifier (UUID).

[0093] 3) The size of the space occupied by the register, that is, the size of the register access space contained in the acceleration unit.

[0094] 4) The number of interrupts, that is, the number of interrupts required by the acceleration unit.

[0095] 5) Binding status with the virtual function. 0 is an invalid flag, indicating an unbound state; 1 is a valid flag, indicating a bound state.

[0096] Since different accelerator devices have different acceleration unit states and virtual function states, it is necessary to find an accelerator device that meets the user's acceleration function requirements.

[0097] Specifically, the data center receives a user acceleration function requirement issued by the user through the target virtual machine, such as requiring the accelerator device to include function A and function B. Then, the data center traverses the acceleration unit status information table and the virtual function status information table of multiple accelerator devices to find an accelerator device that meets the user acceleration function requirement.

[0098] First, the data center queries the acceleration unit status information table of the first accelerator device to determine whether the accelerator device contains function A and function B, and whether both function A and function B are in an unbound state. If not, the accelerator device does not meet the user's acceleration function requirements, and queries the next accelerator device. If yes, proceed to the next step.

[0099] Then, the data center queries the virtual function status information table of the accelerator device to determine whether there is a virtual function state in the accelerator device that can accommodate all the required acceleration units, that is, whether the following conditions are met: 1) The virtual function has not been bound to the acceleration unit; 2) The register access space contained in the virtual function is not less than the sum of the register spaces of all acceleration units; 3) The number of MSI-X interrupts supported by the virtual function is not less than the sum of the number of interrupts of all acceleration units. If all are met, the acceleration device meets the user's acceleration function requirements. Otherwise, the acceleration device does not meet the user's acceleration function requirements, and the next acceleration device is queried until an accelerator device that meets the user's acceleration function requirements is found.

[0100] After finding an accelerator device that meets the user's acceleration function requirements, the physical function is used to configure the mapping table to store the mapping relationship between the target virtual function and multiple target acceleration units based on the virtual function status information table and the acceleration unit status information table, and configure the acceleration unit configuration table to store the information of each target acceleration unit.

[0101] Optionally, the mapping table includes: a basic information area and a plurality of acceleration unit information areas;

[0102] The basic information area includes: the identification number of the target virtual function, the starting address and length of the accessible memory storage space, and the number of bound target acceleration units;

[0103] The acceleration unit information area includes: the index number of the target acceleration unit, the function identification number, the starting address and ending address of the register space in the register access space of the target virtual function, the number of interrupts, and the interrupt number of the starting interrupt in the interrupt space of the target virtual function.

[0104] The mapping table may be as shown in Table 3.

[0105] Table 3 Mapping table

[0106]

[0107] Among them, 1) basic information area, vf_index, represents the identification number of the target virtual function; ddr_start and ddr_length, respectively represent the starting address and length of the memory storage space accessible to the target virtual function; num_afu, represents the number of target acceleration units bound to the target virtual function.

[0108] 2) Acceleration unit information area, afu_index, represents the index number of the target acceleration unit, which is used to identify the number of the acceleration unit in the dynamic area; afu_id, represents the function identification number of the target acceleration unit, which is used to identify the function of the acceleration unit and adopts the UUID format; reg_start and reg_end, respectively represent the starting address and ending address of the register space of the target acceleration unit in the register access space of the target virtual function; msix_count, represents the number of interrupts of the target acceleration unit; msix_index, represents the interrupt number of the starting interrupt of the target acceleration unit in the interrupt space of the target virtual function, and the interrupt numbers are continuous.

[0109] The acceleration unit configuration table includes: the index number of each target acceleration unit, the identification number of the target virtual function, the starting address of the register in the register access space of the target virtual function, the starting address and ending address of the accessible memory storage space, and the interrupt number of the starting interrupt in the interrupt space of the target virtual function.

[0110] The acceleration unit configuration table may be shown in Table 4.

[0111] Table 4 Acceleration unit configuration table

[0112]

[0113] Among them, 1) afu_index represents the index number of the target acceleration unit, which is used to identify the number of the acceleration unit in the dynamic area.

[0114] 2) vf_index, which indicates the identification number of the target virtual function to which the target acceleration unit is bound.

[0115] 3) reg_start, which indicates the starting address of the register of the target acceleration unit in the register access space of the target virtual function.

[0116] 4) ddr_start and ddr_end, respectively, represent the starting address and ending address of the memory storage space accessible to the target acceleration unit.

[0117] 5) msix_index, which indicates the interrupt number of the starting interrupt of the target acceleration unit in the interrupt space of the target virtual function.

[0118] After configuring the mapping table and the acceleration unit configuration table, a target virtual function can be bound to multiple target acceleration units, and then the target virtual function is allocated to the user's target virtual machine and delivered to the user for use.

[0119] The accelerator device provided by the embodiment of the present invention includes: a static area and a dynamic area; wherein the static area includes a physical function and a plurality of virtual functions, and adds a virtual function status information table, an acceleration unit status information table, a mapping table and an acceleration unit configuration table; the dynamic area includes a plurality of acceleration units; since the virtual function status information table is used to store the status information of each virtual function, and the acceleration unit status information table is used to store the status information of each acceleration unit, the physical function can be based on the virtual function status information table and the acceleration unit status information table, the mapping table is configured to store the mapping relationship between the target virtual function and the plurality of target acceleration units, and the acceleration unit configuration table is configured to store the information of each target acceleration unit; and then the target virtual function is assigned to the target virtual machine. In this way, a single target virtual function assigned to the target virtual machine at the user end can be bound to a plurality of target acceleration units. Therefore, the embodiment of the present invention can improve the flexibility of the accelerator device architecture, support the binding of a virtual function to a plurality of acceleration units, thereby improving the acceleration efficiency and the acceleration effect.

[0120] In one embodiment, if Figure 2 As shown, each acceleration unit includes a register access interface;

[0121] The static area also includes:

[0122] A register access routing module, which is connected to each virtual function and the register access arbitration module, and is used to respond to the read and write requests transmitted through the target virtual function, and transmit the first request carrying the index number of the target acceleration unit requested to be accessed and the address of the target register to the register access arbitration module;

[0123] The register access arbitration module is connected to each register access interface and is used to arbitrate and release the first request, and transmit the address of the target register to the target acceleration unit through the register access interface of the target acceleration unit for read and write operations.

[0124] Specifically, the user sends a read / write request to the target virtual function through the target virtual machine, and the target virtual function passes the read / write request to the register access routing module. The register access routing module responds to the read / write request and passes the first request carrying the index number of the target acceleration unit requested to be accessed and the address of the target register to the register access arbitration module. The register access arbitration module queues multiple requests, arbitrates and releases the first request when the first request is queued, and passes the address of the target register to the target acceleration unit through the register access interface of the target acceleration unit for read / write operations, thereby achieving the purpose of the target virtual function accessing the register of a certain target acceleration unit.

[0125] Based on the above embodiments, in one embodiment, the register access routing module is specifically used to: obtain the identification number and register address of the target virtual function in the read and write requests; query the content of the target virtual function from the mapping table based on the identification number of the target virtual function, and determine the index number of the target acceleration unit requested to be accessed based on the register address and the content of the target virtual function; determine the address of the target register based on the register address.

[0126] Specifically, for the index number of the target acceleration unit in the first request, the register access routing module queries the content of the target virtual function from the mapping table according to the identification number of the target virtual function in the read / write request. Then, the target acceleration unit to be accessed is determined according to the register address in the read / write request and the content of the target virtual function, and the index number afu_index of the target acceleration unit requested to be accessed is obtained. For the address of the target register in the first request, after the determination of the target acceleration unit is completed, the address of the target register of the target acceleration unit is determined based on the register address.

[0127] For the register address in the read and write request, optionally, the register address is the address obtained by adding the target starting address and the target offset address; the target starting address is the starting address of the target register of the target acceleration unit requested to be accessed, determined based on the read-only base address register space of the target virtual function, within the register access space of the target virtual function; the target offset address is the offset address of the target register relative to the target acceleration unit.

[0128] Specifically, the target virtual function has two base address register (BAR) spaces, namely, a read-only BAR space and a read-write BAR space. The user can read a fixed address in the read-only BAR space to determine the starting address reg_start of the target register of the target acceleration unit requested to be accessed in the register access space of the target virtual function, i.e., the target starting address. The target offset address is the offset address offset of the target register relative to the target acceleration unit. reg_start+offset is the register address.

[0129] For the address of the target register, optionally, the address of the target register is an address obtained by subtracting the target start address from the register address.

[0130] Based on the above embodiment, in one embodiment, the content of the target virtual function includes the starting address and the ending address of the register space of each target acceleration unit bound to the target virtual function in the register access space of the target virtual function;

[0131] The register access routing module is specifically used to: determine the register interval of each target acceleration unit based on the starting address and ending address of the register space of each target acceleration unit in the register access space of the target virtual function; for each target acceleration unit, when the register address falls within the register interval of the target acceleration unit, determine that the target acceleration unit is the target acceleration unit requested to be accessed.

[0132] Specifically, the content of the target virtual function includes the starting address reg_start and the ending address reg_end of the register space of each target acceleration unit bound to the target virtual function in the register access space of the target virtual function. The register access routing module traverses each target acceleration unit to determine whether the register address of the target acceleration unit falls within the register interval (reg_start, reg_end) of the target acceleration unit. If so, the target acceleration unit is determined to be the target acceleration unit requested for access, otherwise the next target acceleration unit is queried to determine the target acceleration unit requested for access.

[0133] The following is a detailed description of the read and write operations of the target acceleration unit.

[0134] In one embodiment, for a read request, the target acceleration unit is specifically used to: query the identification number of the bound target virtual function from the acceleration unit configuration table based on the index number of the target acceleration unit; read the first data from the address of the target register, and pass the second request carrying the first data and the identification number of the target virtual function to the register access routing module through the register access interface and the register access arbitration module;

[0135] The register access routing module is further used to: respond to the second request and return the first data to the target virtual machine through the target virtual function.

[0136] Specifically, the target acceleration unit queries the identification number vf_index of the bound target virtual function from the acceleration unit configuration table based on the index number afu_index of the target acceleration unit. The target acceleration unit reads the first data from the address of the target register, and passes the second request carrying the first data and the identification number of the target virtual function to the register access routing module through the register access interface and the register access arbitration module. The register access routing module responds to the second request and returns the first data to the target virtual machine through the target virtual function, thereby completing the read operation of the target acceleration unit.

[0137] In one embodiment, for a write request, the register access arbitration module is further used to: transmit the second data carried in the first request to the target acceleration unit through the register access interface of the target acceleration unit;

[0138] The target acceleration unit is specifically used to write the second data into the target register through the address of the target register.

[0139] Specifically, the second data carried in the first request is obtained from the write request. The register access arbitration module transmits the second data to the target acceleration unit through the register access interface of the target acceleration unit. The target acceleration unit writes the second data into the target register through the address of the target register, thereby completing the write operation of the target acceleration unit.

[0140] In one embodiment, if Figure 2 As shown, each acceleration unit includes an interrupt interface;

[0141] The static area also includes:

[0142] An interrupt interface arbitration module, which is connected to each interrupt interface and the interrupt routing module respectively, and is used to respond to the interrupt request transmitted by the target acceleration unit through the interrupt interface, arbitrate and release the interrupt request, and transmit the interrupt request to the interrupt routing module;

[0143] An interrupt routing module, connected to each virtual function, for responding to an interrupt request and transmitting a third request carrying a target interrupt number to a target virtual function;

[0144] The target virtual function is specifically used to: respond to the third request and trigger an interrupt with a target interrupt number to the target virtual machine.

[0145] Specifically, the target acceleration unit transmits the interrupt request to the interrupt interface arbitration module through the interrupt interface. The interrupt interface arbitration module queues the requests in the order of priority, arbitrates and releases the interrupt request when it is queued, and transmits the interrupt request to the interrupt routing module. The interrupt routing module responds to the interrupt request and transmits the third request carrying the target interrupt number to the target virtual function. The target virtual function responds to the third request and triggers an interrupt with the target interrupt number to the target virtual machine, thereby completing the transmission of the interrupt from the acceleration unit to the virtual function.

[0146] For the target interrupt number, optionally, the interrupt routing module is specifically used to: obtain the index number afu_index of the target acceleration unit and the first interrupt number irq of the target acceleration unit carried in the interrupt request, and query the identification number vf_index of the target virtual function bound to the target acceleration unit and the second interrupt number msix_index of the start interrupt of the target acceleration unit in the interrupt space of the target virtual function from the acceleration unit configuration table based on the index number afu_index of the target acceleration unit; add the second interrupt number msix_index and the first interrupt number irq to obtain the target interrupt number.

[0147] In one embodiment, the target virtual function is specifically used to: respond to a memory application request sent by the target virtual machine, and return a target start address and a target address length to the target virtual machine;

[0148] like Figure 2 As shown, the static area also includes:

[0149] a memory data transfer module (also called a direct memory access (DMA) data transfer module), which is connected to each virtual function and is used to respond to a memory data transfer request transmitted by a target virtual machine through a target virtual function, and query from an acceleration unit configuration table based on an identification number of the target virtual function in the memory data transfer request whether a target start address and a target address length in the memory data transfer request are within a memory storage space accessible to the target virtual function; if so, write the third data in the memory data transfer request into a memory storage space corresponding to the target start address and the target address length, otherwise report an exception;

[0150] The target virtual function is also used to write the target start address and the target address length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface.

[0151] Specifically, the user's target virtual machine sends a memory application request based on the interface provided by the device driver of the target virtual function. The target virtual function responds to the memory application request and returns the target starting address ddr_start and the target address length ddr_length to the target virtual machine. Subsequently, the target virtual machine initiates a memory data transfer request, and the memory data transfer request is passed to the memory data transfer module through the target virtual function. The memory data transfer module responds to the memory data transfer request and queries the acceleration unit configuration table based on the identification number vf_index of the target virtual function in the memory data transfer request whether the target starting address ddr_start and the target address length ddr_length in the memory data transfer request are within the memory storage space accessible to the target virtual function. If so, the third data in the memory data transfer request is written into the memory storage space corresponding to the target starting address ddr_start and the target address length ddr_length, otherwise an exception is reported, thereby completing the host's access to the memory storage space.

[0152] In one embodiment, if Figure 2 As shown, each acceleration unit includes a memory access interface;

[0153] The target virtual function is specifically used to: write the target start address and the target address length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface;

[0154] The target acceleration unit is specifically used to: read the target start address and the target address length from the address register, and initiate a memory access request carrying the index number of the target acceleration unit, the target start address and the target address length to the memory access arbitration module through the memory access interface;

[0155] The static area also includes:

[0156] A memory access arbitration module, which is connected to each memory access interface and the memory access module, and is used to arbitrate and release the memory access request and pass the memory access request to the memory access module;

[0157] A memory access module is used to respond to memory access requests and query the acceleration unit configuration table based on the index number of the target acceleration unit to see whether the target starting address and target address length are within the memory storage space accessible to the target virtual function; if so, the data in the memory storage space corresponding to the target starting address and target address length are written into the acceleration unit, otherwise an exception is reported.

[0158] It should be noted that the above-mentioned "memory" may refer to double data rate synchronous dynamic random access memory (DDR SDRAM).

[0159] Specifically, the user's target virtual machine passes the target start address ddr_start and the target address length ddr_length to the target virtual function. The target virtual function writes the target start address ddr_start and the target address length ddr_length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface to inform the address to be accessed. The target acceleration unit reads the target start address ddr_start and the target address length ddr_length from the address register, and initiates a memory access request carrying the index number afu_index of the target acceleration unit, the target start address ddr_start and the target address length ddr_length to the memory access arbitration module through the memory access interface. The memory access arbitration module queues the requests in the order of priority, arbitrates and releases the memory access request when the memory access request is queued, and passes the memory access request to the memory access module. The memory access module responds to the memory access request, and queries the target start address ddr_start and the target address length ddr_length from the acceleration unit configuration table based on the index number afu_index of the target acceleration unit to see whether they are within the memory storage space accessible to the target virtual function. If so, the data in the memory storage space corresponding to the target starting address ddr_start and the target address length ddr_length is written into the acceleration unit, otherwise an exception is reported, thereby completing the acceleration unit's access to the memory storage space.

[0160] In one embodiment, the physical function is also used for: after configuring the mapping table and the acceleration unit configuration table, setting the binding status of the target virtual function and the acceleration unit in the virtual function status information table to a valid identifier, setting the binding status of each target acceleration unit and the virtual function in the acceleration unit status information table to a valid identifier, and timely updating the binding status in the virtual function status information table and the acceleration unit status information table.

[0161] In one embodiment, the physical function is also used for: after the target virtual machine is shut down and the target virtual function is released, setting the binding status of the target virtual function and the acceleration unit in the virtual function status information table to an invalid mark; querying the index number of each target acceleration unit bound to the target virtual function from the mapping table based on the identification number of the target virtual function; setting the binding status of each target acceleration unit and the virtual function in the acceleration unit status information table to an invalid mark; deleting the information of each target acceleration unit in the acceleration unit configuration table; deleting the information of the target virtual function in the mapping table, so as to realize the unbinding of the target virtual function and each target acceleration unit.

[0162] In order to more clearly understand the present invention, the above accelerator device is described in detail below through specific embodiments.

[0163] Assume that an accelerator device includes 4 acceleration units and 4 virtual functions, and its virtual function status information table and acceleration unit status information table are as follows.

[0164] Table 5 Virtual function status information table

[0165]

[0166] Table 6 Acceleration unit status information table

[0167]

[0168] Assume that a user needs an accelerator device including two functions and a memory storage space size of 1 GB, and the function identification numbers of the two functions are 4C3A8ECC-0940-6B0A-C2E3-1570822F090C and 743775C7-CFEC-472B-FCCC-79C271E1C36B respectively.

[0169] The data center found that the accelerator device meets the above user acceleration function requirements, that is, it meets the following conditions: 1) The two functions correspond to the acceleration unit 1 and the acceleration unit 4 of the accelerator device, and both acceleration units are in an unbound state; 2) The register access space 1MB contained in the virtual function is greater than the sum of the register spaces of all acceleration units 20KB; 3) The number of interrupts supported by the virtual function 1 of the accelerator device is 8, which is greater than the sum of the number of interrupts required by the two acceleration units, 5, and the number of interrupts supported by the virtual function 2 is 16, which is greater than the sum of the number of interrupts required by the two acceleration units, 5, so it meets the user acceleration function requirements. Virtual function 3 does not meet the user acceleration function requirements because it has been bound to the acceleration unit. Virtual function 4 does not meet the user acceleration function requirements because the number of interrupts it supports, 4, is less than the sum of the number of interrupts required by the two acceleration units, 5. Therefore, both virtual function 1 and virtual function 2 meet the user acceleration function requirements, and it is assumed that virtual function 1 is selected here.

[0170] Then, the mapping table and the acceleration unit configuration table are configured to bind virtual function 1 to acceleration units 1 and 4. The configured mapping table and acceleration unit configuration table are shown below.

[0171] Table 7 Mapping table

[0172]

[0173] Table 8 Acceleration unit configuration table

[0174]

[0175] As can be seen from Table 7, the memory storage space accessible to virtual function 1 has a starting address of 0x1000, an address length of 0x40000000, and contains 2 acceleration units. The serial number of the first acceleration unit is 1, its register space is 4KB, the address in the register access space of virtual function 1 is [0,0xfff], the number of interrupts required is 1, and the starting number in the interrupt space of virtual function 1 is 0, that is, interrupt No. 0 of virtual function 1 is assigned to the first interrupt of acceleration unit 1. The serial number of the second acceleration unit is 4, its register space is 4KB, the address in the register access space of virtual function 1 is [0x1000,0x1fff], the number of interrupts required is 4, and the starting number in the interrupt space of virtual function 1 is 1, that is, interrupt No. 1 of virtual function 1 is assigned to the first interrupt of acceleration unit 2.

[0176] The following takes the example of a user writing data 0x1000 to a register with an offset of 0x10 in acceleration unit 4 to introduce the register access process.

[0177] 1) The user obtains the register starting address of the acceleration unit 4 contained in the virtual function 1 as 0x1000 by reading the specific address of the read-only BAR space of the virtual function 1, and then initiates a write request to the address 0x1010 of the readable and writable BAR space of the virtual function 1.

[0178] 2) The write request is passed to the register access routing module in the static area. The register access routing module queries the mapping table according to the identification number of the virtual function and determines that the register access address belongs to acceleration unit 4. The actual address is 0x1010-0x1000=0x10.

[0179] 3) The register request is passed to the register access arbitration module. When the request is executed, acceleration unit 4 is selected, the address is set to 0x10, and the data 0x1000 is written to the register 0x10 through the register access interface of acceleration unit 4, thereby completing the register access.

[0180] The implementation method of the accelerator device provided by the present invention is described below. The implementation method of the accelerator device described below and the accelerator device described above can be referenced to each other.

[0181] Please refer to Figure 3 , Figure 3 FIG. 1 is a flow chart of a method for implementing an accelerator device provided in an embodiment of the present invention. Figure 3 As shown, the method may include steps 301 to 303.

[0182] Step 301: Obtain a virtual function status information table and an acceleration unit status information table through a physical function; the virtual function status information table is used to store status information of each virtual function; the acceleration unit status information table is used to store status information of each acceleration unit;

[0183] Step 302: Based on the virtual function status information table and the acceleration unit status information table, a mapping table is configured to store mapping relationships between target virtual functions and multiple target acceleration units, and an acceleration unit configuration table is configured to store information of each target acceleration unit;

[0184] Step 303: Allocate the target virtual function to the target virtual machine.

[0185] In one embodiment, the virtual function status information table includes: the identification number of each virtual function, the number of interrupts supported, the size of the register access space, and the binding status with the acceleration unit;

[0186] The acceleration unit status information table includes: the index number of each acceleration unit, the function identification number, the size of the space occupied by the register, the number of interrupts, and the binding status with the virtual function.

[0187] In one embodiment, the mapping table includes: a basic information area and a plurality of acceleration unit information areas;

[0188] The basic information area includes: the identification number of the target virtual function, the starting address and length of the accessible memory storage space, and the number of bound target acceleration units;

[0189] The acceleration unit information area includes: the index number of the target acceleration unit, the function identification number, the starting address and the ending address of the register space in the register access space of the target virtual function, the number of interrupts, and the interrupt number of the starting interrupt in the interrupt space of the target virtual function;

[0190] The acceleration unit configuration table includes: the index number of each target acceleration unit, the identification number of the target virtual function, the starting address of the register in the register access space of the target virtual function, the starting address and ending address of the accessible memory storage space, and the interrupt number of the starting interrupt in the interrupt space of the target virtual function.

[0191] In one embodiment, if Figure 4 As shown, the method also includes:

[0192] Step 401: respond to the read / write request transmitted through the target virtual function through the register access routing module, and transmit the first request carrying the index number of the target acceleration unit requested to be accessed and the address of the target register to the register access arbitration module;

[0193] Step 402: arbitrate and release the first request through the register access arbitration module, and transfer the address of the target register to the target acceleration unit through the register access interface of the target acceleration unit for read and write operations.

[0194] In one embodiment, the index number of the target acceleration unit requested to be accessed and the address of the target register are determined by the following steps:

[0195] The identification number and register address of the target virtual function in the read and write request are obtained through the register access routing module; the content of the target virtual function is queried from the mapping table based on the identification number of the target virtual function, and the index number of the target acceleration unit requested to be accessed is determined based on the register address and the content of the target virtual function; the address of the target register is determined based on the register address.

[0196] In one embodiment, the content of the target virtual function includes a start address and an end address of a register space of each target acceleration unit bound to the target virtual function within a register access space of the target virtual function;

[0197] The target acceleration unit for the requested access is determined by the following steps:

[0198] The register range of each target acceleration unit is determined through the register access routing module based on the starting address and ending address of the register space of each target acceleration unit in the register access space of the target virtual function; for each target acceleration unit, when the register address falls within the register range of the target acceleration unit, the target acceleration unit is determined to be the target acceleration unit requested to be accessed.

[0199] In one embodiment, the method further comprises:

[0200] For a read request, query the identification number of the bound target virtual function from the acceleration unit configuration table based on the index number of the target acceleration unit through the target acceleration unit; read the first data from the address of the target register, and pass the second request carrying the first data and the identification number of the target virtual function to the register access routing module through the register access interface and the register access arbitration module;

[0201] The register access routing module responds to the second request and returns the first data to the target virtual machine through the target virtual function.

[0202] In one embodiment, the method further comprises:

[0203] For the write request, the second data carried in the first request is transmitted to the target acceleration unit through the register access interface of the target acceleration unit through the register access arbitration module;

[0204] The second data is written into the target register through the address of the target register through the target acceleration unit.

[0205] In one embodiment, the register address is an address obtained by adding the target start address and the target offset address;

[0206] The target start address is a start address of a target register of a target acceleration unit requested to be accessed, determined based on a read-only base address register space of a target virtual function, within a register access space of the target virtual function;

[0207] The target offset address is the offset address of the target register relative to the target acceleration unit.

[0208] In one embodiment, the address of the target register is an address obtained by subtracting the target start address from the register address.

[0209] In one embodiment, if Figure 5 As shown, the method also includes:

[0210] Step 501: respond to the interrupt request transmitted by the target acceleration unit through the interrupt interface through the interrupt interface arbitration module, arbitrate and release the interrupt request, and transmit the interrupt request to the interrupt routing module;

[0211] Step 502: respond to the interrupt request through the interrupt routing module, and transmit the third request carrying the target interrupt number to the target virtual function;

[0212] Step 503: Respond to the third request through the target virtual function, and trigger an interrupt with the target interrupt number to the target virtual machine.

[0213] In one embodiment, the target interrupt number is determined by the following steps:

[0214] The index number of the target acceleration unit and the first interrupt number of the target acceleration unit carried in the interrupt request are obtained through the interrupt routing module. Based on the index number of the target acceleration unit, the identification number of the target virtual function bound to the target acceleration unit and the second interrupt number of the starting interrupt of the target acceleration unit in the interrupt space of the target virtual function are queried from the acceleration unit configuration table; the second interrupt number and the first interrupt number are added to obtain the target interrupt number.

[0215] In one embodiment, if Figure 6 As shown, the method also includes:

[0216] Step 601: respond to the memory request sent by the target virtual machine through the target virtual function, and return the target start address and target address length to the target virtual machine;

[0217] Step 602: respond to the memory data transfer request transmitted by the target virtual machine through the target virtual function through the memory data transfer module, and query from the acceleration unit configuration table based on the identification number of the target virtual function in the memory data transfer request whether the target start address and the target address length in the memory data transfer request are within the memory storage space accessible to the target virtual function; if so, write the third data in the memory data transfer request into the memory storage space corresponding to the target start address and the target address length; otherwise, report an exception;

[0218] Step 603: Write the target start address and the target address length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface through the target virtual function.

[0219] In one embodiment, if Figure 7 As shown, the method also includes:

[0220] Step 701: write the target start address and the target address length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface through the target virtual function;

[0221] Step 702: read the target start address and the target address length from the address register through the target acceleration unit, and initiate a memory access request carrying the index number of the target acceleration unit, the target start address and the target address length to the memory access arbitration module through the memory access interface;

[0222] Step 703: The memory access arbitration module arbitrates and releases the memory access request, and transmits the memory access request to the memory access module;

[0223] Step 704, respond to the memory access request through the memory access module, and query from the acceleration unit configuration table based on the index number of the target acceleration unit whether the target start address and the target address length are within the memory storage space accessible to the target virtual function; if so, write the data in the memory storage space corresponding to the target start address and the target address length into the acceleration unit, otherwise report an exception.

[0224] In one embodiment, the method further includes: after configuring the mapping table and the acceleration unit configuration table through the physical function, setting the binding status of the target virtual function and the acceleration unit in the virtual function status information table to a valid identifier, and setting the binding status of each target acceleration unit and the virtual function in the acceleration unit status information table to a valid identifier.

[0225] In one embodiment, the method further includes: after the target virtual machine is shut down and the target virtual function is released through a physical function, setting the binding status of the target virtual function and the acceleration unit in the virtual function status information table to an invalid mark; based on the identification number of the target virtual function, querying the index number of each target acceleration unit bound to the target virtual function from the mapping table; setting the binding status of each target acceleration unit and the virtual function in the acceleration unit status information table to an invalid mark; deleting the information of each target acceleration unit in the acceleration unit configuration table; and deleting the information of the target virtual function in the mapping table.

[0226] Figure 8 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 8As shown, the electronic device may include: a processor 810, a communication interface 820, a memory 830 and a communication bus 840, wherein the processor 810, the communication interface 820 and the memory 830 communicate with each other through the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute the implementation method of the accelerator device, the method comprising: obtaining a virtual function status information table and an acceleration unit status information table through a physical function; the virtual function status information table is used to store the status information of each virtual function; the acceleration unit status information table is used to store the status information of each acceleration unit; based on the virtual function status information table and the acceleration unit status information table, the mapping table is configured to store the mapping relationship between the target virtual function and multiple target acceleration units, and the acceleration unit configuration table is configured to store the information of each target acceleration unit; the target virtual function is allocated to the target virtual machine.

[0227] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0228] On the other hand, the present invention also provides a computer program product, which includes a computer program, and the computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the implementation method of the accelerator device provided by the above-mentioned method embodiments, the method including: obtaining a virtual function status information table and an acceleration unit status information table through a physical function; the virtual function status information table is used to store the status information of each virtual function; the acceleration unit status information table is used to store the status information of each acceleration unit; based on the virtual function status information table and the acceleration unit status information table, the mapping table is configured to store the mapping relationship between the target virtual function and multiple target acceleration units, and the acceleration unit configuration table is configured to store the information of each target acceleration unit; the target virtual function is assigned to the target virtual machine.

[0229] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the implementation method of the accelerator device provided by the above-mentioned method embodiments, the method comprising: obtaining a virtual function status information table and an acceleration unit status information table through a physical function; the virtual function status information table is used to store the status information of each virtual function; the acceleration unit status information table is used to store the status information of each acceleration unit; based on the virtual function status information table and the acceleration unit status information table, configuring a mapping table to store a mapping relationship between a target virtual function and multiple target acceleration units, and configuring an acceleration unit configuration table to store information of each target acceleration unit; and allocating the target virtual function to a target virtual machine.

[0230] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0231] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0232] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An accelerator device, characterized in that: include: Static area and dynamic area; The static area includes a physical function, a plurality of virtual functions, a virtual function status information table, an acceleration unit status information table, a mapping table and an acceleration unit configuration table; The dynamic region includes a plurality of acceleration units; The virtual function status information table is used to store status information of each virtual function; The acceleration unit status information table is used to store the status information of each acceleration unit; The physical function is used to configure the mapping table to store the mapping relationship between the target virtual function and multiple target acceleration units, and configure the acceleration unit configuration table to store information of each of the target acceleration units based on the virtual function status information table and the acceleration unit status information table; and allocate the target virtual function to the target virtual machine.

2. The accelerator device according to claim 1, characterized in that The virtual function status information table includes: the identification number of each virtual function, the number of interrupts supported, the size of the register access space, and the binding status with the acceleration unit; The acceleration unit status information table includes: the index number of each acceleration unit, the function identification number, the size of the space occupied by the register, the number of interrupts, and the binding status with the virtual function.

3. The accelerator device according to claim 1, characterized in that The mapping table includes: a basic information area and a plurality of acceleration unit information areas; The basic information area includes: the identification number of the target virtual function, the starting address and length of the accessible memory storage space, and the number of bound target acceleration units; The acceleration unit information area includes: the index number of the target acceleration unit, the function identification number, the starting address and the ending address of the register space in the register access space of the target virtual function, the number of interrupts, and the interrupt number of the starting interrupt in the interrupt space of the target virtual function; The acceleration unit configuration table includes: the index number of each target acceleration unit, the identification number of the target virtual function, the starting address of the register in the register access space of the target virtual function, the starting address and ending address of the accessible memory storage space, and the interrupt number of the starting interrupt in the interrupt space of the target virtual function.

4. The accelerator device according to claim 3, characterized in that Each of the acceleration units includes a register access interface; The static area also includes: A register access routing module, connected to each of the virtual functions and the register access arbitration module, for responding to a read or write request transmitted through the target virtual function, and transmitting a first request carrying an index number of the target acceleration unit requested to be accessed and an address of a target register to the register access arbitration module; The register access arbitration module is connected to each of the register access interfaces, and is used to arbitrate and release the first request, and transmit the address of the target register to the target acceleration unit through the register access interface of the target acceleration unit for read and write operations.

5. The accelerator device according to claim 4, characterized in that The register access routing module is specifically used to: obtain the identification number and register address of the target virtual function in the read / write request; query the content of the target virtual function from the mapping table based on the identification number of the target virtual function, and determine the index number of the target acceleration unit requested to be accessed based on the register address and the content of the target virtual function; An address of the target register is determined based on the register address.

6. The accelerator device according to claim 5, characterized in that The content of the target virtual function includes the starting address and the ending address of the register space of each target acceleration unit bound to the target virtual function within the register access space of the target virtual function; The register access routing module is specifically used to: determine the register interval of each target acceleration unit based on the starting address and ending address of the register space of each target acceleration unit in the register access space of the target virtual function; for each target acceleration unit, when the register address falls within the register interval of the target acceleration unit, determine that the target acceleration unit is the target acceleration unit requested to be accessed.

7. The accelerator device according to claim 4, characterized in that For a read request, the target acceleration unit is specifically used to: query the identification number of the bound target virtual function from the acceleration unit configuration table based on the index number of the target acceleration unit; read the first data from the address of the target register, and pass the second request carrying the first data and the identification number of the target virtual function to the register access routing module through the register access interface and the register access arbitration module; The register access routing module is further used to: respond to the second request and return the first data to the target virtual machine through the target virtual function.

8. The accelerator device according to claim 4, characterized in that For a write request, the register access arbitration module is further used to: transfer the second data carried in the first request to the target acceleration unit through the register access interface of the target acceleration unit; The target acceleration unit is specifically used to write the second data into the target register through the address of the target register.

9. The accelerator device according to claim 5, characterized in that The register address is the address obtained by adding the target start address and the target offset address; The target start address is a start address of the target register of the target acceleration unit requested to be accessed within the register access space of the target virtual function, determined based on the read-only base address register space of the target virtual function; The target offset address is an offset address of the target register relative to the target acceleration unit.

10. The accelerator device according to claim 9, characterized in that The address of the target register is an address obtained by subtracting the target start address from the register address.

11. The accelerator device according to claim 3, characterized in that Each of the acceleration units includes an interrupt interface; The static area also includes: An interrupt interface arbitration module, which is connected to each of the interrupt interfaces and the interrupt routing module respectively, and is used to respond to the interrupt request transmitted by the target acceleration unit through the interrupt interface, arbitrate and release the interrupt request, and transmit the interrupt request to the interrupt routing module; The interrupt routing module is connected to each of the virtual functions and is used to respond to the interrupt request and transmit the third request carrying the target interrupt number to the target virtual function; The target virtual function is specifically configured to: respond to the third request and trigger an interrupt with the target interrupt number to the target virtual machine.

12. The accelerator device according to claim 11, characterized in that The interrupt routing module is specifically used to: obtain the index number of the target acceleration unit and the first interrupt number of the target acceleration unit carried in the interrupt request, query the identification number of the target virtual function bound to the target acceleration unit and the second interrupt number of the start interrupt of the target acceleration unit in the interrupt space of the target virtual function from the acceleration unit configuration table based on the index number of the target acceleration unit; add the second interrupt number and the first interrupt number to obtain the target interrupt number.

13. The accelerator device according to claim 4, characterized in that The target virtual function is specifically used to: respond to the memory application request sent by the target virtual machine, and return the target start address and the target address length to the target virtual machine; The static area also includes: a memory data transfer module, which is connected to each of the virtual functions and is used to respond to a memory data transfer request transmitted by the target virtual machine through the target virtual function, and query from the acceleration unit configuration table based on the identification number of the target virtual function in the memory data transfer request whether the target start address and the target address length in the memory data transfer request are within the memory storage space accessible to the target virtual function; if so, write the third data in the memory data transfer request into the memory storage space corresponding to the target start address and the target address length, otherwise report an exception; The target virtual function is also used to write the target start address and the target address length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface.

14. The accelerator device according to claim 4, characterized in that Each of the acceleration units includes a memory access interface; The target virtual function is specifically used to: write the target start address and the target address length into the address register of the target acceleration unit through the register access routing module, the register access arbitration module and the register access interface; The target acceleration unit is specifically used to: read the target start address and the target address length from the address register, and initiate a memory access request carrying the index number of the target acceleration unit, the target start address and the target address length to the memory access arbitration module through the memory access interface; The static area also includes: The memory access arbitration module is connected to each of the memory access interfaces and the memory access module, and is used to arbitrate and release the memory access request, and transmit the memory access request to the memory access module; The memory access module is used to respond to the memory access request and query from the acceleration unit configuration table whether the target starting address and the target address length are within the memory storage space accessible to the target virtual function based on the index number of the target acceleration unit; if so, write the data in the memory storage space corresponding to the target starting address and the target address length into the acceleration unit, otherwise report an exception.

15. The accelerator device according to claim 3, characterized in that The physical function is also used to: after configuring the mapping table and the acceleration unit configuration table, set the binding status of the target virtual function and the acceleration unit in the virtual function status information table to a valid identifier, and set the binding status of each target acceleration unit and virtual function in the acceleration unit status information table to a valid identifier.

16. The accelerator device according to claim 15, characterized in that The physical function is also used to: after the target virtual machine is shut down and the target virtual function is released, set the binding state between the target virtual function and the acceleration unit in the virtual function status information table to an invalid mark; query the index number of each target acceleration unit bound to the target virtual function from the mapping table based on the identification number of the target virtual function; set the binding state between each target acceleration unit and the virtual function in the acceleration unit status information table to an invalid mark; delete the information of each target acceleration unit in the acceleration unit configuration table; The information of the target virtual function in the mapping table is deleted.

17. A method for implementing the accelerator device according to any one of claims 1 to 16, characterized in that: include: Acquire a virtual function status information table and an acceleration unit status information table through a physical function; the virtual function status information table is used to store status information of each virtual function; The acceleration unit status information table is used to store status information of each acceleration unit; Based on the virtual function status information table and the acceleration unit status information table, a mapping table is configured to store mapping relationships between target virtual functions and multiple target acceleration units, and an acceleration unit configuration table is configured to store information of each of the target acceleration units; The target virtual function is allocated to a target virtual machine.

18. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the implementation method of the accelerator device according to claim 17 is implemented.

19. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the implementation method of the accelerator device according to claim 17 is implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the implementation method of the accelerator device as claimed in claim 17 is implemented.

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