Data input and output circuit and memory

Abstract

The embodiments of the present application relate to the field of memory, and provide a data input-output circuit and a memory, including: a parallel-to-serial circuit, configured to receive N data and output the N data serially within a first time period; a read enable signal generating circuit, configured to generate a read enable signal, and the read enable signal is at a valid level within the first time period; a resistance control circuit, electrically connected to the read enable signal generating circuit, configured to receive a termination resistance control code, an output drive resistance control code, and a read enable signal, and based on the read enable signal, select to output a termination resistance control code or output an output drive resistance control code; an output drive circuit, electrically connected to the parallel-to-serial circuit and the resistance control circuit, configured to receive N data and a signal output by the resistance control circuit, and configure an output drive resistance value and output N data based on the signal output by the resistance control circuit, or configure a termination resistance value; wherein N is a positive integer greater than 1.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of memory, and in particular to a data input / output circuit and a memory including the input / output circuit. Background Art

[0002] At present, memory plays a very important role in various electronic devices. When reading and writing data in memory (such as dynamic random access memory, DRAM), data needs to be read and written through the data input / output terminal (DQ). In order to ensure the stable transmission of data on DQ, ODT resistors (On-Die Termination, on-chip termination, termination resistor) and ODI resistors (output drive resistors) need to be configured. In high-speed data transmission, signal reflection and signal attenuation will cause signal quality to deteriorate and increase the bit error rate. The value of the ODT resistor can match the characteristic impedance of the data bus, reduce / absorb the reflection of the signal, and ensure the stable transmission of data on the DQ pin. When the data is output, by adjusting the value of the output drive resistor, the driving strength of the output signal can be controlled to match the characteristic impedance of the external bus, thereby reducing signal reflection and improving signal integrity and stability.

[0003] However, the read and write operations of the memory have strict timing requirements, so there are corresponding timing requirements for the configuration of the ODT resistor and the output drive resistor, so that the ODT resistor and the output drive resistor can match the read and write operation timings so that data can be correctly read / written into the memory. How to design a data input / output circuit so that the memory can perform impedance matching under different operations by controlling the data input / output circuit is an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present application provide a data input / output circuit and a memory including the input / output circuit, which are at least helpful in solving the problem of how to perform impedance matching under different operations of the DQ end.

[0005] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a data input / output circuit, including a parallel-to-serial circuit, a read enable signal generating circuit, a resistance control circuit and an output drive circuit; wherein the parallel-to-serial circuit is configured to receive N data and output the N data in series within a first time period; the read enable signal generating circuit is configured to generate a read enable signal, and the read enable signal is at a valid level within the first time period; the resistance control circuit is electrically connected to the read enable signal generating circuit, and is configured to receive a termination resistance control code, an output drive resistance control code and the read enable signal, and based on the read enable signal, selects to output the termination resistance control code or output the output drive resistance control code; the output drive circuit is electrically connected to the parallel-to-serial circuit and the resistance control circuit, and is configured to receive the N data and a signal output by the resistance control circuit, and configures an output drive resistance value and outputs the N data based on the signal output by the resistance control circuit, or configures a termination resistance value; wherein N is a positive integer greater than 1.

[0006] In some embodiments, the data input / output circuit also includes a pull-up driving circuit and a pull-down driving circuit, and the parallel-to-serial circuit connects the pull-up driving circuit and the pull-down driving circuit to output the N data to the pull-up driving circuit and the pull-down driving circuit.

[0007] In some embodiments, the parallel-to-serial circuit includes a first data input port, a second data input port, a third data input port, and a fourth data input port, and the parallel-to-serial circuit receives the N data through the first to fourth data input ports; the parallel-to-serial circuit also receives a first clock, a second clock, a third clock, and a fourth clock, and samples the N data based on the first to fourth clocks, and outputs the N data serially within a first time period;

[0008] The first time period includes a second time period, a third time period, and a fourth time period, the second time period is earlier than the third time period, and the third time period is earlier than the fourth time period; the parallel-to-serial circuit is further configured to: fixedly output the first level in the second time period and the fourth time period, and serially output the N data in the third time period;

[0009] The clock frequencies of the first clock, the second clock, the third clock and the fourth clock are the same, and the phase differences thereof are respectively one quarter of a cycle; and N is a positive integer multiple of 4.

[0010] In some embodiments, the parallel-to-serial circuit includes a first sampling circuit, a second sampling circuit, and a first NAND gate; the first input end of the first sampling circuit receives the first clock, the second input end of the first sampling circuit is connected to the first data input port, and the data input to the first data input port is sampled by the first clock; the first input end of the second sampling circuit receives the second clock, the second input end of the second sampling circuit receives the second level, and the second level is sampled by the second clock; the first input end of the first NAND gate is connected to the output end of the first sampling circuit, the second input end of the first NAND gate is connected to the output end of the second sampling circuit, and the first NAND gate outputs a first sampling result;

[0011] The parallel-to-serial circuit further includes a third sampling circuit, a fourth sampling circuit, and a second NAND gate; the first input end of the third sampling circuit receives the third clock, the second input end of the third sampling circuit is connected to the third data input port, and the data input to the third data input port is sampled by the third clock; the first input end of the fourth sampling circuit receives the fourth clock, the second input end of the fourth sampling circuit receives the second level, and the second level is sampled by the fourth clock; the first input end of the second NAND gate is connected to the output end of the third sampling circuit, the second input end of the second NAND gate is connected to the output end of the fourth sampling circuit, and the second NAND gate outputs a third sampling result;

[0012] The parallel-to-serial circuit further includes a fifth sampling circuit, a sixth sampling circuit, and a third NAND gate; the first input end of the fifth sampling circuit receives the second clock, the second input end of the fifth sampling circuit is connected to the second data input port, and the data input from the second data input port is sampled by the second clock; the first input end of the sixth sampling circuit receives the third clock, the second input end of the sixth sampling circuit receives the second level, and the second level is sampled by the third clock; the first input end of the third NAND gate is connected to the output end of the fifth sampling circuit, the second input end of the third NAND gate is connected to the output end of the sixth sampling circuit, and the third NAND gate outputs a second sampling result;

[0013] The parallel-to-serial circuit further includes a seventh sampling circuit, an eighth sampling circuit, and a fourth NAND gate; the first input end of the seventh sampling circuit receives the fourth clock, the second input end of the seventh sampling circuit is connected to the fourth data input port, and the data input from the fourth data input port is sampled by the fourth clock; the first input end of the eighth sampling circuit receives the first clock, the second input end of the eighth sampling circuit receives the second level, and the second level is sampled by the first clock; the first input end of the fourth NAND gate is connected to the output end of the seventh sampling circuit, the second input end of the fourth NAND gate is connected to the output end of the eighth sampling circuit, and the fourth NAND gate outputs a fourth sampling result;

[0014] A first AND logic circuit connects the first to fourth NAND gates, receives the first to fourth sampling results, and performs a first AND logic process on the first to fourth sampling results, thereby outputting the first level in a second time period and a fourth time period, and serially outputting the N data in a third time period.

[0015] In some embodiments, the resistance control circuit includes a first selection circuit, which is configured to: receive a termination resistance control code, an output drive resistance control code and the read enable signal, and when the read enable signal is at a valid level, the output end of the first selection circuit outputs the output drive resistance control code or its inverted signal; when the read enable signal is at an invalid level, the output end of the first selection circuit outputs the termination resistance control code.

[0016] In some embodiments, the first selection circuit includes a fifth NAND gate, a sixth NAND gate and a seventh NAND gate; the first input end of the fifth NAND gate receives a read enable signal, and the second input end of the fifth NAND gate receives an output drive resistance control code or its inverted signal; the first input end of the sixth NAND gate receives the inverted signal of the read enable signal, and the second input end of the sixth NAND gate receives a termination resistance control code; the two input ends of the seventh NAND gate are respectively connected to the output end of the fifth NAND gate and the output end of the sixth NAND gate, and the output end of the seventh NAND gate serves as the output end of the first selection circuit.

[0017] In some embodiments, the resistance control circuit includes a first selection circuit, and the first selection circuit is configured to: receive a termination resistance control code, an output drive resistance control code and the read enable signal, and when the read enable signal is at a valid level, the output end of the first selection circuit outputs the output drive resistance control code or its inverted signal to the pull-up drive circuit; when the read enable signal is at an invalid level, the output end of the first selection circuit outputs the termination resistance control code or its inverted signal to the pull-up drive circuit;

[0018] The resistance control circuit also includes a second selection circuit, which is configured to: receive an invalid level, an output drive resistance control code and the read enable signal, and when the read enable signal is a valid level, the output end of the second selection circuit outputs the output drive resistance control code or its inverted signal to the pull-down drive circuit; when the read enable signal is an invalid level, the output end of the second selection circuit outputs the invalid level to the pull-down drive circuit.

[0019] In some embodiments, the output driving circuit includes a pre-driving circuit and a main driving circuit, the pre-driving circuit includes a second AND logic circuit, a first input end of the second AND logic circuit receives the N data, and a second input end of the second AND logic circuit receives a signal output by the resistance control circuit;

[0020] The second AND logic circuit performs a non-AND logic process on the signal received at its first input terminal and the signal received at its second input terminal and then outputs the signal; the main driving circuit comprises a PMOS transistor electrically connected between the power supply voltage and the output port, and the control terminal of the PMOS transistor receives the signal output by the second AND logic circuit;

[0021] Alternatively, the second AND logic circuit performs AND logic processing on the signal received at its first input terminal and the signal received at its second input terminal and outputs the resultant signal, and the main drive circuit includes an NMOS transistor electrically connected between the power supply voltage and the output port, and the control terminal of the NMOS transistor receives the signal output by the second AND logic circuit.

[0022] In some embodiments, the pull-up driving circuit is connected to the output end of the parallel-to-serial circuit and receives the N data in a first time period; the pull-down driving circuit is connected to the output end of the parallel-to-serial circuit and receives the N data in a first time period;

[0023] The pull-up driving circuit is configured to: output a high level of the N data in a first time period, and configure the output driving resistance value based on the output driving resistance control code; the pull-down driving circuit is configured to: output a low level of the N data in a first time period, and configure the output driving resistance value based on the output driving resistance control code;

[0024] The pull-up driving circuit is further configured to configure a termination resistance value outside the first time period.

[0025] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a memory, the memory comprising the input / output circuit described in any of the aforementioned embodiments, the memory further comprising a storage array and a data transmission circuit, the storage array storing data; when a read operation is performed on the memory, the data is read out via the storage array, transmitted via the data transmission circuit, and then output via the data input / output circuit.

[0026] The technical solution provided by the embodiment of the present application has at least the following advantages: the memory can perform impedance matching under corresponding operations under both read operation and non-read operation. Since the timing of the state switching of the termination resistor RTT is the same as the timing of the output data of the read operation, the timing of the state switching of the termination resistor RTT and the timing of the control data output are multiplexed, and the termination resistor control code or the output drive resistor control code is selected by the read enable signal, so that the signal of the output control code word matches the timing of the data output by the parallel-to-serial circuit, thereby reducing power consumption and circuit area while avoiding the impact on tADC. On the other hand, the control code of the termination resistor and the control code of the output drive resistor are combined in one resistance control circuit for operation, which can save the area of ​​the circuit while ensuring the normal operation of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0028] Figure 1 A schematic diagram of the structure of a data input / output circuit provided in an embodiment of the present disclosure.

[0029] Figure 2 A structural schematic diagram of yet another data input / output circuit provided in an embodiment of the present disclosure.

[0030] Figure 3 A schematic diagram of the structure of a parallel-to-serial circuit provided in an embodiment of the present disclosure.

[0031] Figure 4 A timing diagram of a parallel-to-serial circuit provided in an embodiment of the present disclosure.

[0032] Figure 5 A schematic diagram of the structure of a read enable signal generating circuit provided in an embodiment of the present disclosure.

[0033] Figure 6 A timing diagram of a read enable signal generating circuit provided in an embodiment of the present disclosure.

[0034] Figure 7 A schematic diagram of the structure of a first selection circuit provided in an embodiment of the present disclosure.

[0035] Figure 8 A timing diagram of the first selection circuit provided in an embodiment of the present disclosure.

[0036] Fig. 9 A schematic diagram of the circuit structure of a second selection circuit provided in an embodiment of the present disclosure.

[0037] Fig.10 A schematic diagram of the structure of a pull-up pre-driver circuit provided in an embodiment of the present disclosure.

[0038] Fig.11 A schematic structural diagram of a first sub-pull-up main driving circuit provided in an embodiment of the present disclosure.

[0039] Fig.12 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] Below, the exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways, all of which do not deviate from the spirit or scope of the present invention. For example, the exemplary embodiments provided herein are considered to be able to be combined with each other in whole or in part to achieve. Specifically, an element described in a specific exemplary embodiment, even if not described in another exemplary embodiment, can also be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

[0041] Throughout this specification, when any part is referred to as being "connected" to another part, it includes the case where any part and another part are "indirectly connected" to each other due to other parts being interposed therebetween, as well as the case where any part and another part are "directly connected" to each other. For example, it should be understood that when an element is referred to as being "connected" or "coupled" to or "on another element", it may be directly connected or coupled to or on the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, or is referred to as "contacting" or "contacting" another element, there are no intermediate elements at the contact point.

[0042] In addition, "electrical connection" conceptually includes physical connection and physical disconnection. It is understood that when a component is referred to by terms such as "first" and "second", the component is not limited thereto. They may be used only for the purpose of distinguishing the component from other components and may not limit the order or importance of the components. In some cases, the first component may be referred to as the second component without departing from the scope of the claims set forth herein. Similarly, the second component may also be referred to as the first component.

[0043] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0044] Figure 1 Schematic diagram of a data input / output circuit provided by an embodiment of the present disclosure. Figure 1 As shown, the data input / output circuit 100 includes a parallel-to-serial circuit 110, a read enable signal generating circuit 120, a resistance control circuit 130 and an output driving circuit 140. Among them:

[0045] The parallel-to-serial circuit 110 is configured to receive N data D0, D1, D2, ..., D N-2 , D N-1 The inverted signals D0B, D1B, D2B..., D N-2 B.D N-1 B, and serially output the N data D0-D in the first time period N-1 As its output signal DATA, N is a positive integer greater than 1, such as 4, 8, 16, 32, etc. In other embodiments, N may also be other values.

[0046] The read enable signal generating circuit 120 is configured to generate a read enable signal Read_enable, and the read enable signal Read_enable is at a valid level in a first time period. In the embodiments of the present disclosure, a high level is taken as an example of a valid level. It should be understood that a low level can also be used as a valid level. High and low levels can be achieved by simply inverting. In the process of signal transmission, it is often driven by circuits such as inverters, so for the same signal, its inverted signal can be obtained again by simply inverting. Therefore, it is common to use a high level or a low level as a valid level. Unless otherwise specified, in the embodiments of the present disclosure, a signal itself and its inverted signal are regarded as a simple deformed embodiment.

[0047] The resistance control circuit 130 is electrically connected to the read enable signal generating circuit 120, and is configured to receive the termination resistance control code ODT, the output drive resistance control code RON and the read enable signal Read_enable, and based on the read enable signal Read_enable, select the termination resistance control code ODT or the output drive resistance control code RON as its output signal RON_ODT_code.

[0048] The output driving circuit 140 is electrically connected to the parallel-to-serial circuit 110 and the resistance control circuit 130, and is configured to receive the N data (DATA) and the output signal RON_ODT_code of the resistance control circuit 130, and configure the output driving resistance value and output the N data based on the output signal RON_ODT_code of the resistance control circuit 130, or configure the termination resistance value.

[0049] Specifically, when the memory performs a read operation and outputs data via the input / output circuit and the DQ terminal, within a first time period, the parallel-to-serial circuit 110 outputs data DATA, and the read enable signal Read_enable is at a valid level; the resistance control circuit 130 selects the output drive resistance control code RON as its output signal RON_ODT_code based on the valid level of the read enable signal Read_enable; the output drive circuit 140 serially outputs the data DATA received from the parallel-to-serial circuit 110 based on the output drive resistance control code RON, and configures the corresponding output drive resistance value.

[0050] When the memory is in other stages of a read operation, or in a write operation or other operations, the input / output circuit and the DQ terminal do not output data to the outside. At this time, the parallel-to-serial circuit 110 does not output the data DATA, and the read enable signal Read_enable is at an invalid level. The resistance control circuit 130 selects the termination resistance control code ODT as its output signal RON_ODT_code based on the invalid level of the read enable signal Read_enable; the output drive circuit 140 configures the corresponding termination resistance value based on the termination resistance control code ODT.

[0051] That is, the embodiment of the present disclosure provides a data input / output circuit, including a parallel-to-serial circuit, a read enable signal generating circuit, a resistance control circuit, and an output drive circuit; the read enable signal generated by the read enable signal generating circuit matches the timing of the output data of the parallel-to-serial circuit (that is, the read enable signal is at a valid level in the first time period of the serial output data of the parallel-to-serial circuit), receives the termination resistance control code and the output drive resistance control code through the resistance control circuit, and selects the output termination resistance control code or the output drive resistance control code based on the timing of the output data of the parallel-to-serial circuit through the read enable signal, thereby controlling the output drive circuit, and configuring the output drive resistance value and outputting data corresponding to the read operation, or configuring the termination resistance value corresponding to the non-read operation. Therefore, the memory can perform impedance matching under the corresponding operation under both the read operation and the non-read operation. Since the timing of the state switching of the termination resistance RTT is the same as the timing of the output data of the read operation, the timing of the state switching of the termination resistance RTT and the timing of the control data output are reused, so that the power consumption and circuit area can be reduced while avoiding the impact on tADC. On the other hand, the control code of the termination resistor and the control code of the output drive resistor are combined in one resistor control circuit, which can save the circuit area while ensuring the normal operation of the circuit.

[0052] Figure 2 A schematic diagram of the structure of another data input / output circuit provided in an embodiment of the present disclosure. In some cases, it can be Figure 1 An extended implementation of the embodiment shown includes Figure 1 The entire contents of the embodiment. Figure 1 and 2 As shown, the data input / output circuit 100 includes a parallel-to-serial circuit 110, a read enable signal generating circuit 120, a resistance control circuit 130, and an output driving circuit 140. Specifically, the output driving circuit 140 includes pull-up driving circuits 141 and 143 and pull-down driving circuits 142 and 144. The parallel-to-serial circuit 110 is connected to the pull-up driving circuit 141 and the pull-down driving circuit 142, and outputs N data DATA to the pull-up driving circuit 141 and the pull-down driving circuit 142.

[0053] The resistance control circuit 130 includes a pull-up resistance control circuit 131 and a pull-down resistance control circuit 132. The pull-up resistance control circuit 131 receives the termination resistance control code ODT, the output drive resistance control code RON and the read enable signal Read_enable, and configures the output drive resistance value or the termination resistance value of the pull-up drive circuit 141 based on the read enable signal Read_enable. The pull-down resistance control circuit 132 receives the output drive resistance control code RON and the read enable signal Read_enable, and configures the output drive resistance value of the pull-down drive circuit 142 based on the read enable signal Read_enable, or floats (or is in a high impedance state). When the read enable signal Read_enable is at a valid level, the pull-down resistance control circuit 132 selects the output drive resistance control code RON as its output signal RON_PD_CTL; when the read enable signal Read_enable is at an invalid level, the pull-down resistance control circuit 132 outputs an invalid level, turns off the corresponding pull-down drive circuit 142, and makes it output an invalid level (or in a high impedance state). In some other embodiments, the pull-down resistor control circuit 132 may also receive a low level Vss, so as to perform circuit design corresponding to the termination resistor control code ODT received by the pull-up resistor control circuit 131 .

[0054] In some embodiments, the output drive resistance control code RON includes a pull-up output drive resistance control code Pu_Ron and a pull-down output drive resistance control code Pd_Ron, the pull-up resistance control circuit 131 outputs the pull-up output drive resistance control code Pu_Ron or the termination resistance control code ODT to the pull-up drive circuit 141, and the pull-down resistance control circuit 132 outputs the pull-down output drive resistance control code Pd_Ron or outputs an invalid level to the pull-down drive circuit 142.

[0055] In this embodiment, since the pull-up driving circuit 141 and the pull-down driving circuit 142 receive control signals including timing and selected processing, the pull-up driving circuit 141 and the pull-down driving circuit 142 can be connected to the same parallel-to-serial circuit to receive the same data DATA.

[0056] Before and after the memory reads out data, it is necessary to ensure that the level of the DQ end is in a floating state. Since the circuit structures of the pull-up drive circuit and the pull-down drive circuit are different, in the prior art, when performing data parallel-to-serial conversion, two sets of parallel-to-serial circuits need to be made for outputting to the pull-up drive circuit and the pull-down drive circuit respectively, so that before and after the N data are read out, the pull-up drive circuit receives the default signal output by the parallel-to-serial circuit, so that the DQ end level is floating (that is, in a high impedance state), and the pull-down drive circuit receives the default signal output by the parallel-to-serial circuit, so that the DQ end level is floating (that is, in a high impedance state). For example, when the pull-up drive circuit is composed of PMOS transistors and the pull-down drive circuit is composed of NMOS transistors, the pull-up drive circuit outputs a high impedance state when receiving a high-level signal, and the pull-down drive circuit outputs a high impedance state when receiving a low-level signal. At this time, the pull-up drive circuit and the pull-down drive circuit have different requirements for control signals. That is, two sets of parallel-to-serial circuits are needed. When the memory does not read out data, the pull-up driving circuit receives an invalid level, and the pull-down driving circuit receives an invalid level, so that the DQ end maintains a high-impedance output.

[0057] Through the scheme of the embodiment of the present disclosure, since the timing of the state switching of the termination resistor RTT is the same as the timing of the output data of the read operation, the timing of the state switching of the termination resistor RTT (the termination resistor control timing) is used to control the pull-up drive circuit 141, so that the pull-up resistor control circuit can directly configure the termination resistance value of the pull-up drive circuit (and keep the DQ end in a high-impedance output) during non-read operations. Therefore, the pull-up drive circuit and the pull-down drive circuit can be connected to the same parallel-to-serial circuit (that is, the parallel-to-serial circuit only needs to keep the output of the pull-down drive circuit in a high-impedance state), thereby realizing the multiplexing of the parallel-to-serial circuit. Under the premise of ensuring the normal operation of the circuit, the circuit area can be further saved.

[0058] In some embodiments, reference Figure 2 The parallel-to-serial circuit 110 may include a first data input port D0, a second data input port D1, a third data input port D2, and a fourth data input port D3. The parallel-to-serial circuit 110 receives N data D0-D0 through the first to fourth data input ports D0-D3. N-1 The inverted signal D0B-D N-1 B; the parallel-to-serial circuit also receives a first clock CLK0D, a second clock CLK1D, a third clock CLK2D, and a fourth clock CLK3D, and based on the first to fourth clocks CLK0D-CLK3D, the N data D0-D N-1 The inverted signal D0B-D N-1 B sampling, and serially output N data in the first time period T1. Figure 4, the clock frequencies of the first clock CLK0D, the second clock CLK1D, the third clock CLK2D, and the fourth clock CLK3D are the same, and the phase difference is one quarter of a cycle. In some embodiments, N can be a positive integer multiple of 4, such as 4, 8, 16, 32, and the first to fourth data input ports D0-D3 receive N data D0-D3 in sequence. N-1 The inverted signal is sampled alternately by the first to fourth clocks CLK0D-CLK3D. In other embodiments, N may not be a positive integer multiple of 4, and only normal sampling is required, and then the redundant data is shielded. For example, N may be 15, and the last sampled data is regarded as invalid data.

[0059] For illustrative reference only Figure 4 , the first time period T1 includes the second time period T2, the third time period T3, and the fourth time period T4, the second time period T2 is earlier than the third time period T3, and the third time period T3 is earlier than the fourth time period T4; the parallel-to-serial circuit is further configured to: fixedly output the first level in the second time period and the fourth time period, and serially output N data in the third time period. In some embodiments, the first level can be a high level; correspondingly, the high level enters the pull-up output circuit composed of the PMOS tube and the pull-down output circuit composed of the NMOS tube at the DQ end through inversion, so that the pull-up output circuit outputs a high level at the DQ end in the second time period T2 and the fourth time period T4, and the pull-down output circuit outputs a high impedance state in the second time period T2 and the fourth time period T4. In other embodiments, the first level may also be a low level; correspondingly, the low level enters the pull-up output circuit composed of a PMOS transistor and the pull-down output circuit composed of an NMOS transistor at the DQ terminal without being inverted, so that the pull-up output circuit outputs a high level at the DQ terminal in the second time period T2 and the fourth time period T4, and the pull-down output circuit outputs a high impedance state at the DQ terminal in the second time period T2 and the fourth time period T4. In other embodiments, the pull-up output circuit may also be composed of an NMOS transistor, and / or the pull-down output circuit may also be composed of a PMOS transistor. In this case, the high level may enter the pull-up output circuit and / or the pull-down output circuit without being inverted to output a high impedance state at the DQ terminal, and the low level may enter the pull-up output circuit and / or the pull-down output circuit after being inverted to output a high impedance state at the DQ terminal.

[0060] In other embodiments, the first time period T1 also includes other time periods in addition to the second time period T2, the third time period T3, and the fourth time period T4, that is, the second time period T2 and the third time period T3 may be discontinuous, and the third time period T3 and the fourth time period T4 may be discontinuous.

[0061] In some embodiments, the length of the second time period is a unit time interval (1 UI, 1 UnitInterval), the length of the fourth time period is a unit time interval (1 UI), and the N data D0-D N-1 The width of each data in is also 1 UI to facilitate the measurement of tADC.

[0062] Therefore, by setting the second time period and the fourth time period and outputting a fixed level in the second time period and the fourth time period, the preset information of tADC measurement can be manually set before and after the N data are output, so as to measure whether tADC meets the requirements.

[0063] Figure 3 A schematic diagram of the structure of a parallel-to-serial circuit provided in an embodiment of the present disclosure. Figure 4 The timing diagram of the parallel-to-serial circuit is shown in Figure 2. Figure 3 The parallel-to-serial circuit 110 includes a first sampling circuit 111, a second sampling circuit 112, and a first NAND gate NAND1. The first input end of the first sampling circuit 111 receives the first clock CLK0D, and the second input end of the first sampling circuit is connected to the first data input port D0 to receive data input from the first data input port D0, and samples the data input from the first data input port D0 through the first clock CLK0D.

[0064] Figure 4 Taking N=16 as an example, the first data input port D0 transmits data D0, D4, D8, D 12 The inverted signals D0B, D4B, D8B, D 12 B, and defaults to a low level L when no data is transmitted. The first clock CLK0D samples these signals in sequence to obtain a sampling result CLKD0. Figure 3 In the figure, the first sampling circuit 111 is illustrated as an AND gate (NAND gate + NOT gate). In other embodiments, all sampling circuits including the first sampling circuit may also adopt sampling circuits such as OR gates (NOR gates and NOT gates), and triggers (such as D triggers).

[0065] The first input end of the second sampling circuit 112 receives the second clock CLK1D, the second input end of the second sampling circuit 112 receives the second level Vdd, samples the second level Vdd through the second clock CLK1D, and inverts the sampled data. The first input end of the first NAND gate NAND1 is connected to the output end of the first sampling circuit 111, and receives the sampling result CLKD0 output by the first sampling circuit; the second input end of the first NAND gate NAND1 is connected to the output end of the second sampling circuit 112, and receives the sampling result CLKB0 output by the second sampling circuit; the first NAND gate performs a NAND operation on CLKD0 and CLKB0, and outputs the first sampling result Sample_0.

[0066] When the second sampling circuit is an AND gate, the second level Vdd is correspondingly set to a high level H. In other embodiments, the second level may be a low level, and correspondingly, the second sampling circuit uses an OR gate, and the second sampling circuit does not perform inversion processing on the sampling result.

[0067] The parallel-to-serial circuit 110 further includes a third sampling circuit 113, a fourth sampling circuit 114, and a second NAND gate NAND2; a first input end of the third sampling circuit 113 receives a third clock CLK2D, a second input end of the third sampling circuit 113 is connected to a third data input port D2, receives data input from the third data input port D2, and processes the data input from the third data input port D2 through the third clock CLK2D. Figure 4 D2, D6, D 10 , D 14 For example), sampling is performed to obtain a sampling result CLKD2; the first input end of the fourth sampling circuit 114 receives the fourth clock CLK3D, the second input end of the fourth sampling circuit 114 receives the second level Vdd, the second level Vdd is sampled by the fourth clock CLK3D, and then inverted to obtain a sampling result CLKB2; the first input end of the second NAND gate NAND2 is connected to the output end of the third sampling circuit 113 to receive the sampling result CLKD2 outputted by it, the second input end of the second NAND gate is connected to the output end of the fourth sampling circuit to receive the sampling result CLKB2 outputted by it, the second NAND gate NAND2 performs a NAND logic process on CLKD2 and CLKB2, and outputs a third sampling result Sample_2.

[0068] The parallel-to-serial circuit further includes a fifth sampling circuit 115, a sixth sampling circuit 116, and a third NAND gate NAND3; the first input end of the fifth sampling circuit 115 receives the second clock CLK1D, and the second input end of the fifth sampling circuit 115 is connected to the second data input port D1 to receive the data input from the second data input port D1 ( Figure 4 D1, D5, D9, D 13For example), the data input from the second data input port D1 is sampled by the second clock CLK1D to obtain a sampling result CLKD1; the first input end of the sixth sampling circuit 116 receives the third clock CLK2D, the second input end of the sixth sampling circuit 116 receives the second level Vdd, the second level Vdd is sampled by the third clock CLK2D, and then inverted to obtain a sampling result CLKB1; the first input end of the third NAND gate NAND3 is connected to the output end of the fifth sampling circuit 115 to receive the sampling result CLKD1 outputted by it, the second input end of the third NAND gate NAND3 is connected to the output end of the sixth sampling circuit 116 to receive the sampling result CLKB1 outputted by it, the third NAND gate NAND3 performs a NAND logic process on CLKD1 and CLKB1, and outputs a second sampling result Sample_1.

[0069] The parallel-to-serial circuit 110 further includes a seventh sampling circuit 117, an eighth sampling circuit 118, and a fourth NAND gate NAND4; a first input end of the seventh sampling circuit 117 receives a fourth clock CLK3D, and a second input end of the seventh sampling circuit 117 is connected to a fourth data input port D3 to receive data input from the fourth data input port D3 ( Figure 4 D3, D7, D 11 , D 15 For example), the data input from the fourth data input port D3 is sampled by the fourth clock CLK3D to obtain a sampling result CLKD3; the first input end of the eighth sampling circuit 118 receives the first clock CLK0D, the second input end of the eighth sampling circuit 118 receives the second level Vdd, and the second level Vdd is sampled by the first clock CLK0D to obtain a sampling result CLKB3; the first input end of the fourth NAND gate NAND4 is connected to the output end of the seventh sampling circuit 117 to receive the sampling result CLKD3 outputted by the seventh sampling circuit 117, the second input end of the fourth NAND gate NAND4 is connected to the output end of the eighth sampling circuit 118 to receive the sampling result CLKB3 outputted by the eighth sampling circuit 118, the fourth NAND gate NAND4 performs a NAND logic process on CLKD3 and CLKB3, and outputs a fourth sampling result Sample_3.

[0070] The above takes an AND logic circuit as an example of a sampling circuit, but it should be understood that an OR logic circuit, a timing circuit (such as a trigger circuit, specifically, a D trigger circuit) can also implement the above sampling logic, thereby serving as other embodiments of the sampling logic circuit.

[0071] The parallel-to-serial circuit 110 further includes a first AND logic circuit 119, which is connected to the output ends of the first to fourth NAND gates NAND1-NAND4, receives the first to fourth sampling results Sample_0-Sample_3 output by the first to fourth NAND gates NAND1-NAND4, and performs a first AND logic process on the first to fourth sampling results, thereby outputting a first level in the second time period and the fourth time period, and serially outputting N data in the third time period. Figure 3 and 4 In the embodiment of the present invention, the first level is a high level H. Figure 3 In the example, a combination of multiple two-input NAND gates is used to implement AND logic. In other embodiments, AND logic can also be directly implemented by, for example, a four-input NAND gate.

[0072] refer to Figure 4 , CLK is the external clock cycle, and CL time point is the time point when the memory starts to output data. Starting from CL time point, the first to fourth data input ports D0-D3 start to receive N data one after another. Figure 4 Taking N=16 as an example, starting from the time point CL, the first data input port D0 starts to receive data D0, D4, D8, D 12 The inverted signals D0B, D4B, D8B, D 12 B, in addition, except for the moment of data transmission, the data signal defaults to the transmission low level L. The data width of each data is 2T, where T is the external clock cycle, and each half of the external clock cycle is a unit time interval of 1 UI. Among the N data, the interval between each adjacent two data is 1 UI, so the second data input port D1 starts to receive data D1, D5, D9, D1 from CL+1 UI. 13 The inverted signals D1B, D5B, D9B, D 13 B, the third data input port D2 starts to receive data D2, D6, D 10 , D 14 The inverted signals D2B, D6B, D 10 B.D 14 B, the fourth data input port D3 starts to receive data D3, D7, D 11 , D 15 The inverted signals D3B, D7B, D 11 B.D 15 B, the data width of each data is 2T.

[0073] Correspondingly, the clock cycles of the first to fourth clocks CLK0D-CLK3D are also 2T, and the timings differ by 1 UI. After sampling, the data width of each sampling result CLKD0-CLKB3 is 1T. Subsequently, the width of the sampling result is aligned with the clock that is 1 UI apart from the sampling clock, and the sampling results Sample_0-Sample_3 with a data width of 1 UI are obtained.

[0074] That is, first use the four-phase clock (the first to fourth clock CLK0D-CLK3D) to sample N data in sequence, and then align the width of the sampling result with the clock that is 1 UI apart from the sampling clock to obtain the first to fourth sampling results Sample_0-Sample_3, in which the width of each data is 1 UI. In addition, the first to fourth sampling results Sample_0-Sample_3 carry the phase information of the clock. After the data is merged through the first AND logic processing, the parallel-to-serial processing of the data can be completed, and N data are output in series in sequence with a data width of 1 UI. In addition, the circuit outputs a high level as the default state when the clock and data are not transmitted, so that the subsequent output drive circuit can default to a high-impedance output when no data is transmitted.

[0075] Figure 5 A structural schematic diagram of a read enable signal generating circuit is shown. Figure 6 The timing diagram of the read enable signal generating circuit is shown. The read enable signal generating circuit 120 includes an even reset signal sampling circuit FF1, an odd reset signal sampling circuit FF2, and a read enable signal NAND gate NANDR;

[0076] The even reset signal sampling circuit takes a D flip-flop (DFF) as an example. The data input end of the even reset signal sampling circuit FF1 receives the even reset signal TRST_EVEN with ODT timing information, and the clock input end receives the corresponding even sampling clock signal CK1, and samples the even reset signal TRST_EVEN through the even sampling clock signal CK1 to match the data output timing of the parallel-to-serial circuit to obtain an even sampling result;

[0077] The odd reset signal sampling circuit also takes a D flip-flop (DFF) as an example. The data input end of the odd reset signal sampling circuit FF2 receives the odd reset signal TRST_ODD with ODT timing information, and the clock input end receives the odd sampling clock signal CK3. CK1 and CK3 are differential clock signals, and the odd reset signal TRST_ODD is sampled by the odd sampling clock signal CK3 to match the data output timing of the parallel-to-serial circuit to obtain an odd sampling result.

[0078] The read enable signal NAND gate NANDR receives the even sampling result and the odd sampling result, performs AND logic processing on the even sampling result and the odd sampling result, and merges the odd and even paths to obtain a read enable signal that matches the timing of the parallel-to-serial circuit. The read enable signal continues to be at a valid level from the first UI of the data output ( Figure 6 The valid level ends 1 UI after the data output is completed and the signal jumps to the invalid level.

[0079] The odd reset signal and the even reset signal are processing signals of the odd and even paths during internal processing. When data is output, the odd and even paths need to be merged. Figure 6 In the example, the data is read out using the even reset signal TRST_EVEN. First, a total of four data paths enter the parallel-to-serial circuit from the first to fourth data ports D0-D3 in sequence, and the phase difference between the four data paths is 1UI. If the first data entering D0 is the first bit of data read out, and the burst length (BL, Burst Length) is 16, then the even reset signal TRST_EVEN is valid from the CL time point, and the odd reset signal TRST_ODD is valid from the CL-1 (T) time point, and the pulse widths of the odd reset signal TRST_ODD and the even reset signal TRST_EVEN are both 8 T (8 external clock cycles). The sampling clock CK1 has the same source and frequency as the first clock, and is 1 UI earlier than the first clock CK0D. CK1 or CK3 starts sampling data at CL-0.5 (T). In the embodiment where the even reset signal TRST_EVEN reads data first, CK1 starts sampling data at CL-0.5 (T); if the odd reset signal TRST_ODD reads data first, CK3 starts sampling data at CL-0.5 (T). After the data is merged by the NAND gate, a pulse signal with a width of 9T and a valid level from CL-0.5 to CL+8.5 (T) is generated.

[0080] In other embodiments, the read enable signal generating circuit may also be generated by other circuits, and it is only necessary to ensure that a pulse signal with a valid level from CL-0.5 to CL+8.5 (T) is generated to ensure that the data signal entering the driving circuit matches the control signal timing.

[0081] In some embodiments, Figure 2 As shown, the resistance control circuit 130 includes a first selection circuit 1311 . Figure 7 A schematic diagram of the structure of a first selection circuit provided in an embodiment of the present disclosure. Figure 8 Schematic diagram of a first selection circuit. Figure 7As shown, the first selection circuit 1311 is configured to: receive the termination resistance control code ODT, the output drive resistance control code RON and the read enable signal Read_enable; when the read enable signal Read_enable is at a valid level, the output end of the first selection circuit 1311 outputs the output drive resistance control code RON as the output signal RON_ODT_CTL of the first selection circuit 1311; when the read enable signal Read_enable is at an invalid level, the output end of the first selection circuit 1311 outputs the termination resistance control code ODT as the output signal RON_ODT_CTL of the first selection circuit 1311.

[0082] It should be understood that, in order to improve signal quality, driving devices such as inverters are provided at various locations in the digital circuit to improve driving capability. Since a signal and its inverted signal can be easily converted with only one inverter, and the driving signals of the PMOS tube and the NMOS tube are inverted, in the embodiments of the present disclosure, unless otherwise specified, multiple input signals or output signals can be replaced with their inverted signals. For example, Figure 7 In the example, the signal RON_ODT_CTL passes through two stages of inverters when it is output, but based on the need for driving capability, one stage of the inverter can also be set on the subsequent path. Therefore, the signal RON_ODT_CTL can also be set with only one stage of inverter when it is output, so that the output signal is its inverted signal.

[0083] refer to Figure 8 , Figure 8 Taking the high level as an example of the effective level, when the read enable signal Read_enable is an invalid level (that is, before the data starts to be read out), the output signal RON_ODT_CTL of the first selection circuit 1311 (also used as the output signal of the resistance control circuit) is the termination resistance control code ODT; when the read enable signal Read_enable is an effective level (that is, when the data is read out), the output signal RON_ODT_CTL of the first selection circuit 1311 (also used as the output signal of the resistance control circuit) is the inverted signal of the output drive resistance control code RON; when the read enable signal Read_enable is an invalid level (that is, after the data is finished being read out), the output signal RON_ODT_CTL of the first selection circuit 1311 (also used as the output signal of the resistance control circuit) is the termination resistance control code ODT. As a result, the resistance control circuit automatically outputs different control codes in the read phase (Read) and the non-read phase (Termination), so as to match the different impedances that need to be set in different operation phases of the memory (such as the read and non-read phases).

[0084] Figure 8 The timing can be Figure 7 Circuit implementation. Figure 7 The first selection circuit 1311 includes a fifth NAND gate NAND5, a sixth NAND gate NAND6 and a seventh NAND gate NAND7; the first input end of the fifth NAND gate NAND5 receives the read enable signal Read_enable, and the second input end of the fifth NAND gate NAND5 receives the output drive resistance control code RON or its inverted signal RONB; the first input end of the sixth NAND gate NAND6 receives the inverted signal of the read enable signal Read_enable, and the second input end of the sixth NAND gate NAND6 receives the termination resistance control code ODT; the two input ends of the seventh NAND gate NAND7 are respectively connected to the output end of the fifth NAND gate NAND5 and the output end of the sixth NAND gate NAND6, and the output end of the seventh NAND gate NAND7 serves as the output end of the first selection circuit 1311.

[0085] In some embodiments, in order to match the gate delay caused by the inverter before the first input terminal of the sixth NAND gate NAND6, the read enable signal Read_enable is connected to the input terminal of the fifth NAND gate NAND5 after passing through a transmission gate or other timing-matched gate delay.

[0086] In some embodiments, the first selection circuit can also be implemented by a two-choice multiplexer. The read enable signal Read_enable is used as the input signal of the selection end, and the two input ends receive the termination resistance control code ODT and the output drive resistance control code RON respectively, so that the output drive resistance control code RON is output when the read enable signal Read_enable is at a valid level, and the termination resistance control code ODT is output when the read enable signal Read_enable is at an invalid level. In other embodiments, the first selection circuit can also be implemented by a NOR gate. The fifth to seventh NAND gates are all replaced with NOR gates, and the corresponding input signals or output signals are inverted, so as to achieve the requirement that the read enable signal Read_enable selects the output signal. The selection circuit implemented by the NAND gate or the NOR gate can match the timing and avoid the MOS tube superposition effect in high-speed circuits.

[0087] The termination resistance control code ODT and the output drive resistance control code RON can be codewords sent by the memory controller to the memory, and the memory sends them to the data input and output circuit through the register. The termination resistance control code ODT can be a multi-bit control codeword, such as 3 bits; the output drive resistance control code RON can be a multi-bit control codeword, such as 2 bits. Correspondingly, the resistance control circuit can have multiple first selection circuits, corresponding to receiving multi-bit control codewords. For example, the resistance control circuit can include four first selection circuits, thereby outputting multiple termination resistance control code ODT codewords and output drive resistance control code RON codewords, thereby setting different termination resistance values ​​and output drive resistance values.

[0088] In some embodiments, Figure 2 As shown, the output drive circuit includes pull-up drive circuits 141, 143 and pull-down drive circuits 142, 144, and the resistance control circuit 130 includes a pull-up resistance control circuit 131 and a pull-down resistance control circuit 132. The pull-up resistance control circuit 131 may include a plurality of first selection circuits, and correspondingly, the output drive resistance control code RON received by the first selection circuit 1311 is the pull-up output drive resistance control code Pu_Ron. The pull-down resistance control circuit 132 may also include a plurality of second selection circuits, and correspondingly, the output drive resistance control code RON received by the second selection circuit is the pull-down output drive resistance control code Pd_Ron. For a pull-up terminated memory, when it is used as a termination resistor, only the pull-up drive circuit outputs the termination resistance value, and the pull-down drive circuit is in a high impedance state.

[0089] At this time, the resistance control circuit 130 includes a pull-up resistance control circuit, and the pull-up resistance control circuit includes a first selection circuit 1311. The first selection circuit 1311 is configured to: receive the termination resistance control code ODT, the output drive resistance control code RON and the read enable signal Read_enable, when the read enable signal Read_enable is at a valid level, the output end of the first selection circuit 1311 outputs the output drive resistance control code RON or its inverted signal to the pull-up drive circuit; when the read enable signal Read_enable is at an invalid level, the output end of the first selection circuit 1311 outputs the termination resistance control code ODT or its inverted signal to the pull-up drive circuit;

[0090] The resistance control circuit 130 is a pull-down resistance control circuit, and the pull-down resistance control circuit includes a second selection circuit 1321. The second selection circuit 1321 is configured to: receive the termination resistance control code ODT, the output drive resistance control code RON and the read enable signal Read_enable. When the read enable signal Read_enable is at a valid level, the output end of the second selection circuit 1321 outputs the output drive resistance control code RON or its inverted signal RONB to the pull-down drive circuit; when the read enable signal is at an invalid level, the output end of the second selection circuit outputs an invalid level to the pull-down drive circuit. In an embodiment of the pull-down drive circuit composed of an NMOS tube, the invalid level can be a low level, so that the pull-down drive circuit composed of the NMOS tube is not turned on, the output is in a floating state, and the output is in a high impedance state.

[0091] Fig. 9A schematic diagram of the circuit structure of a second selection circuit 1321 is shown. The second selection circuit 1321 may include an eighth NAND gate NAND8, a ninth NAND gate NAND9, and a tenth NAND gate NAND10; the first input end of the eighth NAND gate NAND8 receives the read enable signal Read_enable through a transmission gate, and the second input end of the eighth NAND gate NAND8 receives the output drive resistance control code RON or its inverted signal RONB; the first input end of the ninth NAND gate NAND9 receives the inverted signal of the read enable signal Read_enable, and the second input end of the ninth NAND gate NAND9 receives an invalid level (in some embodiments, the invalid level may be a low level Vss); the two input ends of the tenth NAND gate NAND10 are respectively connected to the output end of the eighth NAND gate NAND8 and the output end of the ninth NAND gate NAND9, and the output end of the tenth NAND gate NAND10 serves as the output end of the second selection circuit 1321, and outputs the signal RON_PD_CTL.

[0092] In other embodiments, for a pull-down terminated memory, the opposite setting to the above can be made. The signal of the termination resistance code ODT input corresponding to the pull-up drive resistor selection circuit is an invalid level, and the signal of the termination resistance code ODT input corresponding to the pull-down drive circuit selection circuit is the code value of ODT.

[0093] like Figure 2 As shown, the output drive circuit includes pre-drive circuits 141, 142 and main drive circuits 143, 144. The pre-drive circuit includes a pull-up pre-drive circuit 141 and a pull-down pre-drive circuit 142, and the main drive circuit includes a pull-up main drive circuit 143 and a pull-down main drive circuit 144. The pull-up pre-drive circuit 141 is connected to the parallel-to-serial circuit 110 and the pull-up resistor control circuit 131, and receives the data signal DATA and the control code output by the pull-up resistor control circuit 131; the pull-down pre-drive circuit 142 is connected to the parallel-to-serial circuit 110 and the pull-down resistor control circuit 132, and receives the data signal DATA and the signal output by the pull-down resistor control circuit 132; the pull-up main drive circuit 143 is connected to the pull-up pre-drive circuit 141, and receives the pre-drive signal PU output by the pull-up pre-drive circuit 141; the pull-down main drive circuit 144 is connected to the pull-down pre-drive circuit 142, and receives the pre-drive signal PD output by the pull-down pre-drive circuit 142.

[0094] The pre-drive circuits 141 and 142 include a second AND logic circuit, a first input end of the second AND logic circuit receives N data DATA in series, and a second input end of the second AND logic circuit receives a signal (RON_ODT_CTL or RON_PD_CTL) output by the resistance control circuit; the second AND logic circuit performs AND-NOT logic processing on the signal received by its first input end and the signal received by its second input end, and then outputs the signal; the main drive circuit 143 includes a PMOS transistor electrically connected between the power supply voltage Vdd and the output port DQ, and the control end of the PMOS transistor receives the signal output by the second AND logic circuit; or, the second AND logic circuit performs AND logic processing on the signal received by its first input end and the signal received by the second input end, and then outputs the signal; the main drive circuit 144 includes an NMOS transistor electrically connected between the power supply voltage Vss and the output port DQ, and the control end of the NMOS transistor receives the signal output by the second AND logic circuit.

[0095] Specifically, refer to Fig.10 , Fig.10 The present invention provides a schematic diagram of the structure of a pull-up pre-driver circuit provided by an embodiment of the present invention. The pull-up pre-driver circuit includes a plurality of second AND logic circuits 1411, wherein the first input end of the second AND logic circuit 1411 receives N data (DATA) in series, and the second input end of the second AND logic circuit 1411 receives one bit of the control code RON_ODT_CTL output by the pull-up resistor control circuit 131 (such as RON_ODT_CTL0 shown in 1411, indicating the lowest bit of the control code RON_ODT_CTL output by the pull-up resistor control circuit 131); the second AND logic circuit 1411 performs AND-NOT logic processing on the signal received by its first input end and the signal received by its second input end, and then processes the signal in a manner similar to Fig.10 After the even number of inverters shown are driven, the pull-up data signal ( Fig.10 In some embodiments, the second AND logic circuit 1411 can directly output the pull-up data signal PU_0 after performing AND-NOT logic processing on the signal received at its first input terminal and the signal received at its second input terminal, without passing through an even number of inverters.

[0096] The pull-up main driving circuit 143 includes a plurality of sub-pull-up main driving circuits. Fig.11 FIG. 1 is a schematic diagram of a first sub-pull-up main driving circuit provided by an embodiment of the present disclosure. Fig.11 As shown, the first sub pull-up main driving circuit 1431 includes a PMOS transistor electrically connected between a power supply voltage Vdd (a high level power supply voltage) and an output port DQ, and a control terminal of the PMOS transistor receives a data signal PU_0 output by the second AND logic circuit.

[0097] refer to Fig.10 The second AND logic circuit 1411 also performs AND logic processing on the serial data signal DATA and the signal RON_ODT_CTL1 output by the pull-up resistor control circuit 131, and performs AND logic processing on the result of the AND logic processing and the ZQ calibration code ZQ_CODE<5:0> for calibrating the ZQ resistor of the main drive circuit to obtain the processed ZQ calibration code ZQ_0<5:0>. The calibrated ZQ calibration code ZQ_0<5:0> is sent to the main drive circuit for calibrating the ZQ resistor of the main drive circuit. By performing AND logic processing on the ZQ calibration code and the signal RON_ODT_CTL output by the pull-up resistor control circuit 131, the ZQ calibration code carries the timing information of the read operation and the non-read operation, so that the ZQ resistance path of the main drive circuit can be closed during the read operation to save power consumption.

[0098] refer to Fig.11 , the first sub-pull-up main driving circuit 1431 includes a data output path (the path where the PMOS1 transistor is located) and a ZQ resistance path (the path where the P0-P5 transistors are located). The data output path is used to receive the pull-up data signal PU_0 output by the pre-driving circuit and output data. The ZQ resistance path receives the processed ZQ calibration code ZQ_0<5:0>, which is used to adjust the resistance of the first sub-pull-up main driving circuit 1431 so that the resistance value of the first sub-pull-up main driving circuit 1431 is 240 ohms. Both the data output path and the ZQ circuit path have resistors for adjusting the linearity of the path.

[0099] A second AND logic circuit 1411 is used to drive a corresponding first sub-pull-up main driving circuit 1431. In some embodiments, the pull-up pre-driving circuit 141 includes 7 second AND logic circuits, the pull-up main driving circuit 143 includes 7 sub-pull-up main driving circuits, and the 7 second AND logic circuits correspond to the 7 sub-pull-up main driving circuits.

[0100] Through the design of the above-mentioned pull-up drive circuits 141 and 143, when the memory enters the state of reading data, the resistance control circuit output signal RON_ODT_CTL is the pull-up output drive resistance control code Pu_Ron, and its control codeword is used to control the path of the pull-up drive circuit. When Pu_Ron=0, the output of the pull-up pre-drive circuit is a high level, and the output of the pull-up drive circuit is a high impedance state. When Pu_Ron=1, the output of the pull-up drive circuit is a data signal DATA. When the memory enters a non-read state (such as a termination resistor ODT state), the resistance control circuit output signal RON_ODT_CTL is a termination resistor control code ODT. Since the parallel-to-serial circuit output is the default value "1" at this time, when the termination resistor control codeword ODT is equal to 1, the output of the pull-up pre-drive circuit is 0, and the corresponding pull-up main drive circuit is turned on as a pull-up resistor. When the termination resistor control codeword ODT is equal to 0, the output of the pull-up pre-drive circuit is 1, and the pull-up main drive circuit outputs a high impedance state.

[0101] As a result, the pull-up pre-drive circuit can send the data to the pull-up main drive circuit without deviation, and then the pull-up main drive circuit outputs the data. When the data is "0", the pull-up main drive circuit will be turned on, and when it is "1", the pull-up main drive circuit will be turned off. Since the pull-up pre-drive circuit will combine the output signal of the resistance control circuit, the data transmission process of the pull-up pre-drive circuit includes the timing of read operation and non-read operation, and the output drive resistance value can be automatically set or the termination resistance value can be configured while transmitting data. When the output signal (control code) of the resistance control circuit is "1", the data output by the parallel-to-serial circuit can be passed to the pull-up main drive circuit through the pull-up pre-drive circuit. On the contrary, if the output signal (control code) of the resistance control circuit is "0", the data output by the parallel-to-serial circuit will be ignored, and the pull-up main drive circuit will be directly turned off. Furthermore, the output signals (control codes) of the parallel-to-serial circuit, the pull-up pre-driver circuit and the resistor control circuit are combined. In the reading process, the output function can be realized by connecting one parallel-to-serial circuit to the pull-up output driver and the pull-down output driver circuit. Also, because only one read enable signal Read_enable is used, the deviation of tADC can be reduced.

[0102] For the pull-down pre-drive circuit and the pull-down main drive circuit, the same Fig.10 and Fig.11Corresponding circuit structure. Exemplarily, the pull-down pre-drive circuit may include a second AND logic circuit, the first input end of the second AND logic circuit receives N data (DATA) in series, and the second input end of the second AND logic circuit receives one bit of the control code RON_PD_CTL output by the pull-down resistor control circuit 132; the second AND logic circuit performs AND logic processing on the signal received by its first input end and the signal received by its second input end, and then outputs it to the pull-down main drive circuit 144. The pull-down main drive circuit 144 includes a plurality of sub-pull-down main drive circuits, and the sub-pull-down main drive circuit includes a data output path and a ZQ resistance path composed of NMOS tubes. Specifically, the sub-pull-down main drive circuit includes an NMOS transistor electrically connected between the power supply voltage Vss (low-level power supply voltage D) and the output port DQ and a resistor for improving linearity, the control end of the NMOS transistor of the data output path receives the signal output by the second AND logic circuit, and the control end of the NMOS transistor of the ZQ resistance path receives the processed ZQ calibration code.

[0103] In other embodiments, Fig.10 The NAND gate in the pull-up pre-driver circuit can be replaced by a NOR gate processing logic. In this case, the input control code RON_PD_CTL can be Figure 7 The inverted signal of the output signal in.

[0104] like Figure 2 As shown, the pull-up driving circuits 141 and 143 are connected to the output end of the parallel-to-serial circuit 110, and receive N data DATA within the first time period T1; the pull-down driving circuits 142 and 144 are connected to the output end of the parallel-to-serial circuit 110, and receive N data DATA within the first time period T1; the pull-up driving circuits 141 and 143 are configured to: output the high level of the N data within the first time period T1, and configure the output driving resistance value based on the output driving resistance control code RON; the pull-down driving circuits 142 and 144 are configured to: output the low level of the N data DATA within the first time period, and configure the output driving resistance value based on the output driving resistance control code ODT; the pull-up driving circuit is also configured to: configure the termination resistance value outside the first time period T1.

[0105] Thus, the pull-up driving circuit and the pull-down driving circuit are connected to the same parallel-to-serial circuit to output data, and at the same time, the output driving resistance value can be configured in the read operation and the termination resistance value can be configured in the non-read operation device.

[0106] The embodiment of the present disclosure also provides a memory. Fig.12 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure. Fig.12The memory 10 includes the input / output circuit 100 described in any of the above embodiments. The memory 10 also includes a storage array 20 and a data transmission circuit 30. The storage array 20 is composed of a plurality of storage cells and is used to store data. The data transmission circuit 30 is used to perform various processing and transmission on the data when the data is written or read. When the memory 10 is read, the data DATA is read out through the storage array 20, transmitted through the data transmission circuit 30, and then output through the data input / output circuit 100.

[0107] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A data input / output circuit, characterized in that: It includes a parallel-to-serial circuit, a read enable signal generating circuit, a resistance control circuit and an output drive circuit; wherein, The parallel-to-serial circuit is configured to receive N data and output the N data in series within a first time period; wherein the first time period includes a second time period, a third time period, and a fourth time period, the second time period is earlier than the third time period, and the third time period is earlier than the fourth time period; the parallel-to-serial circuit is configured to: fixedly output a first level within the second time period and the fourth time period, and output the N data in series within the third time period; The read enable signal generating circuit is configured to generate a read enable signal, wherein the read enable signal is at a valid level in a first time period; The resistance control circuit is electrically connected to the read enable signal generating circuit, and is configured to receive a termination resistance control code, an output drive resistance control code, and the read enable signal, and select to output the termination resistance control code or the output drive resistance control code based on the read enable signal; The output driving circuit is electrically connected to the parallel-to-serial circuit and the resistance control circuit, and is configured to receive the N data and the signal output by the resistance control circuit, and configure the output driving resistance value and output the N data based on the signal output by the resistance control circuit, or configure the termination resistance value; Wherein, N is a positive integer greater than 1.

2. The data input / output circuit according to claim 1, characterized in that: The output driving circuit includes a pull-up driving circuit and a pull-down driving circuit. The parallel-to-serial circuit connects the pull-up driving circuit and the pull-down driving circuit and outputs the N data to the pull-up driving circuit and the pull-down driving circuit.

3. The data input / output circuit according to claim 1 or 2, characterized in that: The parallel-to-serial circuit comprises a first data input port, a second data input port, a third data input port, and a fourth data input port, and the parallel-to-serial circuit receives the N data through the first to fourth data input ports; the parallel-to-serial circuit also receives a first clock, a second clock, a third clock, and a fourth clock, and samples the N data based on the first to fourth clocks, and outputs the N data serially within a first time period; The clock frequencies of the first clock, the second clock, the third clock and the fourth clock are the same, and the phase differences thereof are respectively one quarter of a cycle; and N is a positive integer multiple of 4.

4. The data input / output circuit according to claim 3, characterized in that: The parallel-to-serial circuit comprises a first sampling circuit, a second sampling circuit, and a first NAND gate; the first input end of the first sampling circuit receives the first clock, the second input end of the first sampling circuit is connected to the first data input port, and the data input to the first data input port is sampled by the first clock; The first input terminal of the second sampling circuit receives the second clock, the second input terminal of the second sampling circuit receives the second level, and the second level is sampled by the second clock; A first input end of the first NAND gate is connected to an output end of the first sampling circuit, a second input end of the first NAND gate is connected to an output end of the second sampling circuit, and the first NAND gate outputs a first sampling result; The parallel-to-serial circuit further includes a third sampling circuit, a fourth sampling circuit, and a second NAND gate; the first input end of the third sampling circuit receives the third clock, the second input end of the third sampling circuit is connected to the third data input port, and the data input to the third data input port is sampled by the third clock; The first input terminal of the fourth sampling circuit receives the fourth clock, the second input terminal of the fourth sampling circuit receives the second level, and the second level is sampled by the fourth clock; The first input end of the second NAND gate is connected to the output end of the third sampling circuit, the second input end of the second NAND gate is connected to the output end of the fourth sampling circuit, and the second NAND gate outputs the third sampling result; The parallel-to-serial circuit further includes a fifth sampling circuit, a sixth sampling circuit, and a third NAND gate; the first input end of the fifth sampling circuit receives the second clock, the second input end of the fifth sampling circuit is connected to the second data input port, and the data input from the second data input port is sampled through the second clock; The first input terminal of the sixth sampling circuit receives the third clock, the second input terminal of the sixth sampling circuit receives the second level, and the second level is sampled by the third clock; The first input end of the third NAND gate is connected to the output end of the fifth sampling circuit, the second input end of the third NAND gate is connected to the output end of the sixth sampling circuit, and the third NAND gate outputs a second sampling result; The parallel-to-serial circuit further includes a seventh sampling circuit, an eighth sampling circuit, and a fourth NAND gate; the first input end of the seventh sampling circuit receives the fourth clock, the second input end of the seventh sampling circuit is connected to the fourth data input port, and the data input from the fourth data input port is sampled through the fourth clock; The first input terminal of the eighth sampling circuit receives the first clock, the second input terminal of the eighth sampling circuit receives the second level, and the second level is sampled by the first clock; The first input end of the fourth NAND gate is connected to the output end of the seventh sampling circuit, the second input end of the fourth NAND gate is connected to the output end of the eighth sampling circuit, and the fourth NAND gate outputs a fourth sampling result; A first AND logic circuit connects the first to fourth NAND gates, receives the first to fourth sampling results, and performs a first AND logic process on the first to fourth sampling results, thereby outputting the first level in a second time period and a fourth time period, and serially outputting the N data in a third time period.

5. The data input / output circuit according to claim 1 or 2, characterized in that: The resistance control circuit includes a first selection circuit, which is configured to: receive a termination resistance control code, an output drive resistance control code and the read enable signal, and when the read enable signal is at a valid level, the output end of the first selection circuit outputs the output drive resistance control code or its inverted signal; when the read enable signal is at an invalid level, the output end of the first selection circuit outputs the termination resistance control code.

6. The data input / output circuit according to claim 5, characterized in that: The first selection circuit includes a fifth NAND gate, a sixth NAND gate and a seventh NAND gate; the first input end of the fifth NAND gate receives a read enable signal, and the second input end of the fifth NAND gate receives an output drive resistance control code or an inverted signal thereof; The first input end of the sixth NAND gate receives the inverted signal of the read enable signal, and the second input end of the sixth NAND gate receives the termination resistance control code; the two input ends of the seventh NAND gate are respectively connected to the output end of the fifth NAND gate and the output end of the sixth NAND gate, and the output end of the seventh NAND gate serves as the output end of the first selection circuit.

7. The data input / output circuit according to claim 2, characterized in that: The resistance control circuit includes a first selection circuit, wherein the first selection circuit is configured to: receive a termination resistance control code, an output drive resistance control code and the read enable signal, and when the read enable signal is at a valid level, an output end of the first selection circuit outputs the output drive resistance control code or its inverted signal to the pull-up drive circuit; When the read enable signal is at an invalid level, the output end of the first selection circuit outputs the termination resistance control code or its inverted signal to the pull-up driving circuit; The resistance control circuit further includes a second selection circuit, the second selection circuit being configured to: receive an invalid level, an output drive resistance control code and the read enable signal, and when the read enable signal is at a valid level, an output terminal of the second selection circuit outputs the output drive resistance control code or its inverted signal to the pull-down drive circuit; When the read enable signal is at an invalid level, the output terminal of the second selection circuit outputs the invalid level to the pull-down driving circuit.

8. The data input / output circuit according to claim 1 or 2, characterized in that: The output driving circuit comprises a pre-driving circuit and a main driving circuit, the pre-driving circuit comprises a second AND logic circuit, a first input end of the second AND logic circuit receives the N data, and a second input end of the second AND logic circuit receives a signal output by the resistance control circuit; The second AND logic circuit performs a non-AND logic process on the signal received at its first input terminal and the signal received at its second input terminal and then outputs the signal; the main driving circuit comprises a PMOS transistor electrically connected between the power supply voltage and the output port, and the control terminal of the PMOS transistor receives the signal output by the second AND logic circuit; Alternatively, the second AND logic circuit performs AND logic processing on the signal received at its first input terminal and the signal received at its second input terminal and outputs the resultant signal, and the main drive circuit includes an NMOS transistor electrically connected between the power supply voltage and the output port, and the control terminal of the NMOS transistor receives the signal output by the second AND logic circuit.

9. The data input / output circuit according to claim 2, characterized in that: The pull-up driving circuit is connected to the output end of the parallel-to-serial circuit and receives the N data in a first time period; The pull-down driving circuit is connected to the output end of the parallel-to-serial circuit and receives the N data in a first time period; The pull-up driving circuit is configured to: output a high level of the N data in a first time period, and configure an output driving resistance value based on an output driving resistance control code; The pull-down driving circuit is configured to: output a low level of the N data in a first time period, and configure an output driving resistance value based on an output driving resistance control code; The pull-up driving circuit is further configured to: configure the termination resistance value outside the first time period.

10. A memory, characterized in that: The memory comprises the input / output circuit according to any one of claims 1 to 9, the memory further comprises a storage array and a data transmission circuit, the storage array stores data; When a read operation is performed on the memory, data is read out through the storage array, transmitted through the data transmission circuit, and then output through the data input / output circuit.

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