Wafer-level packaging method and wafer-level packaging structure

Abstract

The present invention discloses a wafer-level packaging method and a wafer-level packaging structure, which are applied to the field of wafer packaging technology, including: setting a through groove in the cutting path of the wafer; etching the cover plate to form a bottom corresponding to the wafer working area and a support portion corresponding to the wafer cutting path; the support portion and the bottom are an integrated structure, the width of the support portion is not greater than the width of the through groove, and the height of the support portion is greater than the depth of the through groove; the support portion is inserted into the through groove and bonded, so that the cover plate and the wafer are embedded and bonded to complete the packaging. By setting a support portion integrally formed with the bottom based on the cover plate, the sealed cavity is integrally formed by the cover plate, and the cover plate is specifically embedded in the interior of the wafer for bonding, so that it has high sealing performance and high bonding strength, and thus has high reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer packaging, and in particular to a wafer-level packaging method and a wafer-level packaging structure. Background Art

[0002] Filters have the advantages of small area, light weight, low loss and good frequency selectivity. The filter market is growing rapidly with the increase of wireless communication frequency bands. Filters are widely used in RF front-end chips. In the process of filter packaging, a cover plate is usually required, and a certain gap is left between the cover plate and the working area of ​​the wafer as a sealed cavity to ensure good performance of the filter.

[0003] However, in the prior art, the cover plate is usually formed of a multi-layer structure, which has the risk of insufficient sealing performance and insufficient reliability. Therefore, how to provide a wafer-level packaging method with good sealing performance and high reliability is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide a wafer-level packaging method and a wafer-level packaging structure, which have good sealing performance and high reliability.

[0005] In order to solve the above technical problems, the present invention provides a wafer-level packaging method, comprising:

[0006] A through groove is provided in a dicing path of the wafer;

[0007] The cover plate is etched to form a bottom corresponding to the wafer working area and a support portion corresponding to the wafer cutting path; the support portion and the bottom are an integrated structure, the width of the support portion is not greater than the width of the through groove, and the height of the support portion is greater than the depth of the through groove;

[0008] The support portion is inserted into the through groove and bonded, so that the cover plate is embedded and bonded to the wafer to complete the packaging.

[0009] Optionally, inserting the support portion into the through groove and bonding the support portion includes:

[0010] Disposing a printed bonding material at the end of the support portion and / or in the through groove;

[0011] After printing the bonding material, the support portion is inserted into the through groove, and a bonding layer is formed between the support portion and the through groove by the bonding material.

[0012] Optionally, the bonding layer fills the gap between the end surface of the support portion and the bottom surface of the through groove, and the gap between the side surface of the support portion and the side wall of the through groove.

[0013] Optionally, the bonding layer is an elastically deformable bonding adhesive layer.

[0014] Optionally, before providing the through groove in the dicing path of the wafer, the method further includes:

[0015] Arranging wafer bumps on the electrode surface of the wafer;

[0016] Before inserting the support portion into the through groove and bonding, the method further comprises:

[0017] A welding spot is arranged at a position of the cover plate corresponding to the wafer bump; the welding spot penetrates the bottom along the thickness direction;

[0018] Inserting the support portion into the through groove and bonding the support portion to embed the cover plate and the wafer comprises:

[0019] The support portion is inserted into the through groove and bonded, so that the cover plate and the wafer are embedded and bonded, and the wafer bumps and the solder joints are commutatively connected.

[0020] Optionally, setting a solder joint at a position of the cover plate corresponding to the wafer bump includes:

[0021] A blind hole is arranged on the surface of the bottom facing the side of the wafer, corresponding to the position of the wafer bump;

[0022] Filling the blind hole with a conductive material to form the solder joint;

[0023] After the support part is inserted into the through slot and bonded, the method further comprises:

[0024] The surface of the cover plate away from the wafer is thinned until the solder joint is exposed.

[0025] Optionally, after thinning the surface of the cover plate away from the wafer, the method further comprises:

[0026] A cover plate bump connected to the soldering point is arranged at a position where the soldering point is exposed on a surface of the cover plate away from the wafer.

[0027] Optionally, filling the blind hole with a conductive material to form the solder joint includes:

[0028] The blind hole is filled with conductive material until the conductive material protrudes out of the bottom and away from the surface of one side of the wafer, so as to form the solder joint.

[0029] Optionally, the sum of the height of the solder joint protruding from the bottom toward the surface of one side of the wafer and the height of the wafer bump is less than the height of the support portion.

[0030] The present invention also provides a wafer-level packaging structure, which is a wafer-level packaging structure prepared by any of the wafer-level packaging methods described above.

[0031] A wafer-level packaging method provided by the present invention includes: setting a through groove in the cutting path of the wafer; etching the cover plate to form a bottom corresponding to the wafer working area and a support part corresponding to the wafer cutting path; the support part and the bottom are an integrated structure, the width of the support part is not greater than the width of the through groove, and the height of the support part is greater than the depth of the through groove; inserting the support part into the through groove and bonding it, so that the cover plate and the wafer are embedded and bonded to complete the packaging.

[0032] By setting a support portion integrally formed with the bottom based on the cover plate, the sealed cavity is integrally formed by the cover plate, and the cover plate is specifically embedded into the interior of the wafer for bonding, so that it has high sealing performance and high bonding strength, thereby having high reliability.

[0033] The present invention also provides a wafer-level packaging structure, which also has the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] FIG1 is a flowchart of a wafer-level packaging method provided by an embodiment of the present invention;

[0036] Figure 2 to Fig.10 A process flow chart of a specific wafer-level packaging method provided by an embodiment of the present invention.

[0037] In the figure: 101. wafer, 102. electrode, 103. functional area, 104. wafer bump, 105. through groove, 201. cover plate, 202. bottom, 203. support part, 204. blind hole, 205. solder joint, 206. cover plate bump, 301. bonding layer. DETAILED DESCRIPTION

[0038] The core of the present invention is to provide a wafer-level packaging method. In the prior art, the cover plate is usually formed by a multi-layer structure, which has the risk of insufficient sealing performance and insufficient reliability.

[0039] The present invention provides a wafer-level packaging method, which includes: setting a through groove in the cutting path of the wafer; etching the cover plate to form a bottom corresponding to the wafer working area and a support portion corresponding to the wafer cutting path; the support portion and the bottom are an integrated structure, the width of the support portion is not greater than the width of the through groove, and the height of the support portion is greater than the depth of the through groove; inserting the support portion into the through groove and bonding it, so that the cover plate and the wafer are embedded and bonded to complete the packaging.

[0040] By setting a support portion integrally formed with the bottom based on the cover plate, the sealed cavity is integrally formed by the cover plate, and the cover plate is specifically embedded into the interior of the wafer for bonding, so that it has high sealing performance and high bonding strength, thereby having high reliability.

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0042] Embodiment 1

[0043] Please refer to FIG. 1 , which is a flowchart of a wafer-level packaging method provided by an embodiment of the present invention.

[0044] Referring to FIG. 1 , in an embodiment of the present invention, a wafer-level packaging method includes:

[0045] S101: a through groove is provided in a cutting path of a wafer.

[0046] Before this step, it is usually necessary to divide the surface of the wafer 101 into functional areas 103, electrical connection areas, and cutting paths, and set structures such as resonance areas in the functional areas 103, and set structures such as electrodes 102 in the electrical connection areas. The electrodes 102 usually need to be electrically connected to the resonance areas. Usually, the functional areas 103 are usually located in the center, the electrical connection areas are located at the edges of the functional areas 103, and the cutting paths surround the functional areas 103 and the electrical connection areas. The specific structures of the functional areas 103 and the electrical connection areas can be set according to actual conditions, and are not specifically limited here.

[0047] In this step, a through groove 105 can be set in the cutting path of the wafer 101 by laser cutting or mechanical cutting or a combination of the two. Obviously, the through groove 105 will not cut through the wafer 101 during the setting process, but only a part of the wafer 101 will be cut along the thickness direction to form the through groove 105. Generally speaking, the wafer 101 includes a plurality of chips, and a cutting path is formed around each chip of the wafer 101. In this embodiment, the through groove 105 is preferably set along the cutting path around the functional area 103 and the electrical connection area to improve the sealing and reliability of the final product.

[0048] S102: etching the cover plate to form a bottom corresponding to the wafer working area and a support portion corresponding to the wafer cutting path.

[0049] In the embodiment of the present invention, the support portion 203 and the bottom 202 are an integrated structure, the width of the support portion 203 is smaller than the width of the through slot 105 , and the height of the support portion 203 is greater than the depth of the through slot 105 .

[0050] In this step, a groove can be etched in the cover plate 201 by a wet etching process or a dry etching process. The bottom surface of the groove is the bottom 202, and the side wall of the groove is the support portion 203. The support portion 203 is usually arranged around the bottom 202. Since the bottom 202 and the support portion 203 are etched from the cover plate 201, the support portion 203 and the bottom 202 need to be an integrated structure to ensure the sealing of the two.

[0051] The size and position of the bottom 202 at least correspond to the size and position of the working area in the wafer 101, and the size and position of the support portion 203 need to correspond to the size and position of the through slot 105. Specifically, in this embodiment, the width of the support portion 203 needs to be no greater than the width of the through slot 105, and the height of the support portion 203 needs to be greater than the depth of the through slot 105, so that the support portion 203 can be embedded in the through slot 105, and after being embedded, a certain space can be left between the wafer 101 and the cover plate 201 to form a sealed cavity.

[0052] It should be noted that in this embodiment, the above processing process for the cover plate 201 and the processing process for the wafer 101 are not limited in order. This embodiment can execute the above S101 and S102 in any order, or execute the above S101 and S102 in parallel, and no specific limitation is made here.

[0053] S103: inserting the support part into the through groove and bonding it, so that the cover plate is embedded and bonded with the wafer to complete the packaging.

[0054] In this step, the support portion 203 is inserted into the through groove 105 for bonding, and the cover plate 201 is equivalent to partially embedding the wafer 101, thereby achieving embedded bonding between the two. Compared with merely bonding the support portion 203 on the surface of the wafer 101, embedding part of the support portion 203 into the cover plate 201 can greatly increase the bonding and sealing between the two. The embedded structure is usually arranged around the functional area 103 and the electrical connection area.

[0055] A wafer-level packaging method provided in this embodiment is characterized in that a support portion 203 integrally formed with a bottom 202 is provided based on a cover plate 201, so that a sealed cavity is integrally formed by the cover plate 201, and the cover plate 201 is specifically embedded in the interior of the wafer 101 for bonding, so that it has high sealing performance and high bonding strength, thereby having high reliability.

[0056] The specific contents of a wafer-level packaging method provided by the present invention will be described in detail in the following invention embodiments.

[0057] Embodiment 2

[0058] Please refer to Figures 2 to Fig.10 , Figure 2 to Fig.10 A process flow chart of a specific wafer-level packaging method provided by an embodiment of the present invention.

[0059] Referring to FIG. 2 , in an embodiment of the present invention, a wafer-level packaging method includes:

[0060] S201: Setting wafer bumps on the electrode surface of the wafer.

[0061] Referring to Figure 3, the surface of the wafer 101 of this embodiment is usually provided with a functional area 103 structure and an electrode 102. In this embodiment, a wafer bump 104 is firstly provided on the surface of the electrode 102. The wafer bump 104 can be formed on the surface of the electrode 102 by adopting a photolithography process, an electroplating process or a photolithography process, a chemical plating process and a ball implantation process.

[0062] S202: Setting a through groove in the cutting path of the wafer.

[0063] See also Figure 4 This step is basically the same as S101 in the above embodiment. For details, please refer to the above invention embodiment, which will not be described in detail here.

[0064] S203: etching the cover plate to form a bottom corresponding to the wafer working area and a support portion corresponding to the wafer cutting path.

[0065] See also Figure 5This step is basically the same as S102 in the above embodiment. For details, please refer to the above invention embodiment, which will not be described again here.

[0066] S204: Setting solder joints at positions of the cover plate corresponding to wafer bumps.

[0067] In the embodiment of the present invention, the solder joint 205 penetrates the bottom 202 along the thickness direction. In this embodiment, the electrode 102 of the wafer 101 can be led out to the surface of the cover plate 201 away from the wafer 101, so as to facilitate the use of the final device. Accordingly, in this step, the solder joint 205 is specifically set at the bottom 202 of the cover plate 201, corresponding to the position of the wafer bump 104, and finally ensures that the solder joint 205 is exposed on the surface of the cover plate 201 away from the wafer 101. Therefore, in this embodiment, the solder joint 205 needs to penetrate the bottom 202 along the thickness direction.

[0068] Specifically, this step may include: setting a blind hole 204 on the surface of the bottom 202 facing the side of the wafer 101 corresponding to the position of the wafer bump 104 ; and filling the blind hole 204 with a conductive material to form the solder joint 205 .

[0069] See also Figure 6 In this step, a laser etching process or other etching process can be used to etch a blind hole 204 of a preset depth at the bottom 202 facing the surface of the wafer 101, that is, at the position corresponding to the wafer bump 104 in the bottom surface of the groove etched on the cover plate 201 in S203, and the distance between the bottom surface of the blind hole 204 and the surface of the cover plate 201 away from the wafer 101 is equal to the thinning thickness of the cover plate 201 to be thinned subsequently.

[0070] See also Figure 7 After that, the blind hole 204 may be filled with a conductive material by an electroplating hole filling process or an electroplating plus chemical plating process to form a solder joint 205. Usually, in this step, the blind hole 204 needs to be filled with a conductive material first. Furthermore, in this step, the blind hole 204 may be filled with a conductive material until the conductive material protrudes from the bottom 202 away from the surface of one side of the wafer 101 to form the solder joint 205. That is, on the basis of filling the blind hole 204, a solder joint 205 whose top surface protrudes from the bottom 202 surface is further made, so as to facilitate the subsequent connection of the solder joint 205 with the wafer bump 104.

[0071] Specifically, in this embodiment, the sum of the height of the solder joint 205 protruding from the bottom 202 toward the surface of the side of the wafer 101 and the height of the wafer bump 104 is less than the height of the support portion 203. At this time, it can be ensured that when the cover plate 201 and the wafer 101 are bonded, the support portion 203 can be embedded in the through groove 105. It should also be emphasized that in this embodiment, bonding is performed by filling a glue layer between the support portion 203 and the through groove 105. In order to avoid overflow of the glue layer during bonding, it is necessary to control the distance between the cover plate 201 and the wafer 101 during bonding to prevent the support portion 203 from over-squeezing the glue layer and causing overflow of the glue layer. The distance between the cover plate 201 and the wafer 101 during bonding can be controlled by the sum of the height of the bottom 202 of the solder joint 205 protruding from the surface of the side of the wafer 101 and the height of the wafer bump 104. Therefore, controlling the sum of the heights of the above two prepared heights is equivalent to controlling the distance between the cover plate 201 and the wafer 101 during bonding, thereby avoiding the occurrence of glue overflow.

[0072] S205: Disposing printed bonding material at the end of the support portion and / or in the through groove.

[0073] In this step, a bonding material may be printed at the end of the support portion 203, i.e., the end of the support portion 203 away from the bottom 202 and / or in the through groove 105 by a glue-inducing process. The bonding material may be a bonding glue, the components of which are usually polymer materials.

[0074] S206: After printing the bonding material, inserting the support portion into the through groove, and forming a bonding layer between the support portion and the through groove through the bonding material.

[0075] See also Figure 8 In this step, a bonding process may be specifically used. First, the support portion 203 is aligned with the through slot 105, and then the support portion 203 is inserted into the through slot 105 for bonding. During bonding, the above bonding material is usually solidified to form a bonding layer 301 between the support portion 203 and the through slot 105, and the bonding layer 301 will fix the support portion 203 and the through slot 105.

[0076] Specifically, in this embodiment, the bonding layer 301 fills the gap between the end surface of the support portion 203 and the bottom surface of the through groove 105, and the gap between the side surface of the support portion 203 and the side wall of the through groove 105. At this time, the bonding layer 301 can fill the gap between the support portion 203 and the through groove 105, effectively increasing the contact area between the bonding layer 301 and the support portion 203 and the through groove 105, ensuring that the support portion 203 and the through groove 105 can be firmly bonded.

[0077] Furthermore, in the present embodiment, the bonding layer 301 is an elastically deformable bonding adhesive layer. That is, the bonding layer 301 formed after the above-mentioned bonding material is solidified allows a certain elastic deformation. The bonding layer 301 with a certain elastic deformation can play a certain buffering role, which can be used as a buffer between the cover plate 201 and the wafer 101, ensuring that the cover plate 201 can still be well bonded when the thermal expansion coefficient CTE is greatly different from the thermal expansion coefficient CTE of the wafer 101. When there is a difference between the thermal expansion coefficient of the cover plate 201 and the thermal expansion coefficient of the wafer 101, deformation will occur between the cover plate 201 and the wafer 101 during temperature changes such as bonding and working processes, and the above-mentioned elastically deformable bonding adhesive layer can accommodate the deformation and ensure the firmness of the bonding between the two. The bonding material used in the present embodiment can be epoxy resin glue, etc., which is not specifically limited here.

[0078] In this embodiment, the above S206 can be viewed from another perspective as follows: inserting the support portion 203 into the through groove 105 and bonding them, so that the cover plate 201 and the wafer 101 are embedded and bonded, and the wafer bumps 104 and the solder joints 205 are commensurately connected.

[0079] That is, when the support part 203 is inserted into the through groove 105, the wafer bump 104 and the solder joint 205 can be brought into contact with each other. When the bonding material is solidified to form the bonding layer 301, the wafer bump 104 and the solder joint 205 can be fused and connected to ensure electrical connection between the two. At this time, the electrode 102 is equivalent to being led out to the solder joint 205 of the cover plate 201. At this time, a sealed cavity is formed between the wafer 101 and the cover plate 201, so as to protect the above-mentioned working area.

[0080] S207: Thinning the surface of the cover plate away from the wafer until the solder joints are exposed.

[0081] See also Fig. 9 In this step, the back side of the cover plate 201, that is, the surface of the cover plate 201 away from the wafer 101, can be thinned by a thinning process to expose the solder joints 205 set in the above-mentioned blind holes 204, so that the solder joints 205 can be exposed to the surface of the cover plate 201 away from the wafer 101, which is equivalent to leading the electrodes 102 in the wafer 101 to the surface of the cover plate 201 away from the wafer 101.

[0082] S208: Arranging a cover plate bump connected to the solder joint at a position where the solder joint is exposed on the surface of the cover plate away from the wafer.

[0083] See also Fig.10 In this step, a cover bump 206 can be set at the position where the solder joint 205 is exposed on the back of the cover 201 through an electroplating process or a ball planting process, so as to facilitate electrical connection of external components with the above-mentioned functional area 103 based on the cover bump 206.

[0084] A wafer-level packaging method provided by an embodiment of the present invention has a cover plate 201 whose overall structure is integrally formed and has good sealing performance; the cover plate 201 and the wafer 101 are embedded bonding structures with high bonding strength; a bonding layer 301 buffer may exist between the wafer 101 and the cover plate 201, and the connection of the electrode 102 is achieved by means of bumps, which has high compatibility with the horizontal offset of the wafer 101; a bonding layer 301 buffer exists between the wafer 101 and the cover plate 201, which has good compatibility even when the thermal expansion coefficients of the two materials are greatly different.

[0085] Embodiment 3

[0086] A wafer-level packaging structure provided by an embodiment of the present invention is introduced below. The wafer-level packaging structure described below and the wafer-level packaging method described above can refer to each other.

[0087] In this embodiment, the wafer-level packaging structure is a wafer-level packaging structure prepared by a wafer-level packaging method provided by any of the above embodiments. The specific contents of the wafer-level packaging method have been described in detail in the above invention embodiments, and will not be repeated here.

[0088] Since the wafer-level packaging structure of this embodiment is a wafer-level packaging structure prepared by a wafer-level packaging method provided by any of the above embodiments, the wafer-level packaging structure has the characteristics of good sealing and high reliability.

[0089] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0090] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0091] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0092] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0093] The above is a detailed introduction to a wafer-level packaging method and a wafer-level packaging structure provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A wafer-level packaging method, characterized in that: include: A through groove is provided in a dicing path of the wafer; The cover plate is etched to form a bottom corresponding to the wafer working area and a support portion corresponding to the wafer cutting path; the support portion and the bottom are an integrated structure, the width of the support portion is not greater than the width of the through groove, and the height of the support portion is greater than the depth of the through groove; Inserting the support portion into the through groove and bonding them, so that the cover plate and the wafer are embedded and bonded to complete the packaging; Inserting the support portion into the through slot and bonding the support portion comprises: Disposing a printed bonding material at the end of the support portion and / or in the through groove; After printing the bonding material, inserting the support portion into the through groove, and forming a bonding layer between the support portion and the through groove by the bonding material; The bonding layer fills the gap between the end surface of the support part and the bottom surface of the through groove, and the gap between the side surface of the support part and the side wall of the through groove; the bonding layer is an elastically deformable bonding adhesive layer.

2. The method according to claim 1, characterized in that Before setting the through groove in the dicing road of the wafer, the method further includes: Arranging wafer bumps on the electrode surface of the wafer; Before inserting the support portion into the through groove and bonding, the method further comprises: A welding spot is arranged at a position of the cover plate corresponding to the wafer bump; the welding spot penetrates the bottom along the thickness direction; Inserting the support portion into the through groove and bonding the support portion to embed the cover plate and the wafer comprises: The support portion is inserted into the through groove and bonded, so that the cover plate and the wafer are embedded and bonded, and the wafer bumps and the solder joints are commutatively connected.

3. The method according to claim 2, characterized in that Arranging solder joints at positions of the cover plate corresponding to the wafer bumps includes: A blind hole is arranged on the surface of the bottom facing the side of the wafer, corresponding to the position of the wafer bump; Filling the blind hole with a conductive material to form the solder joint; After the support part is inserted into the through slot and bonded, the method further comprises: The surface of the cover plate away from the wafer is thinned until the solder joint is exposed.

4. The method according to claim 3, characterized in that After thinning the surface of the cover plate away from the wafer, the method further comprises: A cover plate bump connected to the soldering point is arranged at a position where the soldering point is exposed on a surface of the cover plate away from the wafer.

5. The method according to claim 3, characterized in that: Filling the blind hole with a conductive material to form the solder joint comprises: The blind hole is filled with conductive material until the conductive material protrudes out of the bottom and away from the surface of one side of the wafer, so as to form the solder joint.

6. The method according to claim 3, characterized in that The sum of the height of the solder joint protruding from the bottom toward the surface of one side of the wafer and the height of the wafer bump is less than the height of the support portion.

7. A wafer-level packaging structure, characterized in that: A wafer-level packaging structure prepared by a wafer-level packaging method as described in any one of claims 1 to 6.

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