Digital auxiliary simulation LDO (Low Dropout Regulator) circuit without off-chip capacitor

Abstract

The invention discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a digital-assisted analog LDO (Low Dropout Regulaor, low voltage difference linear regulator) circuit without external capacitors. Background Art

[0002] With the rapid development of microelectronics technology, the application scenarios of multiple voltage domains in large-scale integrated circuits have become more common, so the field of power management chips has become more important. LDO is widely used in power management chips due to its advantages of low cost, simple structure and easy integration. The area of ​​the power management chip is an important indicator. Usually, multiple LDOs are used to implement the multi-voltage threshold of the power management chip. Due to the need to reduce the area of ​​LDO as much as possible, the demand for analog LDO (capless-LDO) without external capacitor compensation is increasing.

[0003] Compared with traditional analog LDO, analog LDO without external capacitor does not need to add large on-chip capacitor for frequency compensation, thus saving a lot of area. However, the parasitic capacitance generated by its excessively large power adjustment tube will have a bad effect on the stability of the loop. Unlike analog LDO, digital LDO has the advantages of smaller power adjustment tube, easy stability, high integration and good process scalability. However, due to the existence of inherent quantization error of digital LDO, it has low accuracy, large output ripple, easy limit cycle oscillation, and relies on external circuit to provide clock.

[0004] In summary, how to reasonably combine the advantages of analog LDO and digital LDO to ensure output voltage accuracy, fast transient response and avoid dependence on external clock while ensuring good loop stability of the system is the key to hybrid LDO research. Summary of the invention

[0005] The present invention aims to solve the problems of poor stability of the existing analog LDO without external capacitors and low precision and dependence on external clocks of digital LDO, and proposes a digital-assisted analog LDO circuit without external capacitors.

[0006] To solve the above problems, the present invention is achieved through the following technical solutions:

[0007] A digital-assisted analog LDO circuit without external capacitors is composed of an analog main loop and a digital auxiliary loop; the analog main loop includes an error amplifier, a buffer stage circuit, an analog power stage circuit and a VG voltage detection circuit; the digital auxiliary loop includes a digital control logic circuit and a digital power stage circuit. The input of the error amplifier circuit is connected to a power supply terminal VDD, a ground terminal GND, bias voltages VB1-VB4, a reference voltage VBG and a feedback voltage VFB. The error amplifier circuit amplifies the difference between the reference voltage VBG and the feedback voltage VFB, outputs an error voltage VPG, and transmits it through a buffer stage circuit, thereby driving the analog power stage circuit and adjusting the output voltage VOUT. The input of the buffer stage circuit is connected to a power supply terminal VDD, a ground terminal GND, a bias voltage VB1, and an error amplifier outputs a voltage VPG. The buffer stage circuit pushes the low-frequency pole of the loop to a high frequency by reducing the output impedance, thereby improving the stability of the loop. The input of the analog power stage circuit is connected to the power supply terminal VDD, the ground terminal GND, and the output voltage VG of the buffer stage circuit. The analog power stage circuit linearly adjusts the output current through the input voltage VG to ensure the stability of the output voltage VOUT. At the same time, through the resistor voltage divider feedback network, it provides the sampling feedback voltage VFB of the error amplifier and the output monitoring voltages V_H and V_L. The input of the VG detection circuit is connected to the power supply terminal VDD, the ground terminal GND, and the output voltage VG of the buffer stage circuit. The VG detection circuit generates a monitoring voltage V1 by amplifying the voltage VG, which is used for the control of the digital auxiliary loop. The input of the digital control logic circuit is connected to the power supply terminal VDD, the ground terminal GND, the monitoring voltage V1, V_H, V_L and the reference voltage VBG. The digital control logic circuit generates logic control signals A and B by comparing V_H and V_L with VBG respectively. The signals A and B control the start of the ring oscillator through the XOR logic, and the 64-bit bidirectional shift register generates different code words through the SR latch logic; to control the number of digital power tubes turned on in the digital power stage circuit. The input of the digital power stage circuit is connected to the power supply terminal VDD, the ground terminal GND, and the control code word OUT<63:0> output by the digital control logic circuit. The digital power stage circuit provides different auxiliary currents to the output of the LDO by turning on different numbers of digital power tubes.

[0008] In the above scheme, the error amplifier is mainly composed of NMOS tubes MN1 to MN4 and PMOS tubes MP1 to MP7; the source of the PMOS tubes MP1, MP4 and MP6 is connected to the power supply VDD; the source of the NMOS tubes MN2 and MN4 is grounded GND; the gate of the PMOS tube MP1 is connected to the bias voltage VB1; the gate of the PMOS tube MP2 is connected to the feedback voltage VFB, forming the sampling input terminal of the error amplifier; the gate of the PMOS tube MP3 is connected to the reference voltage VBG, forming the reference voltage input terminal of the error amplifier; the gates of the PMOS tubes MP4 and MP6 are connected to the drains of the PMOS tubes MP5 and the NMOS tube MN1; the PMOS tubes MP5 and MP6 are connected to the drains of the PMOS tubes MP5 and MP6. The gate of the NMOS tube MN7 is connected to the bias voltage VB2; the gates of the NMOS tubes MN1 and MN3 are connected to the bias voltage VB3; the gates of the NMOS tubes MN2 and MN4 are connected to the bias voltage VB4; the drain of the PMOS tube MP1 is connected to the source of the PMOS tubes MP2 and MP3; the drains of the PMOS tubes MP2 and MP3 are connected to the drains of the NMOS tubes MN2 and MN4 and the sources of the NMOS tubes MN1 and MN3; the drains of the PMOS tubes MP4 and MP6 are connected to the sources of the PMOS tubes MP5 and MP7; the drain of the PMOS tube MP7 is connected to the drain of the NMOS tube MN3, forming an output terminal VPG of the error amplifier, and connected to the input terminal of the buffer stage circuit.

[0009] In the above scheme, the buffer stage circuit is mainly composed of NMOS tubes MN5, MN6, PMOS tubes MP8, MP9, capacitors C1, Cm and resistor R1. The source of PMOS tube MP8 is connected to the power supply VDD; the source of NMOS tube MN5 is grounded GND; the gate of PMOS tube MP8 is connected to one end of resistor R1 and the upper plate of capacitor C1, and the other end of resistor R1 is connected to bias voltage VB1; the gate of PMOS tube MP9 is connected to the lower plate of capacitor C1, forming the input end VPG of the buffer stage circuit, and connected to the output end of the error amplifier; the gate of NMOS tube MN5 is connected to bias voltage VB4; the gate of NMOS tube MN6 is connected to the drain of NMOS tube MN5 and the drain of PMOS tube MP9; the drain of PMOS tube MP8 is connected to the source of PMOS tube MP9 and the drain of NMOS tube MN6, forming the output end VG of the buffer stage circuit, and connected to the input end of the analog power stage circuit.

[0010] In the above scheme, the analog power stage circuit is mainly composed of a PMOS tube MP10 and resistors R2 to R5. The source of the PMOS tube MP10 is connected to the power supply VDD; one end of the resistor R5 is grounded GND; the gate of the PMOS tube MP10 is connected to the output end VG of the buffer stage circuit, forming the input end of the analog power stage circuit; the drain of the PMOS tube MP10 is connected to one end of the resistor R2, forming the first output end of the analog power stage, that is, the output end VOUT of the LDO; the other end of the resistor R2 is connected to one end of the resistor R3, forming the second output end V_L of the analog power stage circuit, and connected to the fourth input end of the digital control logic circuit; the other end of the resistor R3 is connected to one end of the resistor R4, forming the third output end VFB of the analog power stage circuit, and connected to the gate of the PMOS tube MP3 of the error amplifier; the other end of the resistor R4 is connected to the other end of the resistor R5, forming the fourth output end V_H of the analog power stage circuit, and connected to the second input end of the digital control logic circuit.

[0011] In the above scheme, the VG detection circuit is mainly composed of NMOS tubes MN7, MN8 and PMOS tube MP11. The source of the PMOS tube MP11 is connected to the power supply VDD; the source of the NMOS tube MN8 is grounded GND; the gate of the PMOS tube MP11 is connected to the output end VG of the buffer stage circuit, forming the input end of the VG detection circuit; the gate of the NMOS tube MN7 is connected to the gate of the NMOS tube MN8, the drain of the NMOS tube MN7 and the drain of the PMOS tube MP11, forming the output port V1 of the VG detection circuit, and connected to the first input end of the digital control logic circuit; the source of the NMOS tube MN7 is connected to the drain of the NMOS tube MN8.

[0012] In the above scheme, the digital control logic circuit is mainly composed of a Schmitt trigger SCHFF, comparators COMP1, COMP2, AND gates AND1, AND2, NOR gates NOR1, NOR2, an inverter INV, an XOR gate XOR, a ring oscillator and a 64-bit bidirectional shift register. The input end of the Schmitt trigger SCHFF constitutes the first input end of the digital control logic circuit, and is connected to the output port V1 of the VG detection circuit; the non-inverting input end of the comparator COMP1 constitutes the second input end of the digital control logic circuit, and is connected to the fourth output end V_H of the analog power stage circuit; the inverting input end of the comparator COMP1 is connected to the non-inverting input end of the comparator COMP2, constituting the third input end of the digital control logic circuit, and is connected to the reference voltage VBG; the inverting input end of the comparator COMP2 constitutes the fourth input end of the digital control logic circuit, and is connected to the second output end V_L of the analog power stage circuit; the input end of the inverter is connected to the output end VG_H of the Schmitt trigger SCHFF; the input end of the AND gate AND1 is respectively connected to the output end of COMP1 and the output end VG of the Schmitt trigger SCHFF _H; the input end of the AND gate AND2 is respectively connected to the output end of COMP2 and the output end VG_L of the inverter INV; the two input ends of the NOR gate NOR1 are respectively connected to the output end A of the AND gate AND1 and the output end of the NOR gate NOR2; the two input ends of the NOR gate NOR2 are respectively connected to the output end B of the AND gate AND2 and the output end of the NOR gate NOR1; the input end of the XOR gate XOR is connected to the output end A of the AND gate AND1 and the output end B of the AND gate AND2; the input end EN of the ring oscillator is connected to the output end of the XOR gate XOR; the two input ends of the 64-bit bidirectional shift register are respectively connected to the output end CLK of the ring oscillator and the output end of the NOR gate NOR1; the output end OUT<63:0> of the 64-bit bidirectional shift register constitutes 64 output ends of the digital control logic circuit, which are respectively connected to the 64 input ends of the digital power stage circuit.

[0013] In the above scheme, the digital power stage circuit is mainly composed of 64 PMOS tubes MP<63:0>; the source of the PMOS tube MP<63:0> is connected to the power supply VDD; the gate of the PMOS tube MP<63:0> constitutes 64 input terminals of the digital power stage circuit, which are respectively connected to the output terminal OUT<63:0> of the digital control logic circuit; the drains of the PMOS tube MP<63:0> are connected to each other to constitute the output terminal VOUT of the digital power stage circuit, and are connected to the output terminal VOUT of the analog power stage circuit to jointly constitute the output voltage port VOUT of the LDO.

[0014] Compared with the prior art, the present invention has the following characteristics:

[0015] 1. The power adjustment tube is divided into an analog power adjustment tube and 64 digital power adjustment tubes. Since the digital power tube only works in the cutoff region and the deep linear region, under the condition of equal load current, the total area of ​​the power adjustment tube is reduced; since the analog power adjustment tube is smaller than the size of the pure analog LDO power adjustment tube under the same load condition, not only the parasitic capacitance of the gate of the analog power adjustment tube is smaller, the charging and discharging speed is faster, and the transient response of the circuit is effectively improved; the pole at the gate is also located at a high frequency, and the loop is easy to compensate. On this basis, a super source follower structure is added to push this pole to a higher frequency, so that the present invention has better loop stability.

[0016] 2. In steady state, the digital auxiliary loop is disabled, and the analog main loop can ensure strict regulation, low quiescent current, and no switching noise or limit cycle oscillation at the output end; when the load current suddenly changes, the ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of digital power tubes turned on is changed, so that the response time is only the clock establishment time and is not limited by the clock cycle. Therefore, the present invention ensures both voltage accuracy in steady state and fast transient response.

[0017] 3. The clock generation circuit, i.e., the ring oscillator, is integrated into the digital auxiliary loop and works only when the digital auxiliary loop needs it, thereby reducing the static power consumption of the circuit and avoiding dependence on an external clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a digital-assisted analog LDO circuit structure without external capacitors;

[0019] Figure 2 A schematic diagram of the working principle of a digitally assisted analog LDO circuit without external capacitors;

[0020] Figure 3 It is a transient simulation diagram of a digitally assisted analog LDO circuit without external capacitors;

[0021] Figure 4 The figure shows the light-load and heavy-load loop Bode diagrams of a digitally assisted simulation of an LDO circuit without external capacitors. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific examples.

[0023] Figure 1The schematic diagram of the structure of a digital-assisted analog LDO circuit without external capacitors is shown in the figure. As can be seen from the figure, the example consists of an analog main loop and a digital auxiliary loop; the analog main loop includes an error amplifier, a buffer stage circuit, an analog power stage circuit and a VG voltage detection circuit; the digital auxiliary loop includes a digital control logic circuit and a digital power stage circuit. The input of the error amplifier circuit is connected to the power supply terminal VDD, the ground terminal GND, the bias voltage VB1~VB4, the reference voltage VBG and the feedback voltage VFB. The error amplifier circuit amplifies the difference between the reference voltage VBG and the feedback voltage VFB, outputs the error voltage VPG, and transmits it through the buffer stage circuit, thereby driving the analog power stage circuit and adjusting the output voltage VOUT. The input of the buffer stage circuit is connected to the power supply terminal VDD, the ground terminal GND, the bias voltage VB1, and the error amplifier outputs the voltage VPG. The buffer stage circuit pushes the low-frequency pole of the loop to the high frequency by reducing the output impedance, thereby improving the loop stability. The input of the analog power stage circuit is connected to the power supply terminal VDD, the ground terminal GND, and the output voltage VG of the buffer stage circuit. The analog power stage circuit linearly adjusts the output current through the input voltage VG to ensure the stability of the output voltage VOUT. At the same time, through the resistor voltage divider feedback network, it provides the sampling feedback voltage VFB of the error amplifier and the output monitoring voltages V_H and V_L. The input of the VG detection circuit is connected to the power supply terminal VDD, the ground terminal GND, and the output voltage VG of the buffer stage circuit. The VG detection circuit generates a monitoring voltage V1 by amplifying the voltage VG, which is used for the control of the digital auxiliary loop. The input of the digital control logic circuit is connected to the power supply terminal VDD, the ground terminal GND, the monitoring voltage V1, V_H, V_L and the reference voltage VBG. The digital control logic circuit generates logic control signals A and B by comparing V_H and V_L with VBG respectively. The signals A and B control the start of the ring oscillator through the XOR logic, and the 64-bit bidirectional shift register generates different code words through the SR latch logic; to control the number of digital power tubes turned on in the digital power stage circuit. The input of the digital power stage circuit is connected to the power supply terminal VDD, the ground terminal GND, and the control code word OUT<63:0> output by the digital control logic circuit. The digital power stage circuit provides different auxiliary currents to the output of the LDO by turning on different numbers of digital power tubes.

[0024] In this embodiment, the analog main loop acts as the main controller, and generates a continuous analog current Ia through the analog power adjustment PMOS tube MP10. Ia can be continuously adjusted from almost zero to a certain maximum value. The digital auxiliary loop is a slave controller that assists the analog main loop, and the current Id generated by it can be expressed as kI LSB , where k is the number of digital power regulators that are turned on, I LSBIt is the current provided by a single digital power regulator. Therefore, given any load current Iload, there is always a suitable k and Ia, so that Iload = kI LSB +Ia is established, assuming that the adjustable range of Ia is greater than I LSB , where k and Ia correspond to Iload and I LSB The quotient and remainder between .

[0025] In this embodiment, the error amplifier is mainly composed of NMOS tubes MN1 to MN4 and PMOS tubes MP1 to MP7; the source of the PMOS tubes MP1, MP4 and MP6 is connected to the power supply VDD; the source of the NMOS tubes MN2 and MN4 is grounded GND; the gate of the PMOS tube MP1 is connected to the bias voltage VB1; the gate of the PMOS tube MP2 is connected to the feedback voltage VFB, forming the sampling input terminal of the error amplifier; the gate of the PMOS tube MP3 is connected to the reference voltage VBG, forming the reference voltage input terminal of the error amplifier; the gates of the PMOS tubes MP4 and MP6 are connected to the drains of the PMOS tube MP5 and the NMOS tube MN1; the PMOS tubes MP5, MP6 are connected to the drains of the PMOS tubes MP5 and MP6. The gate of P7 is connected to the bias voltage VB2; the gates of the NMOS tubes MN1 and MN3 are connected to the bias voltage VB3; the gates of the NMOS tubes MN2 and MN4 are connected to the bias voltage VB4; the drain of the PMOS tube MP1 is connected to the source of the PMOS tubes MP2 and MP3; the drains of the PMOS tubes MP2 and MP3 are connected to the drains of the NMOS tubes MN2 and MN4 and the source of the NMOS tubes MN1 and MN3; the drains of the PMOS tubes MP4 and MP6 are connected to the source of the PMOS tubes MP5 and MP7; the drain of the PMOS tube MP7 is connected to the drain of the NMOS tube MN3, forming the output terminal VPG of the error amplifier, and connected to the input terminal of the buffer stage circuit.

[0026] In this embodiment, the analog power stage circuit is mainly composed of a PMOS tube MP10 and resistors R2 to R5. The source of the PMOS tube MP10 is connected to the power supply VDD; one end of the resistor R5 is grounded GND; the gate of the PMOS tube MP10 is connected to the output end VG of the buffer stage circuit, forming the input end of the analog power stage circuit; the drain of the PMOS tube MP10 is connected to one end of the resistor R2, forming the first output end of the analog power stage, that is, the output end VOUT of the LDO; the other end of the resistor R2 is connected to one end of the resistor R3, forming the second output end V_L of the analog power stage circuit, and connected to the fourth input end of the digital control logic circuit; the other end of the resistor R3 is connected to one end of the resistor R4, forming the third output end VFB of the analog power stage circuit, and connected to the gate of the PMOS tube MP3 of the error amplifier; the other end of the resistor R4 is connected to the other end of the resistor R5, forming the fourth output end V_H of the analog power stage circuit, and connected to the second input end of the digital control logic circuit.

[0027] In this embodiment, the buffer stage circuit is mainly composed of NMOS tubes MN5, MN6, PMOS tubes MP8, MP9, capacitors C1, Cm and resistor R1. The source of PMOS tube MP8 is connected to the power supply VDD; the source of NMOS tube MN5 is grounded GND; the gate of PMOS tube MP8 is connected to one end of resistor R1 and the upper plate of capacitor C1, and the other end of resistor R1 is connected to bias voltage VB1; the gate of PMOS tube MP9 is connected to the lower plate of capacitor C1, forming the input end VPG of the buffer stage circuit, and connected to the output end of the error amplifier; the gate of NMOS tube MN5 is connected to bias voltage VB4; the gate of NMOS tube MN6 is connected to the drain of NMOS tube MN5 and the drain of PMOS tube MP9; the drain of PMOS tube MP8 is connected to the source of PMOS tube MP9 and the drain of NMOS tube MN6, forming the output end VG of the buffer stage circuit, and connected to the input end of the analog power stage circuit.

[0028] In this embodiment, the VG detection circuit is mainly composed of NMOS tubes MN7, MN8 and PMOS tube MP11. The source of the PMOS tube MP11 is connected to the power supply VDD; the source of the NMOS tube MN8 is grounded GND; the gate of the PMOS tube MP11 is connected to the output end VG of the buffer stage circuit, forming the input end of the VG detection circuit; the gate of the NMOS tube MN7 is connected to the gate of the NMOS tube MN8, the drain of the NMOS tube MN7 and the drain of the PMOS tube MP11, forming the output port V1 of the VG detection circuit, and connected to the first input end of the digital control logic circuit; the source of the NMOS tube MN7 is connected to the drain of the NMOS tube MN8.

[0029] In this embodiment, the digital control logic circuit is mainly composed of a Schmitt trigger SCHFF, comparators COMP1, COMP2, AND gates AND1, AND2, NOR gates NOR1, NOR2, an inverter INV, an XOR gate XOR, a ring oscillator and a 64-bit bidirectional shift register. The input end of the Schmitt trigger SCHFF constitutes the first input end of the digital control logic circuit, and is connected to the output port V1 of the VG detection circuit; the non-inverting input end of the comparator COMP1 constitutes the second input end of the digital control logic circuit, and is connected to the fourth output end V_H of the analog power stage circuit; the inverting input end of the comparator COMP1 is connected to the non-inverting input end of the comparator COMP2, constituting the third input end of the digital control logic circuit, and is connected to the reference voltage VBG; the inverting input end of the comparator COMP2 constitutes the fourth input end of the digital control logic circuit, and is connected to the second output end V_L of the analog power stage circuit; the input end of the inverter is connected to the output end VG_H of the Schmitt trigger SCHFF; the input end of the AND gate AND1 is respectively connected to the output end of COMP1 and the output end VG of the Schmitt trigger SCHFF _H; the input end of the AND gate AND2 is respectively connected to the output end of COMP2 and the output end VG_L of the inverter INV; the two input ends of the NOR gate NOR1 are respectively connected to the output end A of the AND gate AND1 and the output end of the NOR gate NOR2; the two input ends of the NOR gate NOR2 are respectively connected to the output end B of the AND gate AND2 and the output end of the NOR gate NOR1; the input end of the XOR gate XOR is connected to the output end A of the AND gate AND1 and the output end B of the AND gate AND2; the input end EN of the ring oscillator is connected to the output end of the XOR gate XOR; the two input ends of the 64-bit bidirectional shift register are respectively connected to the output end CLK of the ring oscillator and the output end of the NOR gate NOR1; the output end OUT<63:0> of the 64-bit bidirectional shift register constitutes 64 output ends of the digital control logic circuit, which are respectively connected to the 64 input ends of the digital power stage circuit.

[0030] In this embodiment, the digital power stage circuit is mainly composed of 64 PMOS tubes MP<63:0>; the source of the PMOS tube MP<63:0> is connected to the power supply VDD; the gate of the PMOS tube MP<63:0> constitutes 64 input terminals of the digital power stage circuit, which are respectively connected to the output terminal OUT<63:0> of the digital control logic circuit; the drains of the PMOS tube MP<63:0> are connected to each other to constitute the output terminal VOUT of the digital power stage circuit, and are connected to the output terminal VOUT of the analog power stage circuit to jointly constitute the output voltage port VOUT of the LDO.

[0031] The working principle of the present invention is:

[0032] Figure 2It is a schematic diagram of the working principle of a digital-assisted analog LDO circuit without an external capacitor. As can be seen from the figure, the operation of the system is divided into four stages: the load current is stabilized at 1 mA, the load current is switched from 1 mA to 100 mA, the load current is stabilized at 100 mA, and the load current is switched from 100 mA to 1 mA.

[0033] As described above, in the digital-assisted loop, the digital logic control circuit controls the response of the digital power adjustment transistor by detecting the reference voltage VBG, the outputs V_L and V_H of the resistive voltage-dividing feedback network, and the output voltage V1 of the VG detection circuit.

[0034] The relationships between the output voltages V_L and V_H of the resistive voltage-dividing feedback network and the output voltage VOUT are as follows:

[0035]

[0036] Among them,

[0037]

[0038] Therefore, the basic conditions for the response of the digital power adjustment transistor are satisfied: VBG / H < VOUT and VG_H = 1, or VOUT < VBG / H and VG_L = 1.

[0039] When the load current is stabilized at 1 mA in the steady state, the error amplifier of the analog main loop samples the output voltage through the resistive voltage-dividing feedback network, and adjusts the analog power adjustment transistor PMOS transistor MP10 to make the output voltage smooth and stable.

[0040] During the process of the load current switching from 1 mA to 100 mA, the gate voltage VG of the analog power adjustment transistor PMOS transistor MP10 in the analog main loop decreases, and the current flowing through the PMOS transistor MP11 also gradually increases. When the generated V1 voltage increases to the upper threshold voltage of the Schmidt trigger SCHFF, the output voltage VG_H of the Schmidt trigger SCHFF changes from high to low, and the voltage VG_L after passing through the inverter becomes high level, enabling the AND gate AND2. When the output voltage VOUT drops to meet the condition that VOUT is less than VBG / L, the output of the comparator COMP2 changes from low to high, the output of the AND gate AND2 becomes high, and the output EN of the exclusive OR gate XOR becomes high, starting the ring oscillator. The output of the NOR gate NOR1 becomes low. Triggered by the rising edge of the clock, the 64-bit bidirectional shift register generates the corresponding codeword to control the increase in the number of on digital power adjustment transistors, thereby increasing the output voltage VOUT.

[0041] When the load current stabilizes to 100mA, and when the output voltage VOUT meets the condition that VOUT is greater than VBG / L, the output of comparator COMP2 changes from high to low, the output of AND gate AND2 becomes low, the output EN of XOR gate XOR becomes low, the ring oscillator stops working, and the 64-bit bidirectional shift register keeps the code word of the current state. The analog power adjustment tube PMOS tube MP10 of the analog main loop adjusts the output voltage VOUT to keep it smooth and stable.

[0042] In the process of load current switching from 100mA to 1mA, the gate voltage VG of the analog power adjustment tube PMOS tube MP10 of the analog main loop increases, and the current flowing through the PMOS tube MP11 gradually decreases. When the generated V1 voltage decreases to the lower threshold voltage of the Schmitt trigger SCHFF, the output VG_H of the Schmitt trigger SCHFF changes from low to high, enabling the AND gate AND1. When the output voltage VOUT rises to meet the condition that VOUT is greater than VREF / H, the output of the comparator COMP1 changes from low to high, the output of the AND gate AND1 becomes high, the output EN of the XOR gate XOR becomes high, the ring oscillator is started, and the output of the NOR gate becomes high. Under the triggering of the rising edge of the clock, the 64-bit bidirectional shift register generates a corresponding code word to control the reduction of the number of digital power adjustment tubes that are turned on, thereby reducing the output voltage VOUT.

[0043] When the load current stabilizes to 1mA again, and when the output voltage VOUT meets the condition that VOUT is less than VREF / H, the output of comparator COMP1 changes from high to low, the output of AND gate AND1 becomes low, the output EN of XOR gate XOR becomes low, the ring oscillator stops working, and the 64-bit bidirectional shift register keeps the code word of the current state. The analog power adjustment tube PMOS tube MP10 of the analog main loop adjusts the output voltage VOUT to keep it smooth and stable.

[0044] Figure 3 This is a transient simulation diagram of a digitally assisted simulation of an LDO circuit without external capacitors. The results include the power-on process and load current switching process of the digitally assisted simulation of the LDO circuit without external capacitors. The simulated power supply voltage VDD is set to 1.8V, the reference voltage VBG is set to 1.2V, and the output voltage VOUT is limited to 1.5V. The simulated waveforms of the power-on process of this example, the load current Iload, the output voltage VOUT, the gate voltage VG, the digital control logic circuit XOR gate output, the NOR gate NOR1 output, and the ring oscillator output CLK during the load current switching process are as follows Figure 3As shown in the figure, it can be seen that the digital-assisted analog LDO without external capacitors is powered on normally, and the output voltage remains stable when the load current is stable. During the load current switching process, the ring oscillator in the digital auxiliary loop is called to generate a clock signal, so that the response time is only the clock establishment time and is not limited by the clock cycle. This allows the present invention to reduce the static power consumption of the circuit while ensuring voltage accuracy and fast transient response and avoid dependence on an external clock.

[0045] When VGS is 1.1V, the analog power tube of the pure analog LDO circuit without external capacitors needs to have a size of 2500u / 0.2u when carrying a load current of 100mA. In this embodiment, when carrying a load current of 100mA, the size of the analog power adjustment PMOS tube MP10 only needs to be 1000u / 0.2u, the total size of the digital power adjustment PMOS tube MP<63:0> is 512u / 0.2u, and the total size of the power adjustment tube is only 1512u / 0.2u, which is reduced by 40%.

[0046] Figure 4 The Bode diagram of the light-load and heavy-load loops of a digitally assisted simulation LDO circuit without external capacitors is shown in Figure 2. It can be seen that the loop has good stability under both light and heavy loads, and the phase margin is around 80°, which changes little with the load current.

[0047] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A digitally assisted analog LDO circuit without external capacitors. Its characteristics are: It consists of an analog main loop and a digital auxiliary loop; the analog main loop includes an error amplifier, a buffer stage circuit, an analog power stage circuit and a VG voltage detection circuit; the digital auxiliary loop includes a digital control logic circuit and a digital power stage circuit; The input of the error amplifier circuit is connected to the power supply terminal VDD, the ground terminal GND, the bias voltages VB1 to VB4, the reference voltage VBG and the feedback voltage VFB. The error amplifier circuit amplifies the difference between the reference voltage VBG and the feedback voltage VFB, and outputs the error voltage VPG, which is transmitted through the buffer stage circuit to drive the analog power stage circuit and adjust the output voltage VOUT. The input of the buffer stage circuit is connected to the power supply terminal VDD, the ground terminal GND, the bias voltage VB1, and the error amplifier output voltage VPG. The buffer stage circuit pushes the low-frequency pole of the loop to the high frequency by reducing the output impedance, thereby improving the loop stability. The input of the analog power stage circuit is connected to the power supply terminal VDD, the ground terminal GND, and the output voltage VG of the buffer stage circuit. The analog power stage circuit linearly adjusts the output current through the input voltage VG to ensure the stability of the output voltage VOUT. At the same time, through the resistor voltage divider feedback network, it provides the sampling feedback voltage VFB of the error amplifier and the output monitoring voltages V_H and V_L; The input of the VG detection circuit is connected to the power supply terminal VDD, the ground terminal GND, and the output voltage VG of the buffer stage circuit. The VG detection circuit generates a monitoring voltage V1 by amplifying the voltage VG, which is used for controlling the digital auxiliary loop; The input of the digital control logic circuit is connected to the power supply terminal VDD, the ground terminal GND, the monitoring voltage V1, V_H, V_L and the reference voltage VBG. The digital control logic circuit generates logic control signals A and B by comparing V_H, V_L with VBG respectively. The signals A and B control the start of the ring oscillator through the XOR logic, and make the 64-bit bidirectional shift register generate different code words through the SR latch logic; so as to control the number of digital power tubes turned on in the digital power stage circuit; The input of the digital power stage circuit is connected to the power supply terminal VDD, the ground terminal GND, and the control code word OUT<63:0> output by the digital control logic circuit. The digital power stage circuit provides different auxiliary currents to the output of the LDO by turning on different numbers of digital power tubes.

2. The digital-assisted analog LDO circuit without external capacitor according to claim 1, Its characteristics are The error amplifier is mainly composed of NMOS tubes MN1~MN4 and PMOS tubes MP1~MP7; The source of PMOS tubes MP1, MP4 and MP6 is connected to the power supply VDD; the source of NMOS tubes MN2 and MN4 is grounded GND; the gate of PMOS tube MP1 is connected to the bias voltage VB1; the gate of PMOS tube MP2 is connected to the feedback voltage VFB, forming the sampling input terminal of the error amplifier; the gate of PMOS tube MP3 is connected to the reference voltage VBG, forming the reference voltage input terminal of the error amplifier; the gates of PMOS tubes MP4 and MP6 are connected to the drains of PMOS tubes MP5 and NMOS tube MN1; the gates of PMOS tubes MP5 and MP7 are connected to the bias voltage VB2; NMOS tube MN1 The gates of the NMOS tubes MN2 and MN4 are connected to the bias voltage VB3; the gates of the NMOS tubes MN2 and MN4 are connected to the bias voltage VB4; the drain of the PMOS tube MP1 is connected to the source of the PMOS tubes MP2 and MP3; the drains of the PMOS tubes MP2 and MP3 are connected to the drains of the NMOS tubes MN2 and MN4 and the sources of the NMOS tubes MN1 and MN3; the drains of the PMOS tubes MP4 and MP6 are connected to the sources of the PMOS tubes MP5 and MP7; the drain of the PMOS tube MP7 is connected to the drain of the NMOS tube MN3, forming an output terminal VPG of the error amplifier, and connected to the input terminal of the buffer stage circuit.

3. The digital-assisted analog LDO circuit without external capacitor according to claim 1, Its characteristics are: The buffer stage circuit is mainly composed of NMOS tubes MN5, MN6, PMOS tubes MP8, MP9, capacitors C1, Cm and resistor R1; The source of the PMOS tube MP8 is connected to the power supply VDD; the source of the NMOS tube MN5 is grounded GND; the gate of the PMOS tube MP8 is connected to one end of the resistor R1 and the upper plate of the capacitor C1, and the other end of the resistor R1 is connected to the bias voltage VB1; the gate of the PMOS tube MP9 is connected to the lower plate of the capacitor C1, forming the input end VPG of the buffer stage circuit, and connected to the output end of the error amplifier; the gate of the NMOS tube MN5 is connected to the bias voltage VB4; the gate of the NMOS tube MN6 is connected to the drain of the NMOS tube MN5 and the drain of the PMOS tube MP9; the drain of the PMOS tube MP8 is connected to the source of the PMOS tube MP9 and the drain of the NMOS tube MN6, forming the output end VG of the buffer stage circuit, and connected to the input end of the analog power stage circuit.

4. The digital-assisted analog LDO circuit without external capacitor according to claim 1, Its characteristics are: The analog power stage circuit is mainly composed of PMOS tube MP10 and resistors R2~R5; The source of the PMOS tube MP10 is connected to the power supply VDD; one end of the resistor R5 is grounded GND; the gate of the PMOS tube MP10 is connected to the output end VG of the buffer stage circuit to form the input end of the analog power stage circuit; the drain of the PMOS tube MP10 is connected to one end of the resistor R2 to form the first output end of the analog power stage, that is, the output end VOUT of the LDO; the other end of the resistor R2 is connected to one end of the resistor R3 to form the second output end V_L of the analog power stage circuit, and is connected to the fourth input end of the digital control logic circuit; the other end of the resistor R3 is connected to one end of the resistor R4 to form the third output end VFB of the analog power stage circuit, and is connected to the gate of the PMOS tube MP3 of the error amplifier; the other end of the resistor R4 is connected to the other end of the resistor R5 to form the fourth output end V_H of the analog power stage circuit, and is connected to the second input end of the digital control logic circuit.

5. The digital-assisted analog LDO circuit without external capacitor according to claim 1, Its characteristics are: The VG detection circuit is mainly composed of NMOS tubes MN7, MN8 and PMOS tube MP11; The source of the PMOS tube MP11 is connected to the power supply VDD; the source of the NMOS tube MN8 is grounded GND; the gate of the PMOS tube MP11 is connected to the output end VG of the buffer stage circuit, forming the input end of the VG detection circuit; the gate of the NMOS tube MN7 is connected to the gate of the NMOS tube MN8, the drain of the NMOS tube MN7 and the drain of the PMOS tube MP11, forming the output port V1 of the VG detection circuit, and connected to the first input end of the digital control logic circuit; the source of the NMOS tube MN7 is connected to the drain of the NMOS tube MN8.

6. The digital-assisted analog LDO circuit without external capacitor according to claim 1, Its characteristics are: The digital control logic circuit is mainly composed of Schmitt trigger SCHFF, comparators COMP1, COMP2, AND gates AND1, AND2, NOR gates NOR1, NOR2, inverter INV, XOR gate XOR, ring oscillator and 64-bit bidirectional shift register; The input end of the Schmitt trigger SCHFF constitutes the first input end of the digital control logic circuit, and is connected to the output port V1 of the VG detection circuit; the non-inverting input end of the comparator COMP1 constitutes the second input end of the digital control logic circuit, and is connected to the fourth output end V_H of the analog power stage circuit; the inverting input end of the comparator COMP1 is connected to the non-inverting input end of the comparator COMP2, constituting the third input end of the digital control logic circuit, and is connected to the reference voltage VBG; the inverting input end of the comparator COMP2 constitutes the fourth input end of the digital control logic circuit, and is connected to the second output end V_L of the analog power stage circuit; the input end of the inverter is connected to the output end VG_H of the Schmitt trigger SCHFF; the input end of the AND gate AND1 is respectively connected to the output end of COMP1 and the output end VG of the Schmitt trigger SCHFF _H; the input end of the AND gate AND2 is respectively connected to the output end of COMP2 and the output end VG_L of the inverter INV; the two input ends of the NOR gate NOR1 are respectively connected to the output end A of the AND gate AND1 and the output end of the NOR gate NOR2; the two input ends of the NOR gate NOR2 are respectively connected to the output end B of the AND gate AND2 and the output end of the NOR gate NOR1; the input end of the XOR gate XOR is connected to the output end A of the AND gate AND1 and the output end B of the AND gate AND2; the input end EN of the ring oscillator is connected to the output end of the XOR gate XOR; the two input ends of the 64-bit bidirectional shift register are respectively connected to the output end CLK of the ring oscillator and the output end of the NOR gate NOR1; the output end OUT<63:0> of the 64-bit bidirectional shift register constitutes 64 output ends of the digital control logic circuit, which are respectively connected to the 64 input ends of the digital power stage circuit.

7. The digital-assisted analog LDO circuit without external capacitor according to claim 1, Its characteristics are: The digital power stage circuit is mainly composed of 64 PMOS tubes MP<63:0>; The sources of the PMOS tubes MP<63:0> are all connected to the power supply VDD; the gates of the PMOS tubes MP<63:0> constitute 64 input terminals of the digital power stage circuit, which are respectively connected to the output terminals OUT<63:0> of the digital control logic circuit; the drains of the PMOS tubes MP<63:0> are connected to each other to constitute the output terminal VOUT of the digital power stage circuit, and are connected to the output terminal VOUT of the analog power stage circuit to jointly constitute the output voltage port VOUT of the LDO.

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