Built-in self-test repairing method for PE matrix of AI accelerator chip

By introducing built-in self-testing and self-repair circuits into the AI ​​accelerator chip, using scan test generators and redundant computing units, the problem of large area of ​​test circuit modules and external diagnostic dependence is solved, improving chip yield and reducing manufacturing costs .

CN119248544AActive Publication Date: 2025-01-03GUANGDONG UNIV OF TECH
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Patent Information

Application Number
CN202411036803.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-07-31
Publication Date
2025-01-03
Estimated Expiration
2044-07-31

AI Technical Summary

Technical Problem

The test circuit module area of ​​existing AI accelerator chips accounts for a large proportion, resulting in a significant increase in the chip area. It is necessary to diagnose the faulty PE computing unit through external software, resulting in a decrease in yield rate and an increase in manufacturing costs.

Method used

Using built-in self-testing and self-repair methods of AI accelerator chip PE matrix, built-in self-testing and self-repair through scanning test generators, configurable PE computing unit, output response comparator, fault PE diagnostics and redundant computing unit, the built-in self-testing and self-repairing unit is realized through scanning test generators, configurable PE computing unit, output response comparator, fault PE diagnostics and redundant computing units. Fixed to reduce external software dependencies and circuit area.

Benefits of technology

It effectively reduces the proportion of circuit module area, improves the chip yield, reduces the manufacturing cost, and reduces the number of failed PE computing units, and improves the calculation accuracy.

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Abstract

The invention discloses a built-in self-test repairing method for a PE matrix of an AI accelerator chip, and relates to the technical field of circuit structure design of the AI accelerator chip. According to the built-in self-test method, a scan test generator is adopted to generate scan test excitation, an output response is transmitted through a configurable PE operation unit, an output response comparator is adopted to judge whether the output response is correct or not, and a fault PE diagnostor is adopted to judge a row and column address where a fault PE unit is located; according to the built-in self-repairing method, an RPE redundant operation unit is used for replacing and repairing a fault PE unit, and a corresponding data bus is distributed to the RPE redundant operation unit through an activation data bus and a weight data bus distributor according to row and column addresses. According to the invention, the self-test of the PE arithmetic unit and the self-repair of the failed PE arithmetic unit are realized with a relatively small extra circuit area proportion, so that the yield of the AI accelerator chip is improved, and the manufacturing cost of the chip is reduced.
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Citation Information

Patent Citations

  • Convolutional neural network optimization method and device based on pulse array

    CN110852422A

  • Method and apparatus for diagnostic coverage for ai hardware accelerators

    EP4134875A1

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