Layered design rule inspection system and method in EDA

Abstract

The invention discloses a hierarchical design rule checking system and method in EDA (Electronic Design Automation), which are used for efficiently and accurately checking design rules in integrated circuit design. According to the system, primary violation detection, CNN (convolutional neural network) violation classification and precise analysis of an advanced GPU (graphics processing unit) parallel algorithm are combined to form a multi-level inspection process. According to the method, firstly, a primary violation detection model based on a decision-making tree is used for rapidly screening potential design rule violations, then violation types are classified in detail through a CNN violation classifier, a back-end designer checks whether the violation types are clear or not, if the violation types are not clear enough, finally, the high-level GPU parallel algorithm is used for finely analyzing the violation, and the design rule violation is determined. And the accuracy of inspection results is ensured. According to the system and the method, the efficiency and the accuracy of design rule checking are remarkably improved, the design period is shortened through hierarchical checking, and the system and the method have important industrial application value and market potential.

Description

Technical Field

[0001] The present invention belongs to the field of electronic design automation (EDA), and in particular, relates to a hierarchical design rule checking system and method in EDA. Background Art

[0002] like Figure 1 In the evolution of integrated circuit design, design rule checking (DRC) has become increasingly important as a key step to ensure that the design meets the requirements of the manufacturing process. With the continuous miniaturization of technology nodes, design rules have become more and more complex, placing higher demands on the efficiency and accuracy of DRC tools. Traditional DRC methods, based on fixed rule sets and Boolean logic operations, have been unable to adapt to the rapidly evolving process requirements and the expansion of design scale. These methods are not only time-consuming but also difficult to expand when dealing with an increasing number of complex rules, limiting the speed of design innovation and iteration.

[0003] The reduction in technology nodes has brought multiple challenges: first, the number and complexity of design rules have increased significantly, and traditional DRC checking methods are unable to cope with thousands of rules; second, the shortening of design cycles requires that DRC checking must be faster to meet the market demand for rapid product iteration; finally, as the design scale increases, the demand for computing resources is also increasing, and traditional DRC methods are not economical in terms of resource consumption.

[0004] Under such background, the field of electronic design automation (EDA) is in urgent need of a new DRC solution that can not only meet the requirements of high precision, but also improve the inspection speed, shorten the design cycle, and reduce the consumption of computing resources. This is exactly the problem to be solved by the present invention. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a hierarchical design rule checking system and method in EDA for efficient and accurate design rule checking of integrated circuit design. By introducing multi-level deep learning technology, the system and method of the present invention can significantly improve the efficiency of DRC checking while maintaining high accuracy, bringing innovative automated design rule checking solutions to the field of integrated circuit design.

[0006] In the present invention, a multi-level inspection process is formed by combining primary violation detection, convolutional neural network (CNN) violation classification and precise analysis of advanced GPU parallel algorithms. The technical solution of the present invention is specifically described as follows.

[0007] The present invention provides a hierarchical design rule checking system in EDA, including a primary violation detection model, a violation type Classifiers and advanced violation analysis models; among them: A primary violation detection model that uses a decision tree-based deep learning algorithm to perform preliminary screening for potential design rule check (DRC) violations in IC designs; The violation type classifier uses a convolutional neural network (CNN) to classify the types of violations detected by the primary violation detection model; The advanced violation analysis model uses advanced graphics processor GPU parallel algorithm to perform accurate design rule check DRC violation analysis and judgment.

[0008] In the present invention, the primary violation detection model is obtained by learning the existing legal layout pattern and constructing a decision tree capable of identifying violation features; the construction method is as follows: 1) Data preparation Collect layout data from historical compliant designs and use perturbation techniques to obtain compliant and noncompliant design layouts as training and test data sets; 2) Feature Selection Extracting fixed-size window features from the design layout for training the decision tree model; the features are closely related to the process node, including line width, spacing, and shape of different materials; 3) Model training and construction The extracted features are used to train the decision tree model, and the model parameters are optimized to improve the classification accuracy, thus constructing a primary violation detection model.

[0009] In the present invention, the primary violation detection model is constructed by the CART algorithm.

[0010] In the present invention, the violation type classifier is constructed by learning the image features of different violation types; the construction method is as follows: Collect layout data from historical compliant designs, use perturbation technology to obtain compliant and noncompliant design layouts, visualize the noncompliant design layouts, and normalize them as training data sets and validation sets; train a CNN model based on the training data set, evaluate its performance through the validation set, and build a violation type classifier.

[0011] In the present invention, the CNN model includes an input layer, a convolutional layer, a batch normalization layer, an activation layer and an output layer.

[0012] In the present invention, the workflow of the advanced violation analysis model is as follows: 1) System construction Build a system including a data transmission module, a GPU acceleration processing unit, and a conflict identification and processing unit; 2) Data transmission and preprocessing Transfer the geometric information of the design layout from the CPU to the GPU and convert and store the edge sets; 3) GPU accelerated scan line algorithm Initialize and execute the scanline algorithm on the GPU, using parallel processing capabilities to improve algorithm efficiency; 4) Internal polygon check and inter-polygon check Execute in parallel on GPU to quickly locate design rule violations; 5) Conflict identification and resolution Utilize the high parallelism of GPU to analyze and process candidate conflicting edge pairs; 6) Result output and performance optimization The inspection results are transmitted back to the CPU for visual display.

[0013] The present invention also provides a hierarchical design rule checking method in EDA, comprising the following steps: Step 1: Perform a preliminary screening of the IC design using a primary violation detection model to determine if there are any DRC violations. Step 2: For the violations detected by the primary model, use the violation type classifier to classify the violation type; Step 3: For designs that require high-precision judgment, or when chip back-end designers are dissatisfied with the primary detection results, use the advanced violation analysis model to conduct in-depth analysis and obtain a violation analysis report.

[0014] Compared with the prior art, the present invention has the following advantages: High efficiency: The primary violation detection model can quickly complete the DRC violation screening in the design, significantly reducing the inspection time;

[0015] High precision: CNN classifiers and advanced violation analysis models ensure accurate identification and judgment of violation types, improving the accuracy of DRC inspection;

[0016] Flexibility: Designers can choose different levels of DRC checking based on design requirements and personal preferences, balancing checking speed and accuracy;

[0017] User-friendly: The system provides intuitive feedback and violation correction suggestions to help designers quickly respond to and correct design issues. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of layout design rule violations.

[0019] Figure 2 Plot of training data where we obtain incorrect examples for perturbations. Figure 2The process of generating training data by introducing perturbations in a compliant layout is shown. The figure shows that a cut metal is randomly generated after the perturbation and a cut metal spacing violation is generated, and how to extract data for training the primary violation detection model and the CNN model by setting the window size and scanning the entire layout with a step of 0.75 times the edge length.

[0020] Figure 3 An example diagram of a decision tree for a primary breach detection model. Figure 3 The specific steps in primary violation detection are demonstrated.

[0021] Figure 4 The network structure diagram of the CNN violation type classifier. Figure 4 The network architecture of the CNN violation type classifier is shown, including the input layer, convolution layer, batch normalization layer, activation layer, and output layer. The function, parameters, and role of each layer are marked in detail in the figure, showing how to accurately classify violation types through deep learning technology.

[0022] Figure 5 Execution flow chart of advanced GPU parallel algorithm. Figure 5 The detailed process of advanced GPU parallel algorithm in performing DRC checking is shown. The figure includes key steps such as data transmission, preprocessing, parallel scan line algorithm execution, internal polygon checking, inter-polygon checking, conflict identification and processing, and result output. This figure aims to clearly show how parallel algorithms can efficiently complete complex DRC checking tasks. DETAILED DESCRIPTION

[0023] The technical solution of the present invention is described below in conjunction with the accompanying drawings and embodiments.

[0024] Figure 1 Schematic diagram of layout design rule violations. Figure 1 Shows examples of design rule violations in integrated circuit layout. Different metal layers are clearly identified with different color markers in the figure, including but not limited to violations such as via spacing is too close, CutMetal spacing is too close, etc. This figure is intended to intuitively show the types of problems that may be encountered in design rule checking.

[0025] The present invention provides a hierarchical design rule checking system in EDA, including a primary violation detection model, a violation type classifier and an advanced violation analysis model; Primary Violation Detection Model: A decision tree-based deep learning model for automatically identifying and detecting DRC violations from designs. The model builds a decision tree that can identify violation features by learning patterns from existing legal layouts.

[0026] CNN Violation Type Classifier: A deep learning technique used to classify the types of violations identified by the primary violation detection model. The classifier learns the image features of different violation types to accurately identify the violation type.

[0027] Advanced Violation Analysis Model: An advanced GPU parallel algorithm to provide high-precision DRC violation analysis and judgment.

[0028] The model is able to handle complex design rules and provide detailed violation analysis reports.

[0029] Training and testing data set preparation: like Figure 2 , generating training and test datasets through perturbation techniques is a key step to improve the accuracy of design rule checking (DRC) systems. First, we collect layout data from existing compliant designs, and then perform small, random perturbations on this data to generate compliant and violating design variants. The compliant and violating variants will be used to train and test the decision tree model, while only the violating variants are used to train the CNN model. During the perturbation process, we ensure that the compliant variants remain within the range allowed by the process rules, while the violating variants intentionally violate these rules. Next, we extract key features such as line width, spacing, and shape from the perturbed layout data and annotate them for the compliant and violating data respectively. The decision tree model is trained using the features of the compliant and violating datasets, and the model parameters are optimized by learning the features that distinguish the two designs. The CNN model focuses on the violating dataset, treats the violating dataset as an image, and learns the complex patterns of the violating design through its deep learning architecture.

[0030] like Figure 3 , the decision tree model includes: 1. Data preparation: Collect historical design data, such as Figure 2 ,The ,perturbation technique is used to obtain the compliant and violating design layouts ,as training and testing datasets.

[0031] 2. Feature selection: Extract fixed-size window features from the design layout for training the decision tree model. Features include line width, spacing, and shape of different materials.

[0032] 3. Model training: Use the extracted features to train the decision tree model and optimize the model parameters to improve classification accuracy.

[0033] 4. Model deployment: Integrate the trained decision tree model into the system for preliminary screening of design rule violations.

[0034] Convolutional Neural Network (CNN) examples include: 1. Data preprocessing: visualize the design layout and normalize it to meet the input requirements of the CNN model.

[0035] 2. If Figure 4 ,The network structure design includes: designing the CNN model architecture, including a convolutional layer, a normalization layer, an activation layer, and a connection layer. The connection layer is a residual connection to extract image features and classify them.

[0036] 3. Training and validation: Use a large number of illegal design layout images to train the CNN model and evaluate its performance through the validation set.

[0037] 4. Integration and application: Integrate the trained CNN model into the system to classify the potential violations screened by the decision tree in detail.

[0038] like Figure 5 , GPU parallel algorithm embodiments include: 1. System construction: Build a system including data transmission module, GPU acceleration processing unit and conflict identification and processing unit.

[0039] 2. Data transfer and preprocessing: The geometric information of the design layout is transferred from the CPU to the GPU, and the edge set is converted and stored.

[0040] 3. GPU accelerated scanline algorithm: Initialize and execute the scanline algorithm on the GPU, using parallel processing capabilities to improve algorithm efficiency.

[0041] 4. Intra-polygon checking and inter-polygon checking: Executed in parallel on the GPU to quickly locate design rule violations.

[0042] 5. Conflict identification and processing: Utilize the high parallelism of GPU to analyze and process candidate conflicting edge pairs.

[0043] 6. Result output and performance optimization: The inspection results are transmitted back to the CPU for visual display. Example 1

[0044] In this example, we will use the characteristics of the FreePDK 45nm process node to achieve efficient and accurate integrated circuit design rule checking (DRC) by combining decision trees, CNNs, and GPU-based parallel algorithms. First, we collect and perturb compliant and non-compliant 45nm design data to build training and test data sets. Then, we select features closely related to the process node, such as minimum line width, line spacing, etc., use the CART algorithm to build a decision tree model, set the maximum depth to 10, and use Gini impurity as the splitting criterion. The model accuracy is close to 100%.

[0045] Furthermore, we visualized and normalized the design layout to meet the input requirements of the CNN model. We designed a CNN architecture with 5 convolutional layers and corresponding normalization and activation layers. Through training and cross-validation with a large number of 45nm design layout images, the accuracy of the CNN model can reach 90%. In the GPU parallel algorithm implementation phase, we will build a system including a data transmission module, an accelerated processing unit based on the A100 GPU, and a conflict identification and processing unit. Taking advantage of the high parallelism of the A100 GPU, the scan line algorithm and polygon checking are executed, and the overall high-level violation analysis time is less than 10 minutes.

[0046] Taking all factors into consideration, the time for preliminary screening using decision trees is less than 1 minute, and the time for CNN violation classification is less than 5 minutes. At the same time, only a small part of the design needs to be checked by advanced GPU parallel rules after verification by the back-end designer. The total time of the entire DRC check process will be significantly lower than the traditional method while maintaining high accuracy. Such an embodiment not only improves the efficiency of design rule checking, but also ensures the accuracy of the inspection results through a multi-level inspection process, bringing an innovative automated DRC inspection solution to the field of integrated circuit design.

Claims

1. A hierarchical design rule checking system in EDA, characterized in that: It includes a primary violation detection model, a violation type classifier, and an advanced violation analysis model; among which: A primary violation detection model that uses a decision tree-based deep learning algorithm to perform preliminary screening for potential design rule check (DRC) violations in IC designs; The violation type classifier uses a convolutional neural network (CNN) to classify the types of violations detected by the primary violation detection model; The advanced violation analysis model uses advanced graphics processor GPU parallel algorithm to perform accurate design rule check DRC violation analysis and judgment.

2. The system according to claim 1, characterized in that The primary violation detection model is obtained by learning the patterns of existing legal layouts and building a decision tree that can identify violation features; The construction method is as follows: 1) Data preparation Collect layout data from historical compliant designs and use perturbation techniques to obtain compliant and noncompliant design layouts as training and test data sets; 2) Feature Selection Extracting fixed-size window features from the design layout for training the decision tree model; the features are closely related to the process node, including line width, spacing, and shape of different materials; 3) Model training and construction The extracted features are used to train the decision tree model, and the model parameters are optimized to improve the classification accuracy, thus constructing a primary violation detection model.

3. The system according to claim 1, characterized in that The violation type classifier is constructed by learning the image features of different violation types; its construction method is as follows: Collect layout data from historical compliant designs, use perturbation technology to obtain compliant and noncompliant design layouts, visualize the noncompliant design layouts, and normalize them as training data sets and validation sets; The CNN model is trained based on the training dataset, and the performance is evaluated through the validation set to build a violation type classifier.

4. The system according to claim 3, characterized in that The CNN model consists of an input layer, a convolutional layer, a batch normalization layer, an activation layer, and an output layer.

5. The system according to claim 1, characterized in that The workflow of the advanced violation analysis model is as follows: 1) System construction Build a system including a data transmission module, a GPU acceleration processing unit, and a conflict identification and processing unit; 2) Data transmission and preprocessing Transfer the geometric information of the design layout from the CPU to the GPU and convert and store the edge sets; 3) GPU accelerated scan line algorithm Initialize and execute the scanline algorithm on the GPU, using parallel processing capabilities to improve algorithm efficiency; 4) Internal polygon check and inter-polygon check Execute in parallel on GPU to quickly locate design rule violations; 5) Conflict identification and resolution Utilize the high parallelism of GPU to analyze and process candidate conflicting edge pairs; 6) Result output and performance optimization The inspection results are transmitted back to the CPU for visual display.

6. A checking method based on the multi-level deep learning design rule checking system according to claim 1, characterized in that: The following steps are involved: Step 1: Perform a preliminary screening of the IC design using a primary violation detection model to determine if there are any DRC violations. Step 2: For the violations detected by the primary model, use the violation type classifier to classify the violation type; Step 3: For designs that require high-precision judgment, or when chip back-end designers are dissatisfied with the primary detection results, use the advanced violation analysis model to conduct in-depth analysis and obtain a violation analysis report.

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