Area array VCSEL with high heat dissipation efficiency

Abstract

The invention relates to the technical field of semiconductor lasers, in particular to an area array VCSEL (Vertical Cavity Surface Emitting Laser) with high heat dissipation efficiency, which comprises a periodically arranged light-emitting unit array, and deep etching grooves exist between adjacent light-emitting units. Each light-emitting unit is provided with a substrate, a DBR (Distributed Bragg Reflector) structure, an active layer, a current limiting layer, an electrode and an insulating layer arranged on the side surface and a communication region of each light-emitting unit, graphene is plated on all regions of the insulating layer, or graphene is only plated on a heat distribution region according to a thermal simulation result to form a patterned graphene heat dissipation layer. The local heat dissipation problem of the area array VCSEL can be effectively optimized, the temperature difference between different light-emitting units is balanced, and the situation that the performance of a device is reduced due to the fact that local heating of a chip is serious is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor lasers, and in particular provides a planar array VCSEL with high heat dissipation efficiency. Background Art

[0002] Vertical cavity surface emitting semiconductor laser, referred to as (VCSEL), was first proposed by Professor Iga of Tokyo Institute of Technology in Japan in 1977. Different from traditional edge-emitting semiconductor lasers, the epitaxial structure of VCSEL mainly includes multilayer Bragg reflectors (DBR) at the top and bottom, conductive confinement areas, active areas and semiconductor substrates. The upper and lower DBR feedback makes the laser beam in the cavity emit in a direction perpendicular to the substrate. VCSEL has many advantages such as low threshold current, circular spot, high modulation bandwidth, single longitudinal mode lasing, easy to achieve high-density two-dimensional array, and low production cost. Over the past three decades, vertical cavity surface emitting laser (VCSEL) has become the main light source for high-speed data communication and sensing applications due to its compact structure, fast response speed and high energy conversion efficiency. In particular, driven by applications such as face recognition (Face ID), infrared lighting, time-of-flight (ToF) proximity sensing, and 3D sensing in terminals such as smartphones, tablets and robots, the output of VCSEL chips and their modules has reached an unprecedented level of billions. As the detection distance increases, the density of the point cloud decreases, and the resolution is also limited. In order to achieve long-distance 3D scanning screen reconstruction, high-quality laser beams with higher power density and lower divergence angles are required. LiDAR and 3D sensing are expanding to new applications in consumer electronics, automotive and industrial markets. These new applications and new functions require smaller devices, higher power and efficiency. Compared with existing devices, single / multi-junction VCSEL arrays can achieve lower power consumption, higher slope efficiency, and higher peak optical power. The peak optical power, low heat dissipation and small size characteristics of these new multi-single / junction VCSEL arrays are very important for expanding their applications in high-performance all-solid-state medium and long-range LiDAR. Since the DBR part of the VCSEL is formed by alternating dozens of cycles of two materials with large energy band differences, the series resistance of the VCSEL structure itself is large (about 80~100Ω), which causes severe chip heating, thereby reducing the performance of the device. Especially for large-area array VCSELs, the thermal crosstalk between the light-emitting points leads to a high center temperature and ineffective heat dissipation. First, the large temperature difference between the center and the outer ring leads to different optoelectronic performance in different areas of the chip, making the output light intensity of the array chip uneven, affecting the chip performance of the entire VCSEL array. Secondly, the high center temperature leads to concentrated heat and ineffective heat dissipation. The center of the array VCSEL chip is prone to burn, causing the chip to fail prematurely. At present, the main way to improve the heat dissipation of single / multi-junction VCSEL chips is to electroplate a thicker metal layer on the surface, and use the higher thermal conductivity of the metal to improve the heat dissipation efficiency of the center temperature area on both sides. The metals with high thermal conductivity in the electroplating process are mainly high-priced metals such as gold, silver, and copper. In order to improve the lateral heat dissipation efficiency, the thickness of the electroplated metal layer is generally increased.However, an overly thick metal layer will introduce greater stress to the chip surface, which will lead to the risk of splitting and falling off between film layers. At the same time, the accumulated stress mismatch caused by an overly thick film layer is not conducive to the long-term use of the chip, causing the chip to fail prematurely. In addition, an overly thick film layer will greatly increase the consumption of the electroplating solution, increasing the processing cost of the chip. Summary of the invention

[0003] In order to solve the above problems, the present invention provides a planar array VCSEL with high heat dissipation efficiency. By growing a graphene material with high lateral thermal conductivity on the surface of the array VCSEL chip, the heat dissipation efficiency of the array VCSEL chip is improved, and the junction temperature of the central area of ​​each light-emitting unit is reduced, thereby improving the electro-optical conversion efficiency of the VCSEL chip.

[0004] The high heat dissipation efficiency planar VCSEL provided by the present invention comprises: Substrate and first DBR disposed on the substrate The first DBR is provided with a plurality of light-emitting units, the light-emitting units comprising: An active layer, which is used to provide laser gain, with spacer layers disposed above and below the active layer; A current limiting layer, which is disposed in the active layer and is used to limit the current path; A second DBR is disposed on an upper surface of the current limiting layer above the active layer, and a light reflectivity of the second DBR is lower than a light reflectivity of the first DBR; A first electrode and a second electrode are respectively disposed on a lower surface of the substrate and an upper surface of the second DBR; An insulating layer is provided on the side surface of the light-emitting unit and the bottom connecting plane of the adjacent light-emitting units, and a graphene heat dissipation layer is provided on the insulating layer.

[0005] Preferably, the substrate comprises at least one material selected from the group consisting of GaAs, InP and GaSb.

[0006] Preferably, the first DBR is a multi-period N-type DBR structure in which high and low refractive index semiconductor materials are alternately grown, and the second DBR is a multi-period P-type DBR structure in which high and low refractive index semiconductor materials are alternately grown.

[0007] Preferably, the active layer is a multi-quantum well structure.

[0008] Preferably, the band gap of the spacer layer is larger than the quantum well band gap of the active layer.

[0009] Preferably, the first electrode is an N-type contact electrode, the second electrode is a P-type contact electrode, and a P-type doped ohmic contact layer is provided between the second DBR and the first electrode.

[0010] Preferably, the heat distribution area of ​​the insulating layer of all the light-emitting units is obtained by simulation, and the heat distribution area is covered with a patterned graphene heat dissipation layer.

[0011] Compared with the prior art, the present invention can achieve the following beneficial effects: On the one hand, the present invention improves the heat dissipation performance of the array VCSEL chip and reduces the junction temperature of the center area of ​​the array by growing graphene material with high lateral thermal conductivity on the surface of the area array VCSEL chip, thereby improving the electro-optical conversion efficiency of the chip; compared with the existing electroplating metal layer method, the graphene heat dissipation layer used in the present invention has higher lateral thermal conductivity. The lateral thermal conductivity of graphene is more than 10 times that of metal. Therefore, the required thickness of the graphene heat dissipation layer is also much smaller than the electroplating metal layer. Reducing the thickness of the film on the surface of the area array VCSEL chip can avoid the problem of excessive stress and stress mismatch on the chip surface caused by excessive film thickness. The reduction of the film thickness also reduces the preparation cost of the area array VCSEL chip.

[0012] On the other hand, the graphene on the surface of the planar array VCSEL chip of the present invention can be patterned, and the graphene heat dissipation layer can be designed according to the single-tube layout and heat distribution of the array chip, which can improve the local heat dissipation problem, reduce the temperature difference between the light-emitting units in the array, ensure the uniform heat distribution of the light-emitting units in the VCSEL chip, and thus improve the uniformity of the light intensity distribution of the output light array; the planar array VCSEL with high heat dissipation efficiency of the present invention is suitable for the needs of single / multi-junction high-power VCSEL chips in scenarios such as laser radar and 3D sensing. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a structural diagram of a planar array VCSEL with high heat dissipation efficiency provided in Example 1 of the present invention; Figure 2 1 is a structural diagram of a planar VCSEL with high heat dissipation efficiency having a patterned graphene heat dissipation layer provided according to Example 2 of the present invention.

[0014] Reference numerals include: Substrate 100 , N-type DBR 101 , spacer layer 102 , active layer 103 , current limiting layer 104 , P-type DBR 105 , ohmic contact layer 106 , insulating layer 107 , P-type contact electrode 108 , N-type contact electrode 109 , graphene heat dissipation layer 110 . DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same modules are represented by the same reference numerals. In the case of the same reference numerals, their names and functions are also the same. Therefore, the detailed description thereof will not be repeated.

[0016] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0017] Since the multiple light-emitting units of the area array VCSEL are circular table-like structures formed by etching, there are deep etching grooves between adjacent light-emitting units. In order to meet the high power density requirements of area array VCSELs in application scenarios such as lidar and 3D sensing, it is necessary to increase the power density by reducing the etching spacing between the light-emitting units. This makes it difficult for the heat on the surface of the light-emitting units in the etching grooves to be transversely conducted, exacerbating the heat accumulation in the center area of ​​the area array VCSEL, reducing chip performance, and even causing the area array VCSEL to be burned.

[0018] To improve the heat dissipation efficiency of area array VCSEL, please refer to Figure 1 In Embodiment 1 of the present invention, a high heat dissipation efficiency planar array VCSEL based on graphene material is provided, which mainly includes a common substrate of the planar array VCSEL and a plurality of periodically arranged light-emitting units thereon. In Embodiment 1 of the present invention, the common substrate mainly includes a substrate 100 and an N-type DBR 101 grown on the upper surface of the substrate 100, wherein the substrate 100 can be made of III-V semiconductor materials such as GaAs, InP, or GaSb, and the substrate 100 can be made of a single material or a mixture of multiple materials, and the wavelength bands that the substrate 100 can cover are visible light, near infrared, mid-infrared, etc. A multi-period N-type DBR 101 composed of two semiconductor materials with different refractive indices grown alternately is arranged on the upper surface of the substrate 100. A high refractive index material and a low refractive index material are alternately grown once for one period. The thickness of the high refractive index material layer and the low refractive index material layer are both one-fourth of the optical thickness of the corresponding material. The N-type DBR 101 usually has 35 to 40 periods to ensure that the light reflectivity of the N-type DBR 101 can meet the design requirements. Under normal circumstances, it is believed that the reflectivity of the N-type DBR 101 should be greater than 99.9%.

[0019] The light-emitting units on the common substrate all have the same structure, and only differ in their spatial arrangement positions. Therefore, only the structure of any one of the light-emitting units will be described in detail.

[0020] Specifically, the light-emitting unit mainly includes: a spacer layer 102, an active layer 103, a current limiting layer 104 and a P-type DBR 105, wherein the active layer 103 is a key part for achieving high-efficiency electro-optical conversion, and is used to provide the laser gain required for laser emission. In an embodiment of the present invention, the active layer 103 is preferably designed as a multi-quantum well structure. In the quantum well, electrons and holes are confined in a very small space, resulting in a quantum size effect, so that the energy levels of electrons and holes are quantized to form discrete energy levels. These quantized energy levels help to improve the optical gain of the laser, and photons can be generated more efficiently when electrons and holes recombine.

[0021] A lattice-matched spacer layer 102 is provided on both the upper and lower sides of the active layer 103. Specifically, the spacer layer 102 below the active layer 103 is grown on the upper surface of the N-type DBR 101, and the spacer layer 102 above the active layer 103 is grown on the upper surface of the active layer 103. The lattice-matched spacer layer 102 can reduce stress and maintain the stability of the crystal structure. In addition, the design purpose of the spacer layer 102 is mainly to adjust the cavity length of the VCSEL laser to ensure that the laser wavelength meets the design requirements. It can be understood that the laser cavity length can be adjusted by changing the thickness of the spacer layer 102 on both sides of the active layer 103, thereby achieving the designed laser wavelength. In addition, the band gap of the spacer layer 102 is larger than the band gap of the quantum well in the active layer 103, so that the carrier restriction effect can be achieved, thereby improving the performance of the laser.

[0022] Furthermore, an annular current limiting layer 104 is provided in the spacer layer 102 above the active layer 103. The current limiting layer 104 is prepared by lateral oxidation of the spacer layer 102. Different lateral oxidation depths are achieved by changing the oxidation conditions, and finally the current limiting layer 104 with different ring widths is obtained. The inner ring central area of ​​the current limiting layer 104 is an unoxidized hole area, and the oxidized part forms a high resistance area. The current injected into the laser will be limited to pass only through the central unoxidized hole area, so as to limit the injected current path and improve the carrier density of the active area 103.

[0023] A multi-period P-type DBR105 is grown on the upper surface of the spacer layer 102 above the active layer 103. The P-type DBR105 is also composed of two semiconductor materials with different refractive indices grown alternately. One period is the alternating growth of a high refractive index material and a low refractive index material. The thickness of the high refractive index material layer and the low refractive index material layer are both one-fourth of the optical thickness of the corresponding material. Since the planar array VCSEL involved in the embodiment of the present invention is a top-emitting structure, the reflectivity of the P-type DBR105 should be designed to be less than the reflectivity of the N-type DBR101. It can be understood that it can ensure that the laser is emitted from the P-type DBR105.

[0024] N-type contact electrodes 109 and P-type contact electrodes 108 are respectively arranged on the lower surface of the substrate 100 and the upper surface of the P-type DBR 105, which correspond to the positive and negative electrodes of the area array VCSEL, respectively, and the laser is driven to work through the electrodes. In addition, in order to reduce the Schottky barrier between the low metal and semiconductor interface, the embodiment of the present invention also grows a ring-shaped ohmic contact layer 106 on the P-type DBR 105 and the P-type contact electrode 108, and the preparation material is a P-type highly doped semiconductor material, so that the P-type DBR 105 and the P-type contact electrode 108 form an ohmic contact, which reduces the voltage drop on the contact interface, thereby reducing the power loss of the laser.

[0025] Furthermore, the side surface of the light-emitting unit is a cylindrical surface, and an insulating layer 107 is provided on the cylindrical surface and the connecting plane at the bottom of different light-emitting units in the upper surface of the N-type DBR 101. It can be understood that, on the upper surface of the area array VCSEL, except for the P-type contact electrode 108 and the light outlet area, other areas are provided with an insulating layer 107. The function of the insulating layer 107 is to prevent the accidental leakage of current between different light-emitting units and ensure that each light-emitting unit can work independently. The space area between adjacent light-emitting units is the etched grooves existing after processing. As the power density of the area array VCSEL increases, the etched grooves between adjacent light-emitting units continue to shrink, which results in the heat generated by the light-emitting unit being unable to be effectively transversely conducted, increasing the heat dissipation pressure of the area array VCSEL. In the embodiment of the present invention, a graphene heat dissipation layer 110 is integrated on the insulating layer 107. Compared with the metal heat conductive layer, graphene has better heat dissipation performance, and its lateral heat dissipation efficiency is at least ten times that of the metal heat conductive layer. This can avoid plating too thick a heat dissipation layer on the side wall of the light-emitting unit, resulting in an imbalance in the extrusion stress of the side wall of the light-emitting unit. Excessive internal stress of the chip will reduce the service life of the chip and reduce reliability. According to the test, when the thickness of the graphene heat dissipation layer 110 is 500nm, its heat dissipation capacity has exceeded the heat dissipation effect of the traditional 5~8μm electroplated metal layer. According to the design requirements of the chip heat dissipation efficiency, the thickness of the graphene heat dissipation layer 110 can be further increased. In terms of process feasibility, considering the table depth of the single tube of the array chip at the same time, the thickness of the graphene heat dissipation layer 110 below 5μm can be well compatible with the existing VCSEL array chip structure.

[0026] See also Figure 2 In the second embodiment of the present invention, a planar VCSEL with a patterned heat dissipation layer and high heat dissipation efficiency is provided, which is different from the first embodiment only in that: The graphene heat dissipation layer 110 integrated on the insulating layer 107 is a patterned design. First, a thermal simulation is performed on the array VCSEL to obtain the distribution of heat dissipation on the insulating layer 107 of all light-emitting units, and the area that needs auxiliary heat dissipation is divided. Then, according to different array shapes, only specific areas are heat-dissipated. That is, according to the simulation results, only the areas with severe heat generation are covered with graphene to form a patterned graphene heat dissipation layer 110. Figure 2 In the two VCSELs of different array shapes shown in FIG, graphene is first grown on the insulating layer 107, and then the area where graphene needs to be grown is customized according to the heat distribution, and then the non-patterned area is removed by lift-off stripping technology, that is, the graphene in the area where auxiliary heat dissipation is not required is removed. The patterned graphene heat dissipation layer 110 can improve the local heat dissipation problem of the array VCSEL in a targeted manner, reduce the temperature difference between the light-emitting units in the array, and make the overall heat distribution and light intensity of the chip more uniform.

[0027] Based on the above structural description, in the embodiment of the present invention, a planar array VCSEL with high heat dissipation efficiency in the wavelength band of 850nm is taken as an example to illustrate its preparation process, which specifically includes the following steps: S1: The substrate 100 is made of N-type GaAs material, and Al (aluminum) with different Al (aluminum) components are alternately epitaxially grown on the N-type GaAs substrate 100 using organic metal chemical vapor deposition technology (MOCVD). x Ga 1-x As (aluminum gallium arsenic) semiconductor material, in this process, the high Al component x is usually between 0.9 and 1, while the low Al component x is between 0.1 and 0, and the typical DBR growth cycle number is about 35 to 40 cycles, so that a high-reflectivity N-type DBR101 (distributed Bragg reflector) can be prepared on an N-type GaAs substrate 100, and the reflectivity of the final prepared N-type DBR101 is required to be greater than 99.9%.

[0028] S2: epitaxially growing a spacer layer 102 of a certain thickness on the upper surface of the N-type DBR 101, wherein the material of the spacer layer 102 is lattice matched with the GaAs substrate 100; S3: Continue to epitaxially grow the active layer 103 of the multi-quantum well structure on the upper surface of the spacer layer 102. The typical quantum well structure with a wavelength of 850nm is GaAs / Al x Ga 1-x As, where the value of x is between 0.2 and 0.4, by adjusting the thickness of the quantum well or the Al component of the barrier, the light emitting band of the active layer 103 can be adjusted to cover 850nm.

[0029] S4: Continue to epitaxially grow the remaining thickness of the spacer layer 102 on the upper surface of the active layer 103 until a specific thickness is reached, that is, the overall optical thickness of the two parts of the spacer layer 102 (including the thickness of the current limiting layer 104 to be prepared later) and the active layer 103 is designed to be half a wavelength that is an integer multiple of the 850nm wavelength, thereby satisfying the standing wave condition of the laser. This design ensures that the laser can achieve efficient laser emission at a specific wavelength.

[0030] S5: Continue to grow the P-type DBR 105 on the spacer layer 102 above the active layer 103. The P-type DBR 105 is composed of Al with high and low Al components. x Ga 1-x The thickness of each layer of As semiconductor material is alternately grown according to one-quarter of the optical thickness of the material. The typical high Al component x=0.9~1, the low Al component x=0.1~0, the typical number of periods is about 20~25 periods, and the reflectivity of P-type DBR105 is lower than that of N-type DBR101, so that light is emitted from the top.

[0031] S6: An ohmic contact layer 106 of a P-type highly doped GaAs material is grown on the upper surface of the P-type DBR 105. The design of the ohmic contact layer 106 can reduce the Schottky barrier generated by the contact between the metal electrode and the semiconductor material, thereby reducing the resistance.

[0032] S7: After completing S1 to S6 above, the epitaxial growth process of the area array VCSEL with high heat dissipation efficiency has been completed, and the etching preparation process of the light-emitting unit is further carried out. First, the sample obtained in S6 is coated, photolithographic, and developed to form a mask pattern of the area array VCSEL. Then, the VCSEL table is dry-etched using an ICP etching device until the upper surface of the N-type DBR101 is exposed. During the etching process, a mixed gas of Cl2 / BCl3 / Ar can be used as the etching gas for GaAs. These gases can effectively remove the GaAs material while maintaining the flatness of the side wall.

[0033] S8: Use wet nitrogen oxidation equipment to perform transverse oxidation on the position of the preset current limiting layer 104 on the spacer layer 102, control the oxidation rate by adjusting parameters such as oxidation temperature, water vapor temperature, pressure, flow rate, and control the transverse oxidation depth by controlling time, and finally form a central unoxidized hole area in the spacer layer 102 above the active layer 103, and the oxidized part forms a high resistance area, i.e., the current limiting layer 104, and the current injected into the laser will be limited to pass only through the central hole area.

[0034] S9: After the current limiting layer 104 is prepared, an insulating material is deposited on the surface of the sample using PECVD equipment. Typical insulating materials are SiO2 or Si3N4.

[0035] S10: The sample is photolithographically processed again, and after the steps of photoresist coating, photolithography, and development, the active layer 103 on the side of the light-emitting unit and the spacer layer 102 under the active layer 103 that need to be exposed are determined, and dry etching is performed using RIE equipment until etching reaches a set depth, that is, an insulating layer 107 is formed on the side of the light-emitting unit and the bottom connecting plane of the adjacent light-emitting units. The typical etching gas used for etching is SiO2 or Si3N4, and CF4 / O2 can be selected.

[0036] S11: The sample is subjected to a third photolithography. After the steps of coating, photolithography, and development, the ohmic contact layer 106 and the P-type contact electrode 108 are evaporated by electron beam evaporation or magnetron sputtering. The P-type contact electrode 108 is the positive electrode of the area array VCSEL, and the typical positive electrode material is Ti / Pt / Au. After the evaporation is completed, the sample is subjected to a lift-off stripping process in an acetone solution to remove the unnecessary part of the preset light outlet position above the P-type DBR 105, and finally the P-type contact electrode 108 is formed.

[0037] S12: The sample is subjected to a fourth photolithography process. After the steps of coating, photolithography, and development, the area where graphene needs to be grown is determined, and a graphene heat dissipation layer 110 is grown on the surface of the sample using a CVD device. The general growth temperature of graphene can be controlled at 50-300° C. If a patterned graphene heat dissipation layer 110 is formed only in a designated area, the sample after the graphene growth needs to be stripped again to obtain the final required patterned graphene heat dissipation layer 110.

[0038] S13: The bottom of the substrate 100 of the sample is thinned and polished, and then the negative electrode is evaporated by electron beam evaporation or magnetron sputtering, that is, N-type DBR 101 is evaporated at the bottom of the substrate 100. The typical negative electrode material is Au-Ge / Ni / Au. Thus, the high heat dissipation efficiency area array VCSEL provided by the embodiment of the present invention is completed.

[0039] Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. Those skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

[0040] The above specific implementations of the present invention do not constitute a limitation on the protection scope of the present invention. Any other corresponding changes and modifications made based on the technical concept of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A planar VCSEL with high heat dissipation efficiency, comprising a substrate and a first DBR arranged on the substrate, characterized in that: The first DBR is provided with a plurality of light-emitting units, and the light-emitting units include: An active layer, which is used to provide laser gain, wherein spacer layers are provided above and below the active layer; A current limiting layer, which is disposed in the active layer and is used to limit the current path; a second DBR, which is disposed on an upper surface of the current limiting layer above the active layer, wherein the light reflectivity of the second DBR is lower than the light reflectivity of the first DBR; A first electrode and a second electrode are respectively disposed on a lower surface of the substrate and an upper surface of the second DBR; An insulating layer is provided on the side surface of the light-emitting unit and the bottom connecting plane of adjacent light-emitting units, and a graphene heat dissipation layer is provided on the insulating layer.

2. The high heat dissipation efficiency planar VCSEL according to claim 1, characterized in that: The substrate includes at least one material of GaAs, InP, and GaSb.

3. The high heat dissipation efficiency planar VCSEL according to claim 1, characterized in that: The first DBR is a multi-period N-type DBR structure in which high and low refractive index semiconductor materials are alternately grown, and the second DBR is a multi-period P-type DBR structure in which high and low refractive index semiconductor materials are alternately grown.

4. The high heat dissipation efficiency planar VCSEL according to claim 1, characterized in that: The active layer is a multi-quantum well structure.

5. The high heat dissipation efficiency planar VCSEL according to claim 4, characterized in that: The band gap of the spacer layer is larger than the quantum well band gap of the active layer.

6. The high heat dissipation efficiency planar VCSEL according to claim 1, characterized in that: The first electrode is an N-type contact electrode, the second electrode is a P-type contact electrode, and a P-type doped ohmic contact layer is provided between the second DBR and the first electrode.

7. The high heat dissipation efficiency planar VCSEL according to claim 1, characterized in that: The heat distribution area of ​​the insulating layer of all the light-emitting units is obtained by simulation, and the patterned graphene heat dissipation layer is covered in the heat distribution area.

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