An ultra-low power adaptive power supply circuit

Abstract

The present invention discloses an ultra-low power adaptive power supply circuit, which belongs to the field of integrated circuits. The present invention provides the minimum voltage of the circuit at a specific frequency by detecting whether the circuit is flipped. This principle naturally includes the influence factor of PVT, thereby saving power consumption to the greatest extent. It is a brand-new invention, and has the advantages of simple system and fast voltage switching. Because the present invention requires that the monitor circuit and other digital circuits in the SOC have a certain correlation. In view of the shortcomings of DVS, the present invention automatically adjusts the voltage according to the operating frequency, the actual process and the temperature. The voltage is almost the minimum voltage required for operation, so as to achieve the purpose of reducing power consumption to the greatest extent. Moreover, the circuit is very simple, and the voltage switching time is very short.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an ultra-low power consumption adaptive power supply circuit. Background Art

[0002] As people's quality of life improves, the functional requirements for various portable electronic products are getting higher and higher, and complex functions will lead to a significant increase in the power consumption of devices. People have higher requirements for the power consumption of portable electronic products. Lower power consumption can extend the working time of the chip, greatly improve the convenience of use and more application scenarios. At the same time, the battery also has a longer life and reduces damage to the environment. Therefore, low power consumption has always been the direction pursued by chips.

[0003] The power consumption of a chip is divided into dynamic power consumption and static power consumption. Dynamic power consumption is proportional to C*V 2 *F, where C is the circuit capacitance, which is determined when the circuit design is completed. V is the supply voltage, and F is the operating frequency. The operating frequency is determined based on demand. 2 Therefore, the voltage reduction will significantly reduce dynamic power consumption. Static power consumption is V*I, where I is the leakage current. In fact, the leakage current will also decrease with the decrease of voltage. From the above analysis, we can know that when the operating frequency is constant, reducing the voltage can reduce both dynamic and static power consumption.

[0004] In order to reduce power consumption, there is now a technology called DVS (dynamic voltage scaling). According to different operating frequencies, the system will dynamically adjust the supply voltage to achieve the purpose of reducing power consumption. However, this technology currently has the following disadvantages: 1. Due to the need to consider the impact of different processes and temperatures, there is actually a considerable margin in the supply voltage for a certain frequency, and the power consumption cannot be reduced to the limit; 2. The implementation of the system is quite complex, and the voltage switching takes a certain amount of time. Summary of the invention

[0005] The purpose of the present invention is to provide an ultra-low power consumption adaptive power supply circuit to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides an ultra-low power consumption adaptive power supply circuit, comprising: resistors R1-R5, PMOS tube P1, NMOS tubes N1-N3, capacitors C1-C2;

[0007] The source terminal of the PMOS transistor P1 is connected to VDD, the drain terminal is connected to the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to the first terminal of the resistor R2, the second terminal of the resistor R2 is connected to the first terminal of the resistor R3, the second terminal of the resistor R3 is connected to the drain terminal of the NMOS transistor N1, and the source terminal of the NMOS transistor N1 is connected to the ground VSS;

[0008] The gate end of the PMOS transistor P1 and the gate end of the NMOS transistor N1 are connected to the OUT point, and the connection point A of the second end of the resistor R2 and the first end of the resistor R3 is output to VCTRL1 through a first-order low-pass filter composed of a resistor R4 and a capacitor C1. VCTRL1 is connected to the gate end of the NMOS transistor N2, and the drain end of the NMOS transistor N2 is connected to VDD. The source end outputs the voltage Vmonitor;

[0009] The connection point B between the second end of the resistor R1 and the first end of the resistor R2 is output to VCTRL2 through a first-order low-pass filter composed of a resistor R5 and a capacitor C2. VCTRL2 is connected to the gate end of the NMOS tube N3. The drain end of the NMOS tube N3 is connected to VDD, and the source end output is Vsoc.

[0010] In one implementation, the ultra-low power adaptive power supply circuit further includes a monitoring circuit, the power supply of the monitoring circuit is the voltage Vmonitor, and the ground is VSS; the input of the monitoring circuit is the clock for the system SOC to work, and the output is to the OUT point.

[0011] In one implementation, when the power supply voltage Vmonitor of the monitoring circuit is so low that the monitoring circuit cannot work normally, the voltage at the output OUT point is 0; if the monitoring circuit can flip under the voltage Vmonitor, other logic circuits in the system SOC can also flip.

[0012] In one implementation, the resistance of the resistor R3 is much smaller than the resistance of the resistor R1 .

[0013] In one implementation, the NMOS transistors N1, N2 and N3 are all native transistors.

[0014] The ultra-low power consumption adaptive power supply circuit provided by the present invention has the following advantages:

[0015] (1) The present invention regulates the power supply voltage by determining whether the circuit is flipped, so the influence of PVT can be naturally taken into account, thereby providing the lowest power supply voltage and achieving the purpose of reducing power consumption;

[0016] (2) The circuit structure is very simple and the response speed is very fast, which reduces the complexity of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of an ultra-low power consumption adaptive power supply circuit provided by the present invention.

[0018] Figure 2 This is a voltage diagram at a 0.3ns clock period.

[0019] Figure 3 This is a voltage diagram under a 3ns clock period.

[0020] Figure 4 This is a voltage diagram under a 30ns clock period. DETAILED DESCRIPTION

[0021] The following is a further detailed description of an ultra-low power adaptive power supply circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] The present invention provides an ultra-low power consumption adaptive power supply circuit, the structure of which is as follows Figure 1 As shown, it includes resistors R1~R5, PMOS tube P1, NMOS tubes N1~N3, and capacitors C1~C2. The source end of PMOS tube P1 is connected to VDD, the drain end is connected to the first end of resistor R1, the second end of resistor R1 is connected to the first end of resistor R2, the second end of resistor R2 is connected to the first end of resistor R3, the second end of resistor R3 is connected to the drain end of NMOS tube N1, and the source end of NMOS tube N1 is connected to ground VSS. The gate end of PMOS tube P1 and the gate end of NMOS tube N1 are connected to the OUT point. There is a monitor circuit in the circuit, the power supply of this circuit is Vmonitor, and the ground is VSS. The input of the monitor circuit is the clock that the system SOC needs to work, which is output to the OUT point. The connection point A of the second end of resistor R2 and the first end of resistor R3 is output to VCTRL1 through a first-order low-pass filter composed of resistor R4 and capacitor C1. VCTRL1 is connected to the gate end of NMOS tube N2, the drain end of NMOS tube N2 is connected to VDD, and the source end output is Vmonitor. The connection point B between the second end of the resistor R1 and the first end of the resistor R2 is output to VCTRL2 through a first-order low-pass filter composed of a resistor R5 and a capacitor C2. VCTRL2 is connected to the gate end of the NMOS tube N3. The drain end of the NMOS tube N3 is connected to VDD, and the source end output is Vsoc.

[0023] The following is a description of the circuit of the present invention.

[0024] The monitor circuit is a logic circuit composed of various logic gates. There are two requirements for this circuit. First, when the Vmonitor voltage is so low that the circuit cannot work properly, the voltage at the output point OUT is 0. Second, if the monitor circuit can flip under the Vmonitor voltage, other logic circuits in the system SOC can also flip.

[0025] The working mechanism of the circuit is that when Vmonitor is so low that the circuit cannot flip, the voltage at point OUT is 0. At this time, the voltage at point A increases, causing VCTRL1 to increase, thereby causing Vmonitor to increase. After Vmonitor increases, the circuit can flip, and the normal flip of OUT will pull down the voltage at point A and thus reduce Vmonitor. To achieve this goal, the resistance value of resistor R3 is much smaller than the resistance value of resistor R1 to ensure that the voltage at point A decreases when OUT flips normally. Under this negative feedback mechanism, the Vmonitor voltage is guaranteed to be the lowest voltage corresponding to the frequency of the monitor circuit. Resistor R2 takes a smaller resistance in order to ensure that Vsoc, which actually powers the system SOC, is slightly higher than Vmonitor to ensure the stability of the circuit.

[0026] Because the voltage of Vmonitor may be very low when the frequency is low, the NMOS tubes N1, N2 and N3 all use native tubes to eliminate the influence of the threshold voltage Vth.

[0027] Resistor R4 and capacitor C1 are first-order low-pass filters used to filter voltage fluctuations at point A to stabilize the Vmonitor voltage. Similarly, resistor R5 and capacitor C2 are first-order low-pass filters used to filter voltage fluctuations at point B to stabilize the Vsoc voltage. The time constant of the low-pass filter depends on the lowest frequency at which the circuit can operate.

[0028] Based on TSMC22ULL ​​process, the actual circuit is simulated according to the above schematic diagram. In the actual circuit, VDD=0.8V, at TT / 25 0 The simulation is performed under C. The periods of the input clock are 0.3ns, 3ns and 30ns respectively. Figures 2 to 4 The input waveforms and voltage diagrams are shown below when the clock cycle is 0.3ns, 3ns and 30ns. It can be seen from the figure that when the clock cycle is 0.3ns, VCTRL1=658mv, Vmonitor=441mv, VCTRL2=669mv, and Vsoc=526mv.

[0029] When the clock cycle is 3ns, VCTRL1=435mv, Vmonitor=323mv, VCTRL2=458mv, Vsoc=376mv.

[0030] When the clock cycle is 30ns, VCTRL1=339mv, Vmonitor=268mv, VCTRL2=369mv, Vsoc=326mv.

[0031] From the trend, the voltage values ​​of each voltage decrease with the length of the clock cycle. This is in line with the design expectations of the present invention. It should be noted here that Vsoc is much higher than the value of Vmonitor because Vsoc in the simulation circuit does not have an actual load circuit, so the current is small and the voltage is raised. When there is an actual circuit, the load requires a larger current, which will lower the value of Vsoc.

[0032] The resistance value of the resistor R3 in the present invention is much smaller than that of R1, and generally one third of the resistance value of R1 can be used. In this way, when the OUT point is flipped normally, since the pull-down current is greater than the pull-up current, it can be ensured that the voltage of the A point and the B point of the monitor circuit drops when the monitor circuit is flipped normally; the three NMOS tubes N1, N2 and N3 use native tubes to eliminate the influence of the Vth of the MOS tube when the actual power supply voltage is low; Figure 1 When the voltage of the monitor circuit is too low and the circuit does not flip, the output voltage OUT is 0, thus ensuring that the circuit pulls up the supply voltage. The circuit ensures that the circuit works at the lowest supply voltage under this negative feedback mechanism.

[0033] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An ultra-low power adaptive power supply circuit, characterized in that: include: Resistors R1~R5, PMOS tube P1, NMOS tube N1~N3, capacitors C1~C2; The source terminal of the PMOS transistor P1 is connected to VDD, the drain terminal is connected to the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to the first terminal of the resistor R2, the second terminal of the resistor R2 is connected to the first terminal of the resistor R3, the second terminal of the resistor R3 is connected to the drain terminal of the NMOS transistor N1, and the source terminal of the NMOS transistor N1 is connected to the ground VSS; The gate end of the PMOS transistor P1 and the gate end of the NMOS transistor N1 are connected to the OUT point, and the connection point A of the second end of the resistor R2 and the first end of the resistor R3 is output to VCTRL1 through a first-order low-pass filter composed of a resistor R4 and a capacitor C1. VCTRL1 is connected to the gate end of the NMOS transistor N2, and the drain end of the NMOS transistor N2 is connected to VDD. The source end outputs the voltage Vmonitor; The connection point B of the second end of the resistor R1 and the first end of the resistor R2 is output to VCTRL2 through a first-order low-pass filter composed of a resistor R5 and a capacitor C2. VCTRL2 is connected to the gate end of the NMOS tube N3. The drain end of the NMOS tube N3 is connected to VDD. The source end output is Vsoc, which is used to power the system SOC. The ultra-low power adaptive power supply circuit also includes a monitoring circuit, the power supply of the monitoring circuit is a voltage Vmonitor, and the ground is VSS; the input of the monitoring circuit is a clock for the system SOC to work, and the output is to the OUT point; When the power supply voltage Vmonitor of the monitoring circuit is so low that the monitoring circuit cannot work normally, the voltage at the output OUT point is 0; if the monitoring circuit can flip under the voltage Vmonitor, other logic circuits in the system SOC can also flip; The resistance value of the resistor R3 is one third of the resistance value of the resistor R1.

2. The ultra-low power adaptive power supply circuit according to claim 1, characterized in that: The NMOS tubes N1, N2 and N3 are all native tubes.

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