Display panel and display device

Abstract

The invention discloses a display panel and a display device. A second display area of the display panel is located on at least one side of a first display area in the first direction. The display area comprises a plurality of data lines extending in the second direction; the first data line is arranged in the first display area; the second data line is arranged in the second display area; the non-display area comprises a plurality of multiplexers; the display area comprises a plurality of auxiliary wires; the demultiplexer comprises N switch elements; the first ends of the switch elements of the same demultiplexer are electrically connected with the input end of the demultiplexer; the N first data lines are electrically connected with the second ends of the N switch elements in the same first demultiplexer in a one-to-one correspondence manner; the N auxiliary wires are electrically connected with the second ends of the N switch elements in the same second demultiplexer in a one-to-one correspondence manner; the ratio of the number of the first multiplexers to the number of the second multiplexers ranges from 0.8 to 1.5. According to the technical scheme provided by the invention, the narrow frame design of the display panel is further realized.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the screen-to-body ratio of display panels is getting larger and larger, and narrow-border technology is attracting more and more attention.

[0003] In the border area of ​​some display panels, peripheral circuits such as multiplexing circuits and fan-out wiring are arranged to provide signals to the display area circuit of the display panel. However, as the size of the display panel increases, the multiplexing circuits and fan-out wiring will occupy more border area, which is not conducive to the development of narrow borders. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to further realize a narrow frame design of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, comprising: a display area and a non-display area at least partially surrounding the display area;

[0006] The display area includes a first display area and a second display area; the second display area is located at least on one side of the first display area along a first direction; the display area includes a plurality of data lines arranged along the first direction and extending along the second direction; the first direction and the second direction intersect; the data lines include a first data line and a second data line; the first data line is arranged in the first display area; the second data line is arranged in the second display area; the display area includes a plurality of auxiliary wirings;

[0007] The non-display area includes a plurality of demultiplexers; the auxiliary wiring transmits the signal output by the demultiplexer to the second data line;

[0008] Each of the demultiplexers comprises N switch elements; a first end of the switch element of the same demultiplexer is electrically connected to an input end of the demultiplexer;

[0009] The multiplexer includes a first multiplexer and a second multiplexer; along the first direction, N first data lines are electrically connected one-to-one with the second ends of N switching elements in the same first multiplexer; along the first direction, N auxiliary lines are electrically connected one-to-one with the second ends of N switching elements in the same second multiplexer; N is an integer greater than 1; wherein the ratio of the number of the first multiplexers to the number of the second multiplexers is in the range of 0.8 to 1.5.

[0010] In a second aspect, an embodiment of the present invention further provides a display device, wherein the display device comprises the display panel provided by any embodiment of the present invention.

[0011] In the present invention, the display panel includes a first display area and a second display area arranged on at least one side of the first display area along the first direction. The first display area includes a first data line extending along the second direction; the second display area includes a second data line. The non-display area includes a plurality of multiplexers, and the display area also includes an auxiliary line to transmit the signal output by the multiplexer to the second data line. Along the first direction, the N first data lines are connected to the second ends of the N switch elements in the first multiplexer in a one-to-one correspondence, and the N auxiliary lines are connected to the second ends of the N switch elements in the second multiplexer in a one-to-one correspondence. Among them, the ratio of the number of first multiplexers to the number of second multiplexers ranges from 0.8 to 1.5. That is, in this embodiment, the fan-out line in the existing panel is replaced by an auxiliary line to transmit the data signal to the second data line, thereby reducing the occupied space of the lower frame of the display panel and realizing the narrow frame design of the display panel. Moreover, the number of second multiplexers connected to the auxiliary lines in the non-display area is similar to or has a small difference with the number of first multiplexers connected to the first data lines, so that the second multiplexers are positioned on the lower frame to reduce the space occupied by the second multiplexer on the lower R corner, further realizing the narrow frame design of the lower R corner and leaving layout space for other lines of the lower R corner. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of the structure of a display panel in the prior art;

[0013] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0014] Figure 3 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0016] Figure 5 for Figure 4 A schematic diagram of a film structure of a multiplexer of a display panel;

[0017] Figure 6 for Figure 4 A schematic diagram of another film structure of a multiplexer of a display panel;

[0018] Figure 7 A schematic diagram of a film structure of a multiplexer of a display panel provided by an embodiment of the present invention;

[0019] Figure 8 A schematic diagram of a film layer structure of another multiplexer of a display panel provided by an embodiment of the present invention;

[0020] Fig. 9 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0021] Fig.10 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0022] Fig.11 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0023] Fig.12 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0024] Fig.13 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0025] Fig.14 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0026] Fig.15 for Fig.12 The middle panel shows a partial enlarged schematic diagram of the S1 region;

[0027] Fig.16 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0028] Fig.17 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0029] Fig.18 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0030] Fig.19 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0031] Fig. 20 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0032] Fig.21 A timing diagram of a control signal line provided by an embodiment of the present invention;

[0033] Fig. 22 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0034] Fig.23 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0035] Fig.24 A schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0036] Fig.25 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0038] Figure 1 It is a schematic diagram of the structure of the display panel in the prior art. The display panel includes a display area AA' and a non-display area NA'. The display area AA' includes a data line 11' extending along the direction Y' and arranged along the direction X'. The non-display area NA' is provided with peripheral wiring and peripheral circuits. Specifically, the non-display area NA' of the lower step area of ​​the display panel includes a fan-out wiring 16' and a binding area 15'. The data line 11' is electrically connected to the corresponding binding terminal of the binding area 15' through the fan-out wiring 16', and is used to transmit the signal of the binding terminal to the data line 11'. Among them, although the binding area 15' can be bent to the back of the display panel to reduce the width of the lower frame, the fan-out wiring 16' occupies a large amount of space in the lower frame, and the width of the lower frame is B1'. In particular, the R angle area 17' also needs to be designed with a fan-out wiring 16', which hinders the design of a narrow frame.

[0039] To solve the above problems, this embodiment adopts the technology of laying out part of the fan-out lines in the display area (Fanout in AA, FIAA), and adds metal lines in the display area as FIAA lines, which will reduce the number of fan-out lines set in the lower R angle, reduce the width of the lower R angle and the lower frame, and simultaneously set the number of multi-way distribution circuits corresponding to the FIAA lines, reduce the number of pins of the required driver chip, save the cost of the driver chip, and reduce the number of signals required to be provided by the driver chip. The reduction in the number of signals can enhance the signal quality output by the driver chip and improve the charging efficiency of the pixel circuit of the display panel. An embodiment of the present invention provides a display panel, such as Figure 2 and Figure 3 As shown, Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 3A partial structural diagram of a display panel provided by an embodiment of the present invention includes: a display area AA and a non-display area NA at least partially surrounding the display area AA.

[0040] The display area AA includes a first display area AA1 and a second display area AA2; the second display area AA2 is located at least on one side of the first display area AA1 along the first direction X; the display area AA includes a plurality of data lines 11 arranged along the first direction X and extending along the second direction Y; the first direction X and the second direction Y intersect; the data line 11 includes a first data line 111 and a second data line 112; the first data line 111 is located in the first display area AA1; the second data line 112 is located in the second display area AA2; the display area AA includes a plurality of auxiliary wirings 12;

[0041] The non-display area NA includes a plurality of demultiplexers 13; the auxiliary wiring 12 transmits the signal output by the demultiplexer 13 to the second data line 112;

[0042] Each demultiplexer 13 includes N switch elements T; a first end of the switch element T of the same demultiplexer 13 is electrically connected to an input end of the demultiplexer 13;

[0043] The multiplexer 13 includes a first multiplexer 131 and a second multiplexer 132; the N first data lines 111 are electrically connected one-to-one with the second ends of the N switch elements T in the same first multiplexer 131; the N auxiliary lines 12 are electrically connected one-to-one with the second ends of the N switch elements T in the same second multiplexer 132; N is an integer greater than 1; wherein the ratio of the number of first multiplexers 131 to the number of second multiplexers 132 is in the range of 0.8 to 1.5.

[0044] In an embodiment of the present invention, the display panel includes a first display area and a second display area arranged along a first direction on at least one side of the first display area. The first display area includes a first data line extending along a second direction; the second display area includes a second data line. The non-display area includes a plurality of multiplexers, and the display area also includes an auxiliary line to transmit the signal output by the multiplexer to the second data line. Along the first direction, the N first data lines are connected to the second ends of the N switch elements in the first multiplexer in a one-to-one correspondence, and the N auxiliary lines are connected to the second ends of the N switch elements in the second multiplexer in a one-to-one correspondence. Among them, the ratio of the number of first multiplexers to the number of second multiplexers ranges from 0.8 to 1.5. That is, in this embodiment, the auxiliary lines replace part of the fan-out lines in the non-display area of ​​the existing panel to transmit the data signal to the second data line, thereby reducing the occupied space of the lower frame of the display panel and realizing the narrow frame design of the display panel. Moreover, the number of second multiplexers connected to the auxiliary lines in the non-display area is similar to or has a small difference with the number of first multiplexers connected to the first data lines, so that the second multiplexers are positioned on the lower frame to reduce the space occupied by the second multiplexer on the lower R corner, further realizing the narrow frame design of the lower R corner and leaving layout space for other lines of the lower R corner.

[0045] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] The display panel includes a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA may be arranged around the display area AA, or may be arranged around a partial area of ​​the display area AA. This embodiment is illustrated by taking the non-display area NA being arranged around the display area AA as an example. The display area AA is provided with data lines 11 extending along the second direction Y and arranged along the first direction X, wherein the first direction X and the second direction Y intersect, and optionally, the first direction X and the second direction Y may be perpendicular to each other. The data lines 11 may be divided into first data lines 111 and second data lines 112. Optionally, the display area AA may be divided into a first display area AA1 and a second display area AA2 according to the above classification of the data lines. The first display area AA1 is provided with a first data line 111, and the second display area AA2 is provided with a second data line 112. As Figure 2 As shown, along the first direction X, the second display area AA2 is located on at least one side of the first display area AA1. Figure 2As shown, the display area AA may include two second display areas AA2, and the two second display areas AA2 are respectively arranged on opposite sides of the first display area AA1. The display area AA may also include only one second display area AA2, which is only arranged on one side of the first display area AA1. In summary, the second display area AA2 is closer to the edge of the display panel than the first display area AA1. Figure 2 The second display area AA2 is arranged close to the R angle area 17 relative to the first display area AA1.

[0047] The non-display area NA also includes a plurality of demultiplexers 13. Optionally, the non-display area NA may also include: a binding area 15; the binding area 15 is located on a side of the demultiplexer 13 away from the display area AA; the input end of the demultiplexer 13 is electrically connected to the corresponding binding terminal 151 of the binding area 15. Specifically, Figure 3 As shown, the non-display area NA of the lower step area of ​​the display panel can be provided with a multiplexer circuit area 14 and a binding area 15. The multiplexer circuit area 14 includes a plurality of multiplexers 13, and the binding area 15 includes a plurality of binding terminals 151. The binding terminal 151 is electrically connected to the input end of the corresponding multiplexer 13 through a fan-out line 16, and the output end of the multiplexer 13 is electrically connected to the corresponding data line 11, so that the signal obtained by the binding terminal 151 can be finally transmitted to the corresponding data line 11. The multiplexer 13 includes a first multiplexer 131 and a second multiplexer 132. The first multiplexer 131 is used to transmit the signal obtained by the binding terminal 151 to the first data line 111, and the second multiplexer 132 is used to transmit the signal obtained by the binding terminal 151 to the second data line 112. It should be noted that the display area AA further includes a plurality of auxiliary wirings 12, and the auxiliary wirings 12 are used to connect the second demultiplexer 132 and the second data line 112, and are used to transmit the signal output by the second demultiplexer 132 to the second data line 112. In this embodiment, the auxiliary wirings 12 are arranged in the display area AA, and the second data line 112 of the second display area AA2 close to the R angle area 17 is connected to the demultiplexer 13 through the auxiliary wirings 12, and there is no need to arrange a fan-out wiring. In other words, the position of the fan-out wiring of the second data line 112 is moved to the display area AA, thereby reducing the space occupied by the non-display area of ​​the lower step. For example, Figure 2 As shown, the bottom border width is B1. Figure 1 In the prior art, the width B1' of the lower frame of the display panel is reduced, and the width occupied by the fan-out wiring is effectively shortened in this embodiment, thereby further realizing the narrow frame design of the display panel. It can be understood that in order to distinguish the auxiliary wiring 12 from the data line 11, the auxiliary wiring 12 of this embodiment is represented by a dotted line, and the data line 11 is represented by a solid line.

[0048] refer to Figure 3 , the specific structure of each multiplexer 13 includes N switching elements T, where N is an integer greater than 1. The switching element T includes a control end (optionally, it can be a gate), a first end, and a second end. The on and off of the switching element T can be controlled by adjusting the control signal of the control end of the switching element T. Exemplarily, when the control signal is at a high level, the switching element T is turned on; when the control signal is at a low level, the switching element T is turned off. Alternatively, when the control signal is at a high level, the switching element T is turned off; when the control signal is at a low level, the switching element T is turned on. The first ends of the N switching elements T of the same multiplexer 13 are electrically connected to the input end of the multiplexer 13, and the second ends serve as N output ends of the multiplexer 13 respectively. As Figure 2 As shown, along the first direction X, the second ends of the N switch elements T of the same multiplexer 13 are electrically connected to the N data lines 11 in a one-to-one correspondence, so as to transmit the signal to the corresponding data line 11. Specifically, in this embodiment, the second ends of the N switch elements T of the first multiplexer 131 are electrically connected to the N first data lines 111 in a one-to-one correspondence; the second ends of the N switch elements T of the second multiplexer 132 are electrically connected to the N auxiliary wirings 12 in a one-to-one correspondence, and the N auxiliary wirings 12 are electrically connected to the N second data lines 112 in a one-to-one correspondence. In addition, optionally, the non-display area NA also includes N switch control lines; the control ends of the N switch elements T of the same multiplexer 13 are electrically connected to the switch control lines in a one-to-one correspondence. Specifically, the corresponding multiplexer 13 can be provided with N control signal lines, and the N control signal lines are arranged in a one-to-one correspondence with the control ends of the N switch elements T, for time-sharing conduction of the N switch elements T. Optionally, the value of N in this embodiment can be set according to the size of the display panel and the number of data lines. like Figure 2 As shown, when the number of data lines is small, each demultiplexer 13 may include two switch elements T, and the display panel is provided with two control signal lines MUX1 and MUX2. Figure 4 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, when the number of data lines is large, each demultiplexer 13 includes four switch elements T, and the display panel is provided with four control signal lines MUX1, MUX2, MUX3 and MUX4. Of course, N can have other values, which are not listed here one by one.

[0049] Optionally, in order to facilitate the subsequent distinction between the first multiplexer 131 and the second multiplexer 132, in this embodiment, the switch element T of the first multiplexer 131 may be referred to as the first switch element T1, and the switch element T of the second multiplexer 132 may be referred to as the second switch element T2. In this embodiment, the ratio of the number of first multiplexers 131 to the number of second multiplexers 132 is in the range of 0.8 to 1.5. Then, the difference in the number of the first multiplexer 131 and the second multiplexer 132 is small. In this embodiment, while adding the auxiliary wiring 12, the number of the auxiliary wiring 12 is effectively controlled, that is, the ratio of the number of the first data line 111 to the second data line 112 is controlled, so that the ratio of the number of the first data line 111 to the second data line 112 is in the range of 0.8 to 1.5. While ensuring that the R-angle area 17 is not provided with fan-out wiring, the setting position of the multiplexer 13 is effectively controlled, so that the multiplexer 13 is set away from the R-angle area and concentrated in the middle area of ​​the lower frame, further reducing the frame width of the R-angle area, realizing the narrow frame design of the R angle, and leaving layout space for other wiring in the lower R-angle area. It can be understood that when the ratio of the number of the first multiplexers 131 to the number of the second multiplexers 132 is less than 0.8, along the first direction, the width of the lower frame of the display panel will be relatively wide, and when the binding area is bent to the side away from the light-emitting surface of the display panel, the width of the lower frame of the display panel will affect the assembly effect of the display panel module; when the ratio of the number of the first multiplexers 131 to the number of the second multiplexers 132 is greater than 1.5, the large number of second data lines will result in a large number of auxiliary wiring in the display area, affecting the layout of the display area and affecting the pixel circuit of the middle display area.

[0050] Optionally, along the first direction X, adjacent N first data lines 111 can be electrically connected one-to-one with the second ends of N switching elements T in the same first multiplexer 131; along the first direction X, adjacent N auxiliary lines 12 can be electrically connected one-to-one with the second ends of N switching elements T in the same second multiplexer 132.

[0051] Continue to refer Figure 3 In this embodiment, the N data lines 11 connected to the same demultiplexer 13 may be N data lines 11 adjacent to each other along the first direction X. Specifically, the adjacent N first data lines 111 are electrically connected to the second ends of the N first switch elements T1 in the same first demultiplexer 131 in a one-to-one correspondence; the adjacent N second data lines 112 are electrically connected to the adjacent N auxiliary wirings 12 in a one-to-one correspondence; and the adjacent N auxiliary wirings 12 are electrically connected to the second ends of the N second switch elements T2 in the same second demultiplexer 132 in a one-to-one correspondence. Figure 3 and Figure 4As shown, when the adjacent N first data lines 111 are connected to the same first demultiplexer 131, the first connection lead 161 connecting the first data line 111 and the second end of the first switch element T1 can be set shorter, thereby reducing the path resistance value for transmitting signals to the first data line 111 and improving the display accuracy of the display panel. There is no risk of crossing between two adjacent first connection leads 161. For example, along the first direction, the wth first data line 111 among the adjacent N first data lines 111 is electrically connected to the wth first switch element T1 of the first demultiplexer 131, where w is a positive integer less than or equal to N. All first connection leads 161 can be set on the same layer, saving the manufacturing process of the display panel and improving the manufacturing efficiency of the display panel. It is understandable that when the adjacent N auxiliary wirings 12 are connected to the same second demultiplexer 132, the second connecting lead 162 connecting the auxiliary wiring 12 and the second end of the second switch element T2 can be set shorter, thereby reducing the path resistance value for transmitting the signal to the second data line 112, and improving the display accuracy of the display panel. And there is no risk of crossing between two adjacent second connecting leads 162, and all second connecting leads 162 can be set in the same layer, saving the manufacturing process of the display panel and improving the manufacturing efficiency of the display panel. Optionally, when the first connecting lead is set in the same layer, the second connecting lead is also set in the same layer, and the two are located in different metal film layers, it can be ensured that the material of the first connecting lead connected to the multiple first data lines is the same, and it can also be ensured that the material of the second connecting lead connected to the multiple second data lines is also the same, which is beneficial to the display effect.

[0052] Optionally, the ratio of the number of the first multiplexers 131 to the number of the second multiplexers 132 can be in the range of 1 to 1.25. While keeping the difference between the number of the first multiplexers 131 and the number of the second multiplexers 132 small, this embodiment controls the number of the first multiplexers 131 to be greater than or equal to the second multiplexers 132, so as to ensure that there is enough space in the first display area AA1 to arrange the auxiliary wiring 12, avoid the setting density of the auxiliary wiring 12 in the first display area AA1 to be greater than the setting density of the second display area AA2, ensure that the setting density of the auxiliary wiring 12 in the first display area AA1 and the second display area AA2 is uniform, and improve the display uniformity of the display panel. In addition, the second data line 112 in the second display area AA2 does not need to be set with a corresponding fan-out wiring, but is electrically connected to the multiplexer 13 through the auxiliary wiring 12, which effectively reduces the border width of the R angle area, which is conducive to the narrow border design of the display panel.

[0053] Optionally, the auxiliary routing 12 may include a first auxiliary routing 121 extending along the first direction X and a second auxiliary routing 122 extending along the second direction Y; the first auxiliary routing 121 is used to connect the corresponding second data line 112 and the second auxiliary routing 122; the second auxiliary routing 122 is electrically connected to the second end of the switching element T in the second multiplexer 132.

[0054] refer to Figure 3 and Figure 4 The auxiliary wiring 12 includes a first auxiliary wiring 121 and a second auxiliary wiring 122 which are electrically connected. The first auxiliary wiring 121 extends along the first direction X and is electrically connected to the corresponding second data line 112, and the second auxiliary wiring 122 is electrically connected to the corresponding second switch element T2 of the corresponding second demultiplexer 132. Figure 2 In this embodiment, the display area AA may include pixel driving circuits 31 arranged in an array. The data lines 11 and the auxiliary wiring 12 are arranged in the gaps between adjacent pixel driving circuits 31. Exemplarily, the pixel driving circuits 31 are arranged in rows along the first direction X and in columns along the second direction Y. The first auxiliary wiring 121 is arranged in the gaps between two adjacent rows of pixel driving circuits 31, and the second auxiliary wiring 122 is arranged in the gaps between two adjacent columns of pixel driving circuits 31. Optionally, the display panel further includes an auxiliary line segment 12a. Since the second auxiliary wiring 122 does not extend to the entire display area AA along the second direction Y, the auxiliary line segment 12a can fill in the display area space that the second auxiliary wiring 122 does not extend to, and the auxiliary line segment 12a is disconnected from the second auxiliary wiring 122. The auxiliary line segment 12a can be connected to a power signal or other reference signal, thereby reducing the voltage drop of the power signal or the reference signal. In a plane parallel to the entire display panel, the auxiliary line segment 12a and the second auxiliary line 122 are evenly distributed in the display area, improving the uniformity of the layout of the auxiliary line 12 and the auxiliary line segment 12a in the display area AA, thereby improving the uniformity of the display of the display panel. Optionally, in this embodiment, the first display area AA1 and the second display area AA2 are both provided with auxiliary line segments 12a extending along the second direction Y, so that the auxiliary line 12 and the auxiliary line segment 12a form a grid in the entire display area AA, reducing the energy loss of the power signal or other reference signal, avoiding the situation where the auxiliary line 12 is only set in a partial area, affecting the signal of other partial lines such as the data line, avoiding the problem of uneven display brightness in different areas of the display panel, and improving the display effect of the display panel.

[0055] Optionally, the non-display area may include a multiplexer area 14; the multiplexer area 14 is provided with a multiplexer 13. It should be noted that in the present embodiment, a fan-out area is formed between the display area AA and the binding area 15, and the fan-out area includes the multiplexer area 14. The fan-out area may include connecting leads (a first connecting lead 161 and a second connecting lead 162) connecting the data line 11 and the multiplexer 13, the multiplexer 13, and a fan-out routing 16 connecting the multiplexer 13 and the binding terminal 151. In the present embodiment, the multiplexer area 14 is used to set the multiplexer 13. In the present embodiment, the multiplexer 13 is centrally arranged in the lower frame area and away from the R corner area through the auxiliary routing 12.

[0056] Optionally, in the first display area AA1, the virtual extension line of the second auxiliary wiring 122 along the second direction Y may have an overlapping area with the second demultiplexer 132 connected thereto. Figure 4 , the second auxiliary wiring 122 connected to the second multiplexer 132 is arranged in the first display area AA1. In this embodiment, the position of the second multiplexer 132 can be controlled so that the virtual extension line of the second auxiliary wiring 122 along the second direction Y can overlap with the second multiplexer 132 connected thereto, so that the second multiplexer 132 is connected to the second data line 112 nearby, and the second connecting lead 162 is arranged with a shorter length, directly electrically connecting the second data line 112 with the corresponding second switch element T2, reducing the resistance of the transmission path of the second data line 112, reducing the signal transmission loss, and the shorter second connecting lead 162 can further reduce the circuit complexity of the fan-out area. In this embodiment, by adjusting the setting position of the second multiplexer 132, the circuit layout space of the fan-out area is reasonably utilized, and the width of the lower frame is further reduced. Similarly, in the first display area AA1, the virtual extension line of the first data line 111 along the second direction Y may have an overlapping area with the first multiplexer 131 connected thereto, the first multiplexer 131 is connected to the first data line 111 nearby, and the first connecting lead 161 is set to be shorter, thereby reducing the resistance of the transmission path of the first data line 111, further reducing the circuit complexity of the fan-out area, and facilitating the design of a narrow frame.

[0057] Continue to refer Figure 4Optionally, the non-display area NA may include a multiplexer area 14; the multiplexer area 14 is provided with a multiplexer 13; the virtual extension line of the second data line 112 along the second direction Y does not overlap with the multiplexer area 14. The second data line 112 is arranged in the second display area AA2. In this embodiment, the starting position of the multiplexer area 14 along the first direction X can be controlled to be aligned with the starting position of the first data line 111 or there is only a small distance. Then the multiplexer area 14 is arranged in the lower frame area corresponding to the first display area AA1, and does not overlap with the virtual extension line of the second data line 112 along the second direction Y. In this embodiment, the multiplexer area 14 is close to the first display area AA1, so the multiplexer 13 can be connected to the second auxiliary wiring 122 or the first data line 111 in the first display area AA1, further reducing the area of ​​the fan-out area occupied by the connecting lead, thereby realizing the narrow frame design of the display panel.

[0058] In this embodiment, in order to reduce the number of connection leads as much as possible, multiple rows of switch elements T extending along the first direction X and arranged along the second direction Y can be formed in the fan-out region. Each row of switch elements T can be connected to the corresponding second auxiliary trace 122 or first data line 111 nearby, reducing the width of the lower frame occupied by the connection leads, and realizing a narrow frame design of the display panel. In this embodiment, the switch elements T can be divided into multiple rows according to different principles.

[0059] The following is the first one: Figure 5 for Figure 4 A schematic diagram of a film structure of a multiplexer of a display panel, Figure 6 for Figure 4 Another schematic diagram of the film structure of the multiplexer of the display panel is shown in FIG. Figures 4 to 6 As shown, optionally, the first multiplexer 131 may include N first switching elements T1 arranged in sequence along the first direction X; the second multiplexer 132 includes N second switching elements T2 arranged in sequence along the first direction X; the switching element T includes an active layer 21; the active layer 21 of the switching element T of the first multiplexer 131 is located on the side of the active layer 21 of the switching element T of the second multiplexer 132 away from the display area AA; along the first direction X, the i-th first switching element T1 of the first multiplexer 131 and the i-th second switching element T2 of the second multiplexer 132 share a gate 22; 1≤i≤N; i is a positive integer.

[0060] In this embodiment, the second demultiplexer 132 is disposed between the first demultiplexer 131 and the first display area AA1. This reduces the length of the second connection lead 162. Since the auxiliary wiring 12 is added to the signal transmission path of the second data line 112 relative to the signal transmission path of the first data line 111, and the signal loss degree thereof is greater than that of the signal transmission path of the first data line 111, the length of the second connection lead 162 in the signal transmission path of the second data line 112 can be reduced in this embodiment. Figure 5 As shown, the second data line 112 is connected to the second switch element T2 through a shorter second connecting lead 162, thereby effectively reducing the length of the signal transmission path of the second data line 112. In this embodiment, the signal loss degree in the signal transmission path of the second data line 112 is equivalent to the signal loss degree in the signal transmission path of the first data line 111, thereby improving the uniformity of the picture display of the display panel. Optionally, a bus vref2 of a second reference voltage signal is provided on one side of the second multiplexer 132 close to the display area. The second reference voltage signal is a signal that provides a reset signal for the anode in the pixel driving circuit. The bus vref2 of the second reference voltage signal extending along the first direction X can effectively reduce the voltage drop of the second reference voltage during the transmission process.

[0061] Specifically, the display panel may be provided with a substrate and a driving circuit layer in sequence in a direction perpendicular to the thickness of the film layer. The switch element T is provided on the driving circuit layer, and the switch element T may be provided with an active layer 21, a gate 22 (control terminal), and a source and drain (a first terminal 231 and a second terminal 232) in sequence in a direction away from the substrate. Figure 6 The film layer relative to Figure 5The structure of the source and drain metal layer is omitted to facilitate understanding of the structure of the active layer 21 and the gate 22. In this embodiment, the multiplexer 13 is arranged in two rows, the second multiplexer 132 is arranged in a row close to the display area AA, and the first multiplexer 131 is arranged in a row away from the display area AA. The first multiplexer 131 includes N first switch elements T1 arranged in sequence along the first direction X, and the second multiplexer 132 includes N second switch elements T2 arranged in sequence along the first direction X. Along the first direction X, two adjacent switch elements T can share the first end 231. In this embodiment, the active layer 21 of the second switch element T2 is arranged on the side of the active layer 21 of the first switch element T1 close to the first display area AA1. Because the number of the first switch elements T1 is equal to the number of the second switch elements T2, and the N switch elements T in each multiplexer 13 are respectively connected to the corresponding control signal lines. In this embodiment, the i-th first switch element T1 of the first multiplexer 131 and the i-th second switch element T2 of the second multiplexer 132 can be set to share the gate 22, and connected to the corresponding control signal line through the shared gate 22, then the gate 22 can be a bar extending along the second direction Y, reducing the circuit complexity of the multiplexer 13 and improving the manufacturing efficiency and reliability of the display panel. In this embodiment, because the second multiplexer 132 is arranged close to the display area AA, the second end 232 of the second switch element T2 is connected to the second auxiliary wiring 122, and the first end 231 of the second switch element T2 is connected to the fan-out wiring 16. The second end 232 of the first switch element T1 is connected to the fan-out wiring 16 through the connecting lead ( Figure 5 The first end 231 of the second switch element T2 is connected to the fan-out line 16.

[0062] Optional, Figure 7 A schematic diagram of a film structure of a multiplexer of a display panel provided by an embodiment of the present invention, Figure 8 A schematic diagram of the membrane structure of another display panel multiplexer provided in an embodiment of the present invention. Optionally, the multiplexer 13 may include a first element group 133 and a second element group 134; the first element group 133 and the second element group 134 both include a plurality of switch elements T arranged in sequence along a first direction X; the switch element T includes an active layer 21; the active layer 21 of the switch element T of the second element group 134 is located on a side of the active layer 21 of the switch element T of the first element group 133 away from the display area AA; along the first direction X, the pth switch element T of the first element group 133 and the eth switch element T of the second element group 134 share a first end; 1≤p≤N; 1≤e≤N; p and e are positive integers.

[0063] At this time, along the first direction X, each multiplexer 13 is divided into two rows. Specifically, both the first multiplexer 131 and the second multiplexer 132 may include a first element group 133 and a second element group 134. In the same multiplexer 13, the number of switch elements T in the first element group 133 may be N1, and the number of switch elements T in the second element group 134 may be N2, and the sum of N1 and N2 is N. The first element group 133 and the second element group 134 both include a plurality of switch elements T arranged in sequence along the first direction X. The first element group 133 is disposed on a side of the second element group 134 close to the display area AA. Specifically, as shown in FIG. Figure 7 As shown, the switch element T may be sequentially provided with an active layer 21 , a gate 22 (control terminal) and a source and drain (a first terminal 231 and a second terminal 232 ) in a direction away from the substrate. Figure 8 Relative to Figure 7 , the source and drain film layers are omitted to facilitate understanding of the structure of the active layer 21 and the gate 22. The active layer 21 of the switch element T of the first element group 133 is located on the side of the active layer 21 of the switch element T of the second element group 134 close to the display area AA. The first element group 133 of each multiplexer 13 is arranged in a row close to the display area AA, and the second element group 134 of each multiplexer 13 is arranged in a row away from the display area AA. Figure 7 In this embodiment, the p-th switch element T of the first element group 133 and the e-th switch element T of the second element group 134 share the first end 231, and the fan-out trace 16 is connected through the shared first end 231. In this embodiment, the first end 231 can be a bar extending along the second direction Y, which reduces the circuit complexity of the multiplexer 13 and improves the manufacturing efficiency and reliability of the display panel. Optionally, N1=N2 can be set, and the p-th switch element T of the first element group 133 and the p-th switch element T of the second element group 134 can be set to share the first end 231, so that all the first ends 231 form a bar extending along the second direction Y, so as to further reduce the circuit complexity of the multiplexer 13 and improve the manufacturing efficiency of the display panel.

[0064] Continue to refer Figure 7Optionally, along the first direction X, the first multiplexer 131 and the second multiplexer 132 may be alternately arranged. Because each multiplexer 13 is arranged in two rows along the second direction Y, and the first data line and the second auxiliary line in the first display area are alternately arranged, in this embodiment, the first multiplexer 131 and the second multiplexer 132 may be alternately arranged along the first direction X, so that the multiplexer 13 can be connected to the corresponding second auxiliary line 122 or the first data line 111 in the first display area AA1 nearby, further reducing the area of ​​the fan-out area occupied by the connecting lead, thereby realizing a narrow frame design of the display panel. In addition, the setting principle of arranging the multiplexer 13 nearby reduces the resistance of the transmission path of the first data line 111 and the resistance of the transmission path of the second data line 112, thereby reducing the loss of the signal during the transmission process and improving the accuracy of the data line providing the signal to the pixel driving circuit.

[0065] In this embodiment, the display panel can use low temperature polysilicon (LTPS) technology, so that the display panel can be made thinner and smaller, and the power consumption is lower. In addition, the display panel can also use low temperature polycrystalline oxide (LTPO) technology, which combines LTPS technology and indium gallium zinc oxide IGZO technology, has higher mobility and lower leakage current, thereby achieving lower power consumption and better display effect. This embodiment takes the LTPO display panel as an example to illustrate the film layer of the display panel. Fig. 9 and Fig.10 As shown, Fig. 9 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, Fig.10 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention. Optionally, the switch element T may include a dual-gate structure; the dual-gate structure may include a first gate structure 221 and a second gate structure 222; the first gate structure 221 and the second gate structure 222 are arranged in different film layers.

[0066] Fig. 9 The figure shows a partial structure diagram of the LTPS display panel. Fig.10 The partial structure diagram of the LTPO display panel is shown. Regardless of the type of panel, the present embodiment can be provided with a dual-gate structure. That is, gate structures are provided in different film layers, and the gate structures in different film layers are connected to the same control signal. Fig. 9 and Fig.10The dual-gate structure may include a first gate structure 221 and a second gate structure 222, and the first gate structure 221 and the second gate structure 222 are respectively arranged in different metal layers. The arrangement of the first gate structure 221 and the second gate structure 222 can effectively increase the transmission efficiency of the control signal and speed up the turn-on and turn-off speed of the gate of the switching element T. In addition, the gate structures of different film layers can be electrically connected to each other to further reduce the resistance of the gate structure, reduce the loss of the control signal on the gate structure, and improve the control accuracy of the switching element T.

[0067] Continue to refer Fig. 9 Optionally, the display panel may include at least: a substrate 41; a blocking metal layer 40, located on the substrate 41; the blocking metal layer 40 includes a first gate structure 221 of the switching element T; a first active layer 43, located on a side of the blocking metal layer 40 away from the substrate 11; the first active layer 43 includes an active layer 21 of the switching element T; a first gate layer 44, arranged on a side of the first active layer 43 away from the substrate 11; the first gate layer 44 includes a second gate structure 222 of the switching element T; an intermediate metal layer 45, arranged on a side of the first gate layer 44 away from the substrate 11; a source-drain layer 46, arranged on a side of the intermediate metal layer 45 away from the substrate 11; the source-drain layer 46 includes a first end 231 and a second end 232 of the switching element T.

[0068] The display panel generally includes a substrate 11, and a driving circuit layer and a light emitting element layer sequentially arranged on one side of the substrate 11. The driving circuit layer is provided with a plurality of pixel driving circuits, and the light emitting element layer is provided with light emitting elements arranged in an array. The pixel driving circuit can provide working current for the corresponding light emitting element. Fig. 9 As shown, Fig. 9Only the structure of the driving circuit layer is shown, and the light-emitting element layer is not illustrated. It can be understood that the pixel driving circuit is electrically connected to the corresponding light-emitting element to provide an operating current for the light-emitting element. When the process of the display panel is LTPS, the display panel may include a substrate 41 and a shielding metal layer 40, a first active layer 43, a first gate layer 44, an intermediate metal layer 45 and a source-drain layer 46 sequentially arranged on the substrate 41. Among them, the substrate 41 may include a multi-layer stacked structure, specifically including materials such as polyethylene terephthalate, polyetheretherketone, and polystyrene. The shielding metal layer 40 is arranged on the substrate 41. It should be noted that in this embodiment, "on the substrate" represents a positional relationship, and the shielding metal layer 40 is arranged on the side of the substrate 11 close to the light-emitting element. Optionally, other film layers, such as an inorganic insulating layer, may also be arranged between the shielding metal layer 40 and the substrate 41. The shielding metal layer 40 includes a first gate structure 221 of the switching element T, the first active layer 43 includes the active layer 21 of the switching element T, and a buffer layer 42 may be provided between the shielding metal layer 40 and the first active layer 43. The first gate layer 44 includes a second gate structure 222 of the switching element T, the intermediate metal layer 45 is generally used to set the capacitor plate, and the source-drain layer 46 includes a first end 231 and a second end 232 of the switching element T. In this embodiment, the control signal is provided to the switching element T at the same time through the first gate structure 221 and the second gate structure 222, thereby improving the control accuracy of the switching element T.

[0069] Continue to refer Fig. 9 Optionally, the blocking metal layer 40 may further include a blocking portion 401 of the display area AA; the blocking portion 401 at least partially overlaps with the driving transistor T3 of the display area AA; the blocking portion 401 is connected to a preset potential; the preset potential is a first power signal, a second power signal or a reference voltage signal.

[0070] The driving transistor T3 and the switch element T in the display area AA of the display panel can be formed by the same process. Specifically, the gate of the driving transistor T3 is arranged on the first gate layer 44, the active layer of the driving transistor T3 is arranged on the first active layer 43, and the source and drain of the driving transistor T3 are arranged on the source-drain layer 46. In addition, the first electrode plate of the capacitor in the pixel driving circuit is arranged on the first gate layer 44, and the second electrode plate is arranged on the intermediate metal layer 45. It should be noted that the display area AA is provided with a shielding portion 401, which is arranged in the same layer as the first gate structure 221, and is arranged on the shielding metal layer 40. In the plane parallel to the substrate, the shielding portion 401 in this embodiment at least partially overlaps with the driving transistor T3, and the shielding portion 401 is connected to a preset potential with a fixed value, which is used to keep the potential of the driving transistor T3 stable when it is turned on and off, improve the accuracy of the output current of the pixel driving circuit, and thus improve the display effect of the display panel. In addition, because the pixel driving circuit requires fixed potentials such as the first power signal PVDD, the second power signal PVEE or the reference voltage signal VREF during operation, the present embodiment can multiplex any of the above signals into a preset potential without the need to add additional signal terminals, thereby reducing the complexity of the pixel driving circuit and effectively saving the operating energy consumption of the display panel.

[0071] Fig.11 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention. Fig.10 and Fig.11 Optionally, the display panel may include at least: a substrate 41; and a first active layer 43, a first gate layer 44, an intermediate metal layer 45, a second active layer 47, a second gate layer 48 and a source-drain layer 46 sequentially arranged on the substrate 41; the active layer 21 of the switching element T is located in the first active layer 43 and / or the second active layer 47; Fig.11 As shown, the first gate structure 221 of the switch element T is located at the first gate layer 44; the second gate structure 222 of the switch element T is located at the second gate layer 48; or Fig.10 As shown, the first gate structure 221 of the switch element T is located at the middle metal layer 45 ; the second gate structure of the switch element T is located at the second gate layer 48 .

[0072] Fig.11The specific film layers of the driving transistor T3 in the display area are also shown. Specifically, the gate of the driving transistor T3 is arranged on the first gate layer 44, the active layer of the driving transistor T3 is arranged on the first active layer 43, and the source and drain of the driving transistor T3 are arranged on the source-drain layer 46. Of course, the display area may also include other transistors, the gates of other transistors may be arranged on the second gate layer 48, the active layers are arranged on the second active layer 47, and the source and drain of the driving transistor T3 are arranged on the source-drain layer 46. If the first active layer 43 includes a low-temperature polysilicon material, and the second active layer 47 includes an oxide semiconductor (which may be indium gallium zinc oxide), then the display panel in this embodiment is an LTPO display panel. For the LTPO display panel, the active layer 22 of the switching element T may be arranged on the first active layer 43 or the second active layer 47. Optionally, the active layer 22 of some switching elements T in this embodiment is arranged on the first active layer 43, and the active layer 22 of some switching elements T is arranged on the second active layer 47. This embodiment is illustrated by taking the active layer 22 of the switch element T as an example in which it is arranged on the second active layer 47. When the active layer 22 of the switch element T is arranged on the second active layer 47, the second gate structure 222 of the switch element T of the dual-gate structure is located at the second gate layer 48, and the first gate structure 221 of the switch element T can be arranged on the first gate layer 44 or the intermediate metal layer 45. In this embodiment, the control signal is provided to the switch element T by the first gate structure 221 and the second gate structure 222 at the same time, so as to reduce the voltage drop of the control signal on the gate structure and improve the control accuracy of the switch element T.

[0073] In addition, in another example of the present embodiment, both the first active layer 43 and the second active layer 47 may include oxide semiconductors. Then the driving transistor T3 and the switching element T form a thin film transistor with a stacked arrangement. Optionally, in the first active layer 43 and the second active layer 47, the components of the oxide semiconductor are different, or the proportions of the components are different. For example, the first active layer 43 contains indium, gallium, zinc, tin and oxygen elements, while the second active layer 47 only contains indium, gallium, zinc and oxygen elements. For another example, the components in the first active layer 43 and the second active layer 47 both include indium, gallium, zinc, tin and oxygen elements, but the content ratio of gallium to indium in the second active layer 47 is higher than the content ratio of gallium to indium in the first active layer 43, and the content ratio of zinc to indium in the second active layer 47 is higher than the content ratio of zinc to indium in the first active layer 43. In this embodiment, the material composition or material ratio of the first active layer 43 and the second active layer 47 are adjusted differently so that the driving transistor T3 and the switching element T have different conduction properties.

[0074] Continue to refer Figure 2Optionally, the display area AA may include a plurality of columns of pixel driving circuits 31 extending along the second direction Y and arranged along the first direction X; each column of pixel driving circuits 31 is electrically connected to a data line 11. In this embodiment, the pixel driving circuits 31 are arranged in columns along the second direction Y, and each column of pixel driving circuits 31 is electrically connected to a data line 11, so this embodiment forms a single data signal line (DDL) layout. Figure 2 As shown, optionally, in the first display area AA1, a second auxiliary wiring 122 may be included between adjacent first data lines 111. Then along the first direction X, the number of first data lines 111 and the number of second auxiliary wiring 122 in the first display area AA1 are roughly the same, so that the number ratio of the first multiplexer 131 and the second multiplexer 132 tends to be 1:1, which is convenient for the first multiplexer 131 to connect to the first data line 111 nearby, and convenient for the second multiplexer 132 to connect to the second auxiliary wiring 122 nearby, reducing the setting length of the first connecting lead 161 and the second connecting lead 162, which is conducive to reducing the width of the fan-out area and realizing the narrow frame design of the lower frame of the display panel. In addition, the principle of nearby setting is conducive to the multiplexer 13 being closer to the first display area AA1, and the T angle area 17 is no longer provided with a multiplexer and a fan-out wiring, which is conducive to realizing the narrow frame design of the R angle area. It should be noted that in order to evenly arrange the auxiliary wirings 12 on the display panel and improve the display uniformity of the panel, a second auxiliary wiring 122 may be included between adjacent second data lines 112 in the second display area AA2 .

[0075] Fig.12 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention. Optionally, in the first display area AA1, two first data lines 111 may be included between adjacent second auxiliary wirings 122. For an LTPO display panel, the layout of two adjacent columns of pixel driving circuits 31 may be symmetrically arranged, such as Fig.12 As shown, in the first display area AA1, along the first direction X, there is a situation where no auxiliary wiring 12 and data line 11 are set between two adjacent columns of pixel driving circuits 31, and there is also a situation where two first data lines 111 are set between two adjacent columns of pixel driving circuits 31. In this case, if a second auxiliary wiring 122 is set corresponding to each column of pixel driving circuits 31, the second auxiliary wiring 122 can be respectively set outside the two first data lines 111, forming a structure in which two first data lines 111 can be included between adjacent second auxiliary wirings 122. Fig.12It can be seen that in the first display area AA1, the ratio of the number of the second auxiliary lines 122 to the first data lines 111 is 1:1, which facilitates the first multiplexer 131 to connect to the first data lines 111 nearby, and facilitates the second multiplexer 132 to connect to the second auxiliary lines 122 nearby, reducing the setting length of the first connection lead 161 and the second connection lead 162, which is conducive to reducing the width of the fan-out area and realizing the narrow frame design of the lower frame of the display panel. Similarly, in order to make the auxiliary lines 12 evenly arranged on the display panel, in the second display area AA2, two first data lines 111 can be included between adjacent second auxiliary lines 122.

[0076] Fig.13 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention. Optionally, when the layout of two adjacent columns of pixel driving circuits 31 can be symmetrically arranged, two second auxiliary wirings 122 can be included between adjacent first data lines 111 in the first display area AA1, and the first multiplexer 131 can be connected to the first data line 111 nearby, and the second multiplexer 132 can be connected to the second auxiliary wiring 122 nearby. In addition, two second auxiliary wirings 122 can be included between adjacent first data lines 111 in the second display area AA2.

[0077] Fig.14 A schematic diagram of the partial structure of another display panel provided by an embodiment of the present invention, optionally, when the layout of two adjacent columns of pixel driving circuits 31 can be symmetrically arranged, a second auxiliary wiring 122 can be included between adjacent first data lines 111 in the first display area AA1. Then the longitudinal wiring density along the second direction Y in the first display area AA1 is small, thereby reducing the signal interference between the parallel first data lines 111 and the second auxiliary wiring 122, and when the longitudinal wiring density is small, the process difficulty of the driving circuit layer is effectively reduced, and the yield rate of the display panel is improved. In addition, in the second display area AA2, a second auxiliary wiring 122 can be included between adjacent first data lines 111, so that the second auxiliary wiring 122 is evenly arranged on the entire display panel.

[0078] Fig.15 for Fig.12 The middle panel shows a partial enlarged schematic diagram of the S1 region. Fig.12 and Fig.15 Optionally, the display area may further include: sub-pixels arranged in an array ( Fig.14); the plurality of pixel driving circuit columns 31 include a first pixel driving circuit column 32 and a second pixel driving circuit column 33 which are alternately arranged; the first pixel driving circuit column 32 includes a first pixel driving circuit 311 and a second pixel driving circuit 312 which are alternately arranged along the second direction Y; the second pixel driving circuit column 33 includes a third pixel driving circuit 313; the first pixel driving circuit 311 is electrically connected to the first color sub-pixel; the second pixel driving circuit 312 is electrically connected to the second color sub-pixel; the third pixel driving circuit 313 is electrically connected to the third color sub-pixel; along the first direction X, the qth second auxiliary wiring 122 is electrically connected to the first pixel driving circuit column 32; the q+1th second auxiliary wiring 122 is electrically connected to the second pixel driving circuit column 33; 1≤q<N; q is a positive integer.

[0079] like Fig.15 As shown, the display panel includes a plurality of pixel driving circuits 31 arranged in an array, and different pixel driving circuits 31 drive sub-pixels (light-emitting elements) of different colors. Optionally, in this embodiment, the sub-pixels may include a first color sub-pixel capable of emitting a first color light, a second color sub-pixel capable of emitting a second color light, and a third color sub-pixel capable of emitting a third color light. Exemplarily, the first color sub-pixel may be a red sub-pixel, the second color sub-pixel may be a blue sub-pixel, and the third color sub-pixel may be a green sub-pixel. In this embodiment, the pixel driving circuit that drives the first color sub-pixel to emit light may be referred to as a first pixel driving circuit 311, the pixel driving circuit that drives the second color sub-pixel to emit light may be referred to as a second pixel driving circuit 312, and the pixel driving circuit that drives the third color sub-pixel to emit light may be referred to as a third pixel driving circuit 313. Along the first direction X, the first pixel driving circuit column 32 and the second pixel driving circuit column 33 are alternately arranged, wherein the first pixel driving circuit column 32 includes the first pixel driving circuit 311 and the second pixel driving circuit 312 alternately arranged along the second direction Y, and the second pixel driving circuit column 33 is only provided with the third pixel driving circuit 313. To facilitate understanding of the specific positions of different pixel driving circuits, this embodiment uses different filling patterns to represent the first pixel driving circuit 311, the second pixel driving circuit 312 and the third pixel driving circuit 313 respectively. Fig.12As shown, in the first display area AA1, along the first direction X, among the adjacent N second auxiliary wirings 122, the qth second auxiliary wiring 122 is electrically connected to the first pixel driving circuit column 32; the q+1th second auxiliary wiring 122 is electrically connected to the second pixel driving circuit column 33, that is, for every two adjacent second auxiliary wirings 122, there is a pixel driving circuit 31 connected to the first pixel driving circuit column 32, and the other pixel driving circuit 31 connected to the second pixel driving circuit column 33. Then, along the first direction X, the arrangement order of the second data lines 112 is the same as the arrangement order of the second auxiliary wirings 122 connected thereto, which facilitates the wiring of the second auxiliary wirings 122, avoids the situation where the auxiliary wirings 12 are intertwined with each other, and reduces the complexity of the auxiliary wirings 12. And the connection order of the switch elements T of all the multiplexers and the control signal lines can be kept the same. For example, as Figure 2 As shown, along the first direction X, the connection sequence between the switch element T of each multiplexer 13 and the control signal line is MUX1 and MUX2, which is convenient for wiring the gate of the switch element T.

[0080] Fig.16 A schematic diagram of the partial structure of another display panel provided in an embodiment of the present invention, optionally, the display area AA may also include a first power signal line VDD extending along the second direction Y and arranged along the first direction X; a first gap area S2 is included between adjacent first data lines 111; a second auxiliary wiring 122 and a first power signal line VDD are provided in the first gap area S2; and the second auxiliary wiring 122 and the first power signal line VDD are symmetrically arranged about the first gap area S2.

[0081] refer to Fig.16, for the case where each column of pixel driving circuits is electrically connected to a data line, if two adjacent columns of pixel driving circuits 31 of the display panel of this embodiment can be symmetrically arranged. Then two columns of pixel driving circuits are included between adjacent first data lines 111. This embodiment only shows part of the pixel driving circuits 31 to make the wiring relationship between the second auxiliary wiring 122 and the first power signal line VDD clearer, but in the actual structure, the pixel driving circuits 31 are arranged in an array on the display area AA, covering the entire display area AA. A first gap area S2 is included between adjacent first data lines 111, and a second auxiliary wiring 122 and a first power signal line VDD are arranged in the first gap area S2, and the second auxiliary wiring 122 and the first power signal line VDD are symmetrically arranged about the central axis φ extending along the second direction Y of the first gap area S2. The first power signal line VDD can reduce the capacitance between the second auxiliary wiring 122 and the first data line 111 to a certain extent, and can maintain the voltage on the second auxiliary wiring 122 and the first data line 111, thereby reducing the voltage drop (IR drop) between the second auxiliary wiring 122 and the first data line 111 as the length increases.

[0082] Fig.17 A schematic diagram of the partial structure of another display panel provided in an embodiment of the present invention, optionally, the data line may include a third data line 113 and a fourth data line 114; the display area AA includes a plurality of columns of pixel driving circuits 31 extending along the second direction Y and arranged along the first direction X; the pixel driving circuits 31 in odd rows of each column of pixel driving circuits 31 are electrically connected to the third data line 113; the pixel driving circuits 31 in even rows of each column of pixel driving circuits 31 are electrically connected to the fourth data line 114; the third data line 113 and the fourth data line 114 are respectively arranged on opposite sides of a column of pixel driving circuits 31.

[0083] In this embodiment, two data lines are correspondingly arranged for each column of pixel driving circuits 31: a third data line 113 and a fourth data line 114. In this embodiment, whether it is the first display area AA1 or the second display area AA2, the pixel driving circuit columns therein are all provided with the third data line 113 and the fourth data line 114, then the first data line 111 includes the third data line 113 and the fourth data line 114, and the second data line 112 includes the third data line 113 and the fourth data line 114. Along the second direction Y, the pixel driving circuits 31 of the odd rows of each column of pixel driving circuits 31 are connected to the third data line 113, and the pixel driving circuits 31 of the even rows of each column of pixel driving circuits 31 are connected to the fourth data line 114. In this embodiment, in order to reduce the cost, the double data signal line (DDL) technology is added to the display panel process, so as to realize the frequency conversion technology of the display panel at a lower cost. In addition, this embodiment can halve the number of data signals provided by the driver chip of the display panel through a 1:4 multiplexer, and further reduce the width of the R corner area and the bottom frame by combining the FIAA technology. In summary, this embodiment combines the DDL technology and the FIAA technology and applies them to the LTPO panel, further reducing the frame width of the display panel while achieving low-cost frequency conversion.

[0084] Continue to refer Fig.17 Optionally, in the first display area AA1, a second gap area S3 may be included between the third data line 113 and the fourth data line 114; a second auxiliary wiring 122 is disposed in the second gap area S3. In this embodiment, only one second auxiliary wiring 122 may be disposed between the third data line 113 and the fourth data line 114, and one second auxiliary wiring 122 is correspondingly inserted into each column of pixel driving circuits 31. In this embodiment, the arrangement density of the second auxiliary wiring 122 in the display area AA is relatively low, thereby reducing signal interference between the parallel first data lines 111 and the second auxiliary wiring 122.

[0085] Fig.18A schematic diagram of the partial structure of another display panel provided in an embodiment of the present invention, optionally, in the first display area AA1, a second auxiliary routing line 122 may be arranged between the adjacent third data line 113 and the fourth data line 114; in a direction perpendicular to the display panel, the second auxiliary routing line 122 at least partially overlaps with the third data line 113, or the second auxiliary routing line 122 at least partially overlaps with the fourth data line 114. In this embodiment, if the data line 11 and the second auxiliary routing line 122 are arranged in the same layer, the second auxiliary routing line 122 may be arranged in the second gap area S3 between the adjacent third data line 113 and the fourth data line 114. If the data line 11 and the second auxiliary routing line 122 are located in different film layers, the second auxiliary routing line 122 may overlap with the third data line 113 or the fourth data line 114 in a plane parallel to the substrate. Fig.18 The overlap between the second auxiliary wiring 122 and the third data line 113 is used as an example for illustration, and Fig.18 The figure shows the situation where the second auxiliary wiring 122 overlaps with the third data line 113. In this embodiment, an overlapping area is set between the second auxiliary wiring 122 and the data line 113 to save layout space parallel to the plane where the substrate is located, avoid the problem of too many longitudinal wirings extending along the second direction Y limiting the layout of the driving circuit layer, and reduce the complexity of the driving circuit layer.

[0086] Fig.19 A schematic diagram of the partial structure of another display panel provided in an embodiment of the present invention, optionally, in the first display area AA1, a second gap area S3 may be included between adjacent third data lines 113 and fourth data lines 114; two second auxiliary lines 122 are provided in the second gap area S3. In this embodiment, two second auxiliary lines 122 are provided in the second gap area S3 between the third data line 113 and the fourth data line 114, and two second auxiliary lines 122 are correspondingly inserted into each column of pixel driving circuits 31. In the first display area AA1, the number of second auxiliary lines 122 and first data lines is the same, then the number of first multiplexers 131 and second multiplexers 132 is the same, and they can be centrally arranged at the lower frame of the first display area AA1 to reduce the width of the R angle area. And the first multiplexer 131 is connected to the corresponding data line nearby, and the second multiplexer 132 is connected to the corresponding second auxiliary line 122 nearby, so as to reduce the space of the fan-out area and realize the narrow frame design of the lower side.

[0087] Fig. 20A schematic diagram of a partial structure of another display panel provided in an embodiment of the present invention, optionally, in the first display area AA1, two second auxiliary routing lines 122 may be provided between adjacent third data lines 113 and fourth data lines 114; in a direction perpendicular to the display panel, one second auxiliary routing line 122 at least partially overlaps with the third data line 113; another second auxiliary routing line 122 at least partially overlaps with the fourth data line 114. In this embodiment, when two second auxiliary routing lines 122 are inserted between adjacent third data lines 113 and fourth data lines 114, in a plane parallel to the substrate, one second auxiliary routing line 122 has an overlapping area with the third data line 113, and another second auxiliary routing line 122 has an overlapping area with the fourth data line 114. Optionally, as Fig. 20 As shown, the third data line 113 overlaps with one second auxiliary wiring 122, and the fourth data line 114 overlaps with another second auxiliary wiring 122. This embodiment can save the layout space of the display panel parallel to the plane where the substrate is located, avoid the problem that the layout of the driving circuit layer is limited due to the large number of longitudinal wirings extending along the second direction Y, and reduce the complexity of the driving circuit layer. It should be noted that because Fig. 20 The second auxiliary wiring 122 substantially coincides with the data line. It should be emphasized in this embodiment that the first auxiliary wiring 121 is electrically connected to the third data line 113 or the fourth data line 114 in the second display area AA2, and the first auxiliary wiring 121 is electrically connected to the second auxiliary wiring 122 in the first display area AA1.

[0088] Continue to refer Fig.19 Optionally, the display area may further include: sub-pixels arranged in an array ( Fig.19 31); the plurality of pixel driving circuits 31 include a first pixel driving circuit column 32 and a second pixel driving circuit column 33 which are alternately arranged; the first pixel driving circuit column 32 includes a first pixel driving circuit 311 and a second pixel driving circuit 312 which are alternately arranged along the second direction Y; the second pixel driving circuit column 33 includes a third pixel driving circuit 313; the first pixel driving circuit 311 is electrically connected to the first color sub-pixel; the second pixel driving circuit 312 is electrically connected to the second color sub-pixel; the third pixel driving circuit 313 is electrically connected to the third color sub-pixel; along the first color sub-pixel In a direction X, the hth second auxiliary routing 122 is electrically connected to the first pixel driving circuit 311 of the first pixel driving circuit column 32; the h+1th second auxiliary routing 122 is electrically connected to the second pixel driving circuit 312 of the first pixel driving circuit column 32; the h+2th second auxiliary routing 122 is electrically connected to the third pixel driving circuit 313 of the odd row of the second pixel driving circuit column 33; the h+3th second auxiliary routing 122 is electrically connected to the third pixel driving circuit 313 of the even row of the second pixel driving circuit column 33; 1≤h≤N-3; h is a positive integer.

[0089] like Fig.19 As shown, the display panel includes a plurality of pixel driving circuits 31 arranged in an array, and different pixel driving circuits 31 drive sub-pixels (light-emitting elements) of different colors. Optionally, the sub-pixels in this embodiment may include first color sub-pixels, second color sub-pixels, and third color sub-pixels. Exemplarily, the first color sub-pixel may be a red sub-pixel, the second color sub-pixel may be a blue sub-pixel, and the third color sub-pixel may be a green sub-pixel. In this embodiment, the pixel driving circuit that drives the first color sub-pixel to emit light may be referred to as a first pixel driving circuit 311, the pixel driving circuit that drives the second color sub-pixel to emit light may be referred to as a second pixel driving circuit 312, and the pixel driving circuit that drives the third color sub-pixel to emit light may be referred to as a third pixel driving circuit 313. Along the first direction X, the first pixel driving circuit column 32 and the second pixel driving circuit column 33 are alternately arranged, wherein the first pixel driving circuit column 32 includes the first pixel driving circuit 311 and the second pixel driving circuit 312 alternately arranged along the second direction Y. For example, the first pixel driving circuit 311 can be arranged in odd rows, the second pixel driving circuit 312 can be arranged in even rows, and the second pixel driving circuit column 33 is only provided with the third pixel driving circuit 313. To facilitate understanding of the specific positions of different pixel driving circuits, this embodiment uses different filling patterns to represent the first pixel driving circuit 311, the second pixel driving circuit 312 and the third pixel driving circuit 313 respectively. Fig.19 As shown, in the first display area AA1, along the first direction X, among the adjacent N second auxiliary wirings 122, the hth second auxiliary wiring 122 is electrically connected to the first pixel driving circuit 311 of the first pixel driving circuit column 32; the h+1th second auxiliary wiring 122 is electrically connected to the second pixel driving circuit 312 of the first pixel driving circuit column 32, the h+2th second auxiliary wiring 122 is electrically connected to the third pixel driving circuit 313 of the odd-numbered rows of the second pixel driving circuit column 33, and the h+3th second auxiliary wiring 122 is electrically connected to the third pixel driving circuit 313 of the even-numbered rows of the second pixel driving circuit column 33. That is, for every four adjacent second auxiliary wirings 122, there is one connected to the first pixel driving circuit 311, one connected to the second pixel driving circuit 312, and the remaining two connected to the third pixel driving circuit 313. Then, along the first direction X, the arrangement order of the second data line 112 is the same as the arrangement order of the second auxiliary wiring 122 connected thereto, which facilitates the wiring of the second auxiliary wiring 122, avoids the situation where the auxiliary wirings 12 are intertwined, and reduces the complexity of the auxiliary wiring 12. In this embodiment, two data lines are used to charge a column of pixel driving circuits, so one data line only needs to charge half of the pixel driving circuits in a column of pixel driving circuits, thereby improving the charging effect of the pixel driving circuits and improving the display effect of the entire display panel. Optionally, you can continue to refer to Fig.19In the display area, the third data line 113 and the second auxiliary wiring 122 connected to the output ends of the switches respectively controlled by mux4 in the first multiplexer 131 and the second multiplexer 132 can be set adjacent to each other, so that the switches corresponding to the adjacent signal lines can be turned on at the same time, reducing the coupling jump between the adjacent signal lines. Optionally, the color of the light-emitting element corresponding to the pixel driving circuit electrically connected to the third data line 113 can also be set to be the same as the color of the light-emitting element corresponding to the pixel driving circuit electrically connected to the second auxiliary wiring 122, reducing the signal crosstalk between the adjacent wirings.

[0090] In addition, in this embodiment, the effective frequency conversion technology is realized by controlling the connection relationship between the multiplexer and the control signal line. Fig.21 The timing diagram of the control signal line provided by the embodiment of the present invention. The control signal line includes a first control signal line MUX1, a second control signal line MUX2, a third control signal line MUX3 and a fourth control signal line MUX4. When the switch element of the multiplexer is driven, the first control signal line MUX1, the second control signal line MUX2, the third control signal line MUX3 and the fourth control signal line MUX4 output valid pulses in sequence. For example, Fig.19 As shown, the first control signal line MUX1 can control the fan-out wiring 16 to transmit a signal to the first pixel driving circuit 311, the third control signal line MUX3 can control the fan-out wiring 16 to transmit a signal to the second pixel driving circuit 312, and the second control signal line MUX2 and the fourth control signal line MUX4 both transmit a signal to the third pixel driving circuit 313. This embodiment achieves effective frequency conversion by adjusting the driving sequence of different types of pixel driving circuits.

[0091] In a specific example, if Fig. 22 As shown, Fig. 22 A schematic diagram of the partial structure of another display panel provided by an embodiment of the present invention, wherein the first control signal line MUX1 can control the fan-out line 16 to transmit a signal to the first pixel driving circuit 311, the fourth control signal line MUX4 can control the fan-out line 16 to transmit a signal to the second pixel driving circuit 312, and the second control signal line MUX2 and the third control signal line MUX3 both transmit a signal to the third pixel driving circuit 313. If the display panel currently displays the third color, during the control period of the second control signal line MUX2 and the third control signal line MUX3, the frequency of the high-low flipping of the voltage output on the driver chip is reduced by half, which effectively reduces the power consumption of the driver chip and improves the battery life of the display panel.

[0092] Continue to refer Fig.18, Optionally, along the first direction X from the second display area AA2 to the first display area AA1, the tth first data line 111 is electrically connected to the jth second auxiliary wiring 122; the t+1th first data line 111 is electrically connected to the j+1th second auxiliary wiring 122; wherein, 1≤t<M; 1≤j≤M; M is the number of second data lines 112 of the second display area AA2 on one side of the first display area AA1; t, j and M are all positive integers. Along the first direction X from the second display area AA2 to the first display area AA1, the second data lines 112 on the second display area AA2 are sequentially connected to the nearest second auxiliary wiring 122, and the setting length of the first auxiliary wiring 121 required for each second data line 112 to connect to the second auxiliary wiring 122 tends to be the same. Then, the difference in resistance value of the signal transmission path of each data line is small, and it is not easy to have a situation where the signal transmission path loss of a certain data line is large and the display screen is uneven, thereby improving the display effect of the display panel.

[0093] Continue to refer Fig. 22 Optionally, the second display area AA2 may include a plurality of data line groups 115; the data line group 115 includes W second data lines 112 adjacently arranged along the first direction X; W is an integer greater than 1; in the direction from the second display area AA2 to the first display area AA1 along the first direction X, the fth second data line 112 in the same data line group 115 is electrically connected to the kth second auxiliary wiring 122; the f+1th second data line 112 is electrically connected to the k+1th second auxiliary wiring 122; wherein 1≤f<W; 1≤k≤M; f, k and M are all positive integers; M is the number of second data lines 112 in the second display area AA2 on one side of the first display area AA1. In this embodiment, the second data lines 112 may be divided into a plurality of data line groups 115 in the direction from the second display area AA2 to the first display area AA1 along the first direction X, and each data line group 115 includes the same number of second data lines 112. And in the direction from the second display area AA2 to the first display area AA1, the fth second data line 112 is connected to the kth second auxiliary wiring 122 in the first display area AA1, and the f+1th second data line 112 is connected to the k+1th second auxiliary wiring 122. Fig.18 In this embodiment, the first auxiliary wiring 121 is arranged irregularly. The design of irregular auxiliary wiring can reduce the uneven display of the display panel, reduce the generation of mura, and improve the picture display effect of the display panel.

[0094] Continue to refer Fig. 22Optionally, the non-display area may include a first fan-out area S4; the first fan-out area S4 is arranged on a side of the multiplexer 13 close to the display area; the first fan-out area S4 includes a plurality of first connecting leads 161 and a plurality of second connecting leads 162; the second auxiliary wiring 122 is connected to the second connecting lead 162; the first connecting lead 161 is used to connect the first data line 111 and the first multiplexer 131; the second connecting lead 162 is used to connect the second auxiliary wiring 122 and the second multiplexer 132. As can be seen from the above, the fan-out area includes connecting leads, multiplexers, fan-out wiring, etc. In this embodiment, it can be set that the non-display area may include the first fan-out area S4. The first fan-out area S4 is located between the display area and the multiplexer 13. The first fan-out area S4 includes a first connection lead 161 and a second connection lead 162. The first connection lead 161 transmits the output signal of the first demultiplexer 131 to the first data line 111, and the second connection lead 162 transmits the output signal of the second demultiplexer 132 to the second auxiliary wiring 122. In this embodiment, the demultiplexer 13 is electrically connected to the corresponding first data line 111 or the second auxiliary wiring 122 according to the principle of nearest connection, which effectively reduces the width of the first fan-out area S4 along the second direction Y, and realizes the narrow frame design of the display panel.

[0095] Fig.23 A schematic diagram of a film structure of a display panel provided by an embodiment of the present invention. Fig. 22 and Fig.23 Optionally, the non-display area may include a multiplexer area 14; the multiplexer area 14 is provided with a multiplexer 13; the second multiplexer 132 is arranged on the side of the first multiplexer 131 close to the display area; along the first direction X, a second power bus BUS2 is arranged on one side of the multiplexer area 14; the length L2 of the second power bus BUS2 along the second direction Y is greater than the length L1 of the multiplexer area 14 along the second direction Y; the side of the multiplexer area 14 away from the display area includes the first power bus BUS1.

[0096] like Fig.23 As shown, a demultiplexer region 14 is provided in a non-display area near the first display area. Along the first direction X, a second power bus BUS2 may be provided on one or both sides of the demultiplexer region 14, and the second power bus BUS2 may be used to provide a second power signal PVEE for the pixel driving circuit. Fig.23As shown, the longitudinal length L2 of the second power bus BUS2 along the second direction Y is greater than the longitudinal length L1 of the demultiplexer area 14 along the second direction Y. In this embodiment, the space occupied by the non-display area is reduced by setting the demultiplexer 13, especially the space in the R corner area. Then, the second power bus BUS2 with a larger size is set in the space freed in the non-display area to reduce the loss of the second power signal PVEE during the transmission process, and the first power bus BUS1 is set on the side of the demultiplexer area 14 away from the display area to provide accurate driving current for the pixel driving circuit and improve the display effect of the display panel.

[0097] refer to Fig. 9 and Fig.23 Optionally, the display panel may include a substrate 41 and a driving circuit layer on the substrate 41; the driving circuit layer is provided with a plurality of pixel driving circuits; the driving circuit layer includes a first active layer 43, a first gate layer 44, a source-drain layer 46, a third metal layer 49 and a fourth metal layer 50 which are sequentially away from the substrate 41; the auxiliary wiring 12 and the data line 11 are arranged in different metal layers; the first power bus BUS1 includes a first bus portion 51 of the fourth metal layer 50; the first bus portion 51 extends to the multiplexer area 14; the second power bus BUS2 includes a first branch portion 52 of the source-drain layer 46, a second branch portion 53 of the third metal layer 49 and a third branch portion 54 of the fourth metal layer 50.

[0098] In this embodiment, the display panel may be an LTPO panel or an LTPS panel. Fig. 9 Take the LTPS panel as an example. The driving circuit layer of the display panel includes a first active layer 43, a first gate layer 44, a source-drain layer 46, a third metal layer 49 and a fourth metal layer 50, which are sequentially arranged away from the substrate 11. Optionally, an intermediate metal layer 45 may be arranged between the first gate layer 44 and the source-drain layer 46. Optionally, when the display panel is an LTPO panel, the intermediate metal layer 45 and the source-drain layer 46 are further provided with a second active layer and a second gate layer. The auxiliary wiring 12 and the data line 11 may be arranged in different metal layers, for example, Fig. 9 As shown, optionally, the data line 11 can be arranged on the third metal layer 49; the second auxiliary wiring 122 can be arranged on the fourth metal layer 50; and the first auxiliary wiring 121 can be arranged on the source and drain layer 46. Fig. 9 and Fig.23 As shown, the first power bus BUS1 includes a first bus portion 51 of the fourth metal layer 50, and the first bus portion 51 extends to the demultiplexer area 14, which increases the width of the first power bus BUS1 and reduces the loss of the first power signal, while reusing the space of the demultiplexer area 14, without affecting the narrow frame design of the display panel. It should be noted that Fig.23The first gate layer and the first active layer are not shown in the figure to show the structure of the first bus portion 51, but the actual panel structure includes the first gate layer and the first active layer. The second power bus BUS2 includes a multi-layer stacking structure to further reduce the resistance of the second power bus BUS2. Specifically, Fig. 9 As shown, the second power bus BUS2 includes a first branch portion 52 of the source-drain layer 46, a second branch portion 53 of the third metal layer 49 and a third branch portion 54 of the fourth metal layer 50, and adjacent ones of the first branch portion 52, the second branch portion 53 and the third branch portion 54 are electrically connected by punching.

[0099] Fig.24 A schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention. Fig.10 and Fig.24 Optionally, the multiplexer area may include a first multiplexer area 141 and a second multiplexer area 142; the first multiplexer area 141 is used to set the first multiplexer 131; the second multiplexer area 142 is used to set the second multiplexer 132; the display panel includes a substrate 11 and a driving circuit layer on the substrate 11; the driving circuit layer is provided with a plurality of pixel driving circuits; the driving circuit layer includes a first active layer 43, a first gate layer 44, a source and drain layer 46 and a third metal layer 49 which are sequentially away from the substrate 11; the second auxiliary wiring 122 and the data line 11 are arranged in the third metal layer 49; the first power bus BUS1 includes a second bus portion 55 of the third metal layer 49; the second bus portion 55 extends to the first multiplexer area 141; the second power bus BUS2 includes a first branch portion 52 of the source and drain layer 46 and a second branch portion 53 of the third metal layer 49.

[0100] In this embodiment, the display panel may be an LTPO panel or an LTPS panel. Fig.10 Take the LTPS panel as an example. The driving circuit layer of the display panel includes a first active layer 43, a first gate layer 44, a source-drain electrode layer 46, and a third metal layer 49, which are sequentially arranged away from the substrate 11. Optionally, an intermediate metal layer 45 may be arranged between the first gate layer 44 and the source-drain electrode layer 46. Optionally, when the display panel is an LTPO panel, the intermediate metal layer 45 and the source-drain electrode layer 46 are further provided with a second active layer 47 and a second gate layer 48. Fig.10As shown, the fourth metal layer is not provided in this embodiment, so the second auxiliary wiring 122 and the data line 11 can be provided in the same layer and provided in the third metal layer 49. The first auxiliary wiring can be provided in other metal layers such as the source and drain layer and the second gate layer. The specific film layer of the first auxiliary wiring is not particularly limited in this embodiment. In addition, the first power bus BUS1 does not provide the first bus portion 51, but provides the second bus portion 55 in the third metal layer 49. The second bus portion 55 covers part of the multiplexer area, while increasing the width of the first power bus BUS1 and reducing the loss of the first power signal, the space of the multiplexer area 14 is reused, and the narrow frame design of the display panel is not affected.

[0101] It should be noted that, because the first data line also needs to pass through the first connecting lead 161 of the third metal layer 49 to connect to the first demultiplexer 131, and the first connecting lead 161 needs to cross the second demultiplexer region 142 where the second demultiplexer 132 is located, in a plane parallel to the substrate, the second bus portion 55 only covers the first demultiplexer region 141 where the second demultiplexer 132 is located, but does not cover the second demultiplexer region 142. In addition, Fig.10 As shown, the second power bus BUS2 includes a multi-layer stacked structure, which only includes the first branch portion 52 of the source and drain layer 46 and the second branch portion 53 of the third metal layer 49 to increase the width of the second power bus BUS2 and reduce the loss of the second power signal.

[0102] Continue to refer Fig.24 Optionally, the non-display area may include a multiplexer area 14; the multiplexer area 14 is provided with a multiplexer; along the first direction X, the distance d1 between the edge of the multiplexer area 14 and the starting position of the first data line 111 is less than a preset distance D; or, along the first direction X, the edge of the multiplexer area 14 is aligned with the starting position of the second auxiliary routing line 122.

[0103] In this embodiment, along the first direction X, the edge of the demultiplexer area 14 can be aligned with the starting position of the second auxiliary trace 122, that is, the demultiplexer area 14 is only provided in the frame area below the first display area AA1, saving the frame area below the second display area AA2 for the layout of other signal lines or further reducing the width of the frame area below the second display area AA2, thereby realizing a narrow frame design of the display panel. Or, as Fig.24As shown, along the first direction X, the distance d1 between the edge of the multiplexer area 14 and the starting position of the first data line 111 is less than the preset distance D. Optionally, the value of the preset distance D can be 1 to 2 times the size of the pixel driving circuit along the first direction X. In this embodiment, the edge of the multiplexer area 14 and the starting position of the first data line 111 tend to be in the same position, so the multiplexer 13 and the fan-out wiring are not set in the R corner area of ​​the display panel and the frame area below the second display area AA2, further reducing the frame width and improving the user experience. In addition, because the second auxiliary wiring 122 connecting the multiplexer 13 and the first data line 111 are both set in the first display area AA1, this embodiment sets the multiplexer area 14 close to the first display area AA1, which can further reduce the setting length of the first connecting lead 161, the second connecting lead and the fan-out wiring, reduce the resistance value of each transmission path, and reduce the signal transmission loss. In addition, the lengths of the first connecting lead 161, the second connecting lead and the fan-out routing can be set as short as possible to further reduce the overall space occupied by the fan-out area and reduce the width of the lower frame of the entire display panel. It should be noted that the lower frame in this embodiment is a non-display area where the fan-out area is set.

[0104] An embodiment of the present invention further provides a display device. Fig.25 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.25 As shown, the display device provided by the embodiment of the present invention includes the display panel 200 provided by any embodiment of the present invention. The display device can be as follows Fig.25 The display device of the mobile phone shown in the figure may also be a display device of an electronic device such as a computer, a television, a smart wearable device, etc., and this embodiment does not specifically limit this.

[0105] The display device in this embodiment includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding technical features, which will not be described in detail here.

[0106] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: a display area and a non-display area at least partially surrounding the display area; The display area includes a first display area and a second display area; the second display area is located at least on one side of the first display area along a first direction; the display area includes a plurality of data lines arranged along the first direction and extending along the second direction; the first direction and the second direction intersect; the data lines include a first data line and a second data line; the first data line is arranged in the first display area; the second data line is arranged in the second display area; the display area includes a plurality of auxiliary wirings; The non-display area includes a plurality of demultiplexers; the auxiliary wiring transmits the signal output by the demultiplexer to the second data line; Each of the demultiplexers comprises N switch elements; a first end of the switch element of the same demultiplexer is electrically connected to an input end of the demultiplexer; The multiplexer includes a first multiplexer and a second multiplexer; N first data lines are electrically connected one-to-one with the second ends of N switching elements in the same first multiplexer; N auxiliary lines are electrically connected one-to-one with the second ends of N switching elements in the same second multiplexer; N is an integer greater than 1; wherein the ratio of the number of the first multiplexers to the number of the second multiplexers is in the range of 0.8 to 1.

5.

2. The display panel according to claim 1, characterized in that: Along the first direction, adjacent N first data lines are electrically connected to the second ends of N switch elements in the same first demultiplexer in a one-to-one correspondence; Along the first direction, adjacent N auxiliary wirings are electrically connected to the second ends of the N switch elements in the same second demultiplexer in a one-to-one correspondence.

3. The display panel according to claim 1, characterized in that: The ratio of the number of the first demultiplexers to the number of the second demultiplexers is in a range of 1 to 1.

25.

4. The display panel according to claim 1, characterized in that: The auxiliary routing includes a first auxiliary routing extending along a first direction and a second auxiliary routing extending along a second direction; the first auxiliary routing is used to connect the corresponding second data line and the second auxiliary routing; the second auxiliary routing is electrically connected to the second end of the switching element in the second multiplexer.

5. The display panel according to claim 4, characterized in that: The non-display area includes a demultiplexer area; the demultiplexer area is provided with the demultiplexer; Along the first direction, the distance between the edge of the demultiplexer area and the starting position of the first data line is less than a preset distance; or, Along the first direction, an edge of the demultiplexer region is aligned with a starting position of the second auxiliary trace.

6. The display panel according to claim 4, characterized in that: In the first display area, a virtual extension line of the second auxiliary wiring along the second direction and the second multiplexer connected thereto have an overlapping area.

7. The display panel according to claim 1, characterized in that: The non-display area includes a demultiplexer area; the demultiplexer area is provided with the demultiplexer; A virtual extension line of the second data line along the second direction does not overlap with the demultiplexer area.

8. The display panel according to claim 1, characterized in that: The first demultiplexer comprises N first switch elements arranged in sequence along the first direction; the second demultiplexer comprises N second switch elements arranged in sequence along the first direction; the switch elements comprise active layers; The active layer of the switch element of the first demultiplexer is located on a side of the active layer of the switch element of the second demultiplexer away from the display area; Along the first direction, the i-th first switch element of the first demultiplexer and the i-th second switch element of the second demultiplexer share a gate; 1≤i≤N; i is a positive integer.

9. The display panel according to claim 1, characterized in that: The multiplexer comprises a first element group and a second element group; the first element group and the second element group each comprise a plurality of switch elements sequentially arranged along the first direction; the switch element comprises an active layer; The active layer of the switch element of the second element group is located on a side of the active layer of the switch element of the first element group away from the display area; Along the first direction, the p-th switch element of the first element group and the e-th switch element of the second element group share the first end; 1≤p≤N; 1≤e≤N; p and e are positive integers.

10. The display panel according to claim 9, characterized in that: Along the first direction, the first demultiplexers and the second demultiplexers are alternately arranged.

11. The display panel according to claim 1, characterized in that: The switch element comprises a dual-gate structure; The dual-gate structure includes a first gate structure and a second gate structure; the first gate structure and the second gate structure are arranged in different film layers.

12. The display panel according to claim 11, characterized in that: The display panel at least comprises: a substrate; A shielding metal layer, located on the substrate; the shielding metal layer includes a first gate structure of the switch element; A first active layer, located on a side of the shielding metal layer away from the substrate; the first active layer includes an active layer of the switch element; A first gate layer is disposed on a side of the first active layer away from the substrate; the first gate layer includes a second gate structure of the switch element; An intermediate metal layer, disposed on a side of the first gate layer away from the substrate; The source-drain electrode layer is arranged on a side of the intermediate metal layer away from the substrate; the source-drain electrode layer includes a first end and a second end of the switch element.

13. The display panel according to claim 12, characterized in that: The shielding metal layer also includes a shielding portion of the display area; The shielding portion at least partially overlaps with the driving transistor of the display area; the shielding portion is connected to a preset potential; the preset potential is a first power signal, a second power signal or a reference voltage signal.

14. The display panel according to claim 11, characterized in that: The display panel at least comprises: a substrate; and a first active layer, a first gate layer, an intermediate metal layer, a second active layer, a second gate layer and a source-drain electrode layer sequentially arranged on the substrate; The active layer of the switching element is located in the first active layer and / or the second active layer; The first gate structure of the switch element is located at the first gate layer; the second gate structure of the switch element is located at the second gate layer; or, The first gate structure of the switch element is located at the middle metal layer; the second gate structure of the switch element is located at the second gate layer.

15. The display panel according to claim 1, characterized in that: The non-display area further comprises: a binding area; the binding area is located at a side of the demultiplexer away from the display area; The input end of the demultiplexer is electrically connected to the corresponding binding terminal of the binding area; The non-display area further comprises N switch control lines; the control ends of the N switch elements of the same multiplexer are electrically connected to the switch control lines in a one-to-one correspondence.

16. The display panel according to claim 4, characterized in that: The display area includes a plurality of columns of pixel driving circuits extending along the second direction and arranged along the first direction; each column of pixel driving circuits is electrically connected to a data line.

17. The display panel according to claim 16, characterized in that: In the first display area, one second auxiliary wiring is included between adjacent first data lines.

18. The display panel according to claim 16, characterized in that: In the first display area, two first data lines are included between adjacent second auxiliary wirings.

19. The display panel according to claim 16, characterized in that: The display area also includes: sub-pixels arranged in an array; The plurality of pixel driving circuit columns include a first pixel driving circuit column and a second pixel driving circuit column that are alternately arranged; the first pixel driving circuit column includes a first pixel driving circuit and a second pixel driving circuit that are alternately arranged along a second direction; the second pixel driving circuit column includes a third pixel driving circuit; the first pixel driving circuit is electrically connected to a first color sub-pixel; the second pixel driving circuit is electrically connected to a second color sub-pixel; the third pixel driving circuit is electrically connected to a third color sub-pixel; Along the first direction, the qth second auxiliary wiring is electrically connected to the first pixel driving circuit column; the q+1th second auxiliary wiring is electrically connected to the second pixel driving circuit column; 1≤q<N; q is a positive integer.

20. The display panel according to claim 16, characterized in that: The display area further includes a first power signal line extending along the second direction and arranged along the first direction; A first gap region is included between adjacent first data lines; one second auxiliary wiring and one first power signal line are disposed in the first gap region; and the second auxiliary wiring and the first power signal line are symmetrically disposed about the first gap region.

21. The display panel according to claim 4, characterized in that: The data lines include a third data line and a fourth data line; The display area includes a plurality of columns of pixel driving circuits extending along the second direction and arranged along the first direction; the pixel driving circuits in odd rows of each column of pixel driving circuits are electrically connected to the third data line; the pixel driving circuits in even rows of each column of the pixel driving circuits are electrically connected to the fourth data line; the third data line and the fourth data line are respectively arranged on opposite sides of a column of pixel driving circuits.

22. The display panel according to claim 21, characterized in that: In the first display area, a second gap area is included between the third data line and the fourth data line; and a second auxiliary wiring is disposed in the second gap area.

23. The display panel according to claim 21, characterized in that: In the first display area, a second auxiliary wiring is arranged between the third data line and the fourth data line; In a direction perpendicular to the display panel, the second auxiliary routing line at least partially overlaps with the third data line, or the second auxiliary routing line at least partially overlaps with the fourth data line.

24. The display panel according to claim 21, characterized in that: In the first display area, a second gap area is included between the adjacent third data line and the fourth data line; and two second auxiliary wirings are disposed in the second gap area.

25. The display panel according to claim 21, characterized in that: In the first display area, two second auxiliary wirings are arranged between the adjacent third data line and the fourth data line; In a direction perpendicular to the display panel, one of the second auxiliary routing lines at least partially overlaps with the third data line; another of the second auxiliary routing lines at least partially overlaps with the fourth data line.

26. The display panel according to claim 21, characterized in that: The display area also includes: sub-pixels arranged in an array; The plurality of pixel driving circuit columns include a first pixel driving circuit column and a second pixel driving circuit column that are alternately arranged; the first pixel driving circuit column includes a first pixel driving circuit and a second pixel driving circuit that are alternately arranged along a second direction; the second pixel driving circuit column includes a third pixel driving circuit; the first pixel driving circuit is electrically connected to a first color sub-pixel; the second pixel driving circuit is electrically connected to a second color sub-pixel; the third pixel driving circuit is electrically connected to a third color sub-pixel; Along the first direction, the hth second auxiliary routing is electrically connected to the first pixel driving circuit of the first pixel driving circuit column; the h+1th second auxiliary routing is electrically connected to the second pixel driving circuit of the first pixel driving circuit column; the h+2th second auxiliary routing is electrically connected to the third pixel driving circuit of the odd row of the second pixel driving circuit column; the h+3th second auxiliary routing is electrically connected to the third pixel driving circuit of the even row of the second pixel driving circuit column; 1≤h≤N-3; h is a positive integer.

27. The display panel according to claim 4, characterized in that: Along the first direction from the second display area to the first display area, the tth first data line is electrically connected to the jth second auxiliary wiring; the t+1th first data line is electrically connected to the j+1th second auxiliary wiring; wherein, 1≤t<M; 1≤j≤M; M is the number of second data lines in the second display area on one side of the first display area; t, j and M are all positive integers.

28. The display panel according to claim 4, characterized in that: The second display area includes a plurality of data line groups; the data line groups include W second data lines adjacently arranged along the first direction; W is an integer greater than 1; Along the first direction from the second display area to the first display area, the fth second data line in the same data line group is electrically connected to the kth second auxiliary wiring; the f+1th second data line is electrically connected to the k+1th second auxiliary wiring; wherein, 1≤f<W; 1≤k≤M; f, k and M are all positive integers; M is the number of second data lines in the second display area on one side of the first display area.

29. The display panel according to claim 4, characterized in that: The non-display area includes a first fan-out area; the first fan-out area is arranged on a side of the multiplexer close to the display area; the first fan-out area includes a plurality of first connecting leads and a plurality of second connecting leads; the second auxiliary wiring is connected to the second connecting leads; The first connecting lead is used to connect the first data line and the first demultiplexer; the second connecting lead is used to connect the second auxiliary line and the second demultiplexer.

30. The display panel according to claim 4, characterized in that: The non-display area includes a demultiplexer area; the demultiplexer area is provided with the demultiplexer; the second demultiplexer is provided on a side of the first demultiplexer close to the display area; A second power bus is provided on one side of the demultiplexer region along the first direction; a length of the second power bus along the second direction is greater than a length of the demultiplexer region along the second direction; A side of the demultiplexer region away from the display area includes a first power bus.

31. The display panel according to claim 30, characterized in that: The display panel comprises a substrate and a driving circuit layer on the substrate; the driving circuit layer is provided with a plurality of pixel driving circuits; The driving circuit layer includes a first active layer, a first gate layer, a source-drain layer, a third metal layer and a fourth metal layer which are sequentially away from the substrate; The auxiliary wiring and the data line are arranged in different metal layers; The first power bus includes a first bus portion of the fourth metal layer; the first bus portion extends to the demultiplexer region; The second power bus includes a first branch portion of the source-drain layer, a second branch portion of the third metal layer, and a third branch portion of the fourth metal layer.

32. The display panel according to claim 31, characterized in that: The data line is arranged on the third metal layer; the second auxiliary wiring is arranged on the fourth metal layer; and the first auxiliary wiring is arranged on the source and drain electrode layer.

33. The display panel according to claim 30, characterized in that: The demultiplexer area includes a first demultiplexer area and a second demultiplexer area; the first demultiplexer area is used to set the first demultiplexer; the second demultiplexer area is used to set the second demultiplexer; The display panel comprises a substrate and a driving circuit layer on the substrate; the driving circuit layer is provided with a plurality of pixel driving circuits; the driving circuit layer comprises a first active layer, a first gate layer, a source-drain electrode layer and a third metal layer which are sequentially away from the substrate; The second auxiliary wiring and the data line are arranged in the third metal layer; the first power bus includes a second bus portion of the third metal layer; the second bus portion extending to the first demultiplexer region; The second power bus includes a first branch portion of the source-drain layer and a second branch portion of the third metal layer.

34. A display device, characterized in that: A display panel comprising any one of claims 1 to 33.

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