Cache management method, cache management device and electronic equipment

Abstract

The invention provides a cache management method, a cache management device and electronic equipment. The method comprises the following steps: receiving a data access request; in response to the fact that first data corresponding to the data access request is stored in the cache, increasing the activeness of the first data, and adjusting the priority of the first data based on the increased activeness of the first data; and in response to the fact that the first data is not stored in the cache and the cache is full, deleting second data in the data with the lowest priority in the cache, loading the first data into the cache, and setting the priority and the activeness of the first data. According to the method, the activeness and the priority of the data in the cache can be managed, so that the data with high access frequency and the new data are stored in the cache, and the cache hit rate and the data access efficiency are improved.

Description

Technical Field

[0001] The present disclosure generally relates to the field of data processing technology, and more specifically, to a cache management method, a cache management device, and an electronic device. Background Art

[0002] Currently, commonly used cache replacement strategies include LFU (Least Frequently Used) and LRU (Least Recently Used).

[0003] The LFU algorithm replaces the data with the smallest number of accesses each time, counts the frequency of cache usage, sorts the data from small to large according to frequency, replaces the data with relatively low frequency of use first, and stores the frequently used data in the cache. Figure 1 is a diagram showing an example of LFU algorithm data access, referring to Figure 1 , the data in the cache are arranged from small to large according to the frequency of use. When accessing data B, first check whether data B is in the cache. Figure 1 As shown, if data B is in the cache, then data B is directly accessed and the usage frequency of data B is increased by 1. When accessing data D, determine whether data D is in the cache. At this time, if data D is in the cache, the usage frequency of data D is increased by 1, and the data in the cache are reordered according to the usage frequency. If the usage frequency of data D is greater than the usage frequency of data C, the order of data D and data C is swapped. When accessing data F, if data F is not in the cache, remove the data E with the lowest usage frequency in the existing cache from the cache, then store data F in the cache, and change the usage frequency of data F to 1.

[0004] Figure 2 is a diagram showing the data structure of the LRU algorithm, refer to Figure 2 The LRU algorithm replaces the data that has not been accessed for the longest time each time and inserts the new data directly into the cache queue. If the cache queue is full, the data at the end of the queue is deleted and the new data is inserted into the head of the queue. If the new data is in the cache queue, the new data in the queue is moved from the original position to the head of the queue. Figure 3 is a diagram showing an example of LRU algorithm data access, referring to Figure 3 When data A, B, C, D, and E enter the cache queue, if the queue is not full, data A, B, C, D, and E are directly inserted into the cache queue. When data F enters the cache queue, if the cache queue is full, data A at the end of the queue is removed; when accessing data C, if data C is in the cache queue, data C is moved from the original position to the head of the queue; when accessing data G, if data G is not in the cache queue and the cache queue is full, data B at the end of the queue is removed and data G is inserted into the head of the queue. Summary of the invention

[0005] The embodiments of the present disclosure provide a cache management method, a cache management device and an electronic device, which can manage the priority and activity of data so that both high-frequency data and new data are retained in the cache, thereby improving the cache hit rate and access efficiency.

[0006] According to a first aspect of an embodiment of the present disclosure, a cache management method is provided, which includes: receiving a data access request; in response to first data targeted by the data access request being stored in the cache, increasing the activity of the first data, and adjusting the priority of the first data based on the increased activity of the first data; in response to the first data not being stored in the cache and the cache being full, deleting second data among the data with the lowest priority in the cache, loading the first data into the cache, and setting the priority and activity of the first data.

[0007] Optionally, the cache management method further includes: in response to the first data not being stored in the cache and the cache being not full, loading the first data into the cache and setting the priority and activity of the first data.

[0008] Optionally, the cache management method also includes: in response to the arrival of a time slice, determining the number of accesses to the cache; in response to the number of accesses being greater than a preset access threshold, lowering the priority of each data stored in the cache, and lowering the activity of each data stored in the cache; in response to the number of accesses being less than or equal to the preset access threshold, keeping the priority and activity of each data stored in the cache unchanged.

[0009] Optionally, the priority and activity of the data stored in the cache are reflected by a priority list, wherein the priority list includes multiple priority queues, each priority queue has a unique priority and each priority queue includes at least one node, and each node includes the activity of the data corresponding to the node.

[0010] Optionally, the step of adjusting the priority of the first data based on the increased activity of the first data includes: in response to the increased activity of the first data being greater than or equal to a preset activity threshold, moving the node corresponding to the first data from the current i-th priority queue to the head of the i+1-th priority queue to adjust the priority of the first data, where i is an integer greater than or equal to 1.

[0011] Optionally, the step of deleting the second data among the data with the lowest priority in the cache includes: deleting the node at the end of the first priority queue, and deleting the second data corresponding to the node at the end of the first priority queue from the cache.

[0012] Optionally, the step of setting the priority and activity of the first data includes: inserting a node corresponding to the first data into the head of a second priority queue, and assigning a value to the activity included in the inserted node.

[0013] Optionally, the step of lowering the priority of each data stored in the cache includes: connecting the first priority queue to the tail of the second priority queue; updating the priority of the i-th priority queue to i-1, and updating the priority of the first priority queue to N, where N is the number of priorities, i is an integer greater than 1 and less than or equal to N, and the priorities of the N-th priority queue to the first priority queue decrease successively.

[0014] Optionally, the activity included in each node is in array form, wherein the step of reducing the activity of each data stored in the cache includes: performing subtraction and / or shift operations on the activity included in each node to reduce the activity of each data stored in the cache.

[0015] According to a second aspect of an embodiment of the present disclosure, a cache management device is provided, including: a data request receiving unit, configured to receive a data access request; a first data processing unit, configured to, in response to the first data targeted by the data access request being stored in the cache, increase the activity of the first data, and adjust the priority of the first data based on the increased activity of the first data; a second data processing unit, configured to, in response to the first data not being stored in the cache and the cache being full, delete second data from the data with the lowest priority in the cache, load the first data into the cache, and set the priority and activity of the first data.

[0016] Optionally, the second data processing unit is configured to, in response to the first data not being stored in the cache and the cache being not full, load the first data into the cache and set the priority and activity of the first data.

[0017] Optionally, the cache management device also includes a third data processing unit, which is configured to determine the number of accesses to the cache in response to the arrival of a time slice; in response to the number of accesses being greater than a preset access threshold, reduce the priority of each data stored in the cache, and reduce the activity of each data stored in the cache; in response to the number of accesses being less than or equal to the preset access threshold, keep the priority and activity of each data stored in the cache unchanged.

[0018] Optionally, the priority and activity of the data stored in the cache are reflected by a priority list, wherein the priority list includes multiple priority queues, each priority queue has a unique priority and each priority queue includes at least one node, and each node includes the activity of the data corresponding to the node.

[0019] Optionally, the first data processing unit is configured to move the node corresponding to the first data from the current i-th priority queue to the head of the i+1-th priority queue in response to the increased activity of the first data being greater than or equal to a preset activity threshold, so as to adjust the priority of the first data, where i is an integer greater than or equal to 1.

[0020] Optionally, the second data processing unit is configured to delete the node at the tail of the first priority queue, and delete the second data corresponding to the node at the tail of the first priority queue from the cache.

[0021] Optionally, the second data processing unit is configured to insert a node corresponding to the first data into the head of the second priority queue, and assign a value to the activity included in the inserted node.

[0022] Optionally, the third data processing unit is configured to connect the first priority queue to the tail of the second priority queue; update the priority of the i-th priority queue to i-1, and update the priority of the first priority queue to N, where N is the number of priorities, i is an integer greater than 1 and less than or equal to N, and the priorities of the N-th priority queue to the first priority queue decrease in sequence.

[0023] Optionally, the activity included in each node is in array form, and the third data processing unit is configured to perform subtraction and / or shift operations on the activity included in each node to reduce the activity of each data stored in the cache.

[0024] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, comprising: at least one processor; a cache; and at least one memory storing computer executable instructions, wherein the computer executable instructions, when executed by the at least one processor, cause the at least one processor to execute the cache management method as described above.

[0025] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium storing instructions is provided, and when the instructions are executed by a processor, the cache management method as described above is implemented.

[0026] According to the cache management method, cache management device and electronic device disclosed in the present invention, the activity and priority of the data in the cache can be managed, so that the data with high access frequency and new data can be stored in the cache, thereby improving the cache hit rate and data access efficiency, and at the same time, it can reduce the burden of the processor and improve the speed of cache management. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a diagram showing an example of LFU algorithm data access.

[0028] Figure 2 is a diagram showing the data structure of the LRU algorithm.

[0029] Figure 3 is a diagram showing an example of LRU algorithm data access.

[0030] Figure 4 is a diagram illustrating an example of a defect of the LFU algorithm.

[0031] Figure 5 is a diagram illustrating an example of a defect of the LRU algorithm.

[0032] Figure 6 is a diagram illustrating a computing framework of a cache according to an embodiment of the present disclosure.

[0033] Figure 7 is a flowchart illustrating a cache management method according to an embodiment of the present disclosure.

[0034] Figure 8 is a diagram illustrating a priority queue according to an embodiment of the present disclosure.

[0035] Fig. 9 is a diagram illustrating an example of adjusting the priority of first data according to an embodiment of the present disclosure.

[0036] Fig.10is a diagram illustrating an example of deleting second data among data with the lowest priority in a cache and setting the priority and activity of first data according to an embodiment of the present disclosure.

[0037] Fig.11 is a diagram illustrating an example of managing a priority queue according to an embodiment of the present disclosure.

[0038] Fig.12 is a diagram illustrating another example of managing a priority queue according to an embodiment of the present disclosure.

[0039] Fig.13 is a diagram illustrating an example of reducing activity of each data stored in a cache according to an embodiment of the present disclosure.

[0040] Fig.14 is a diagram illustrating an example of implementing activity management through PIM in a DRAM buffer according to an embodiment of the present disclosure.

[0041] Fig.15 is a diagram illustrating another example of implementing activity management through PIM in a DRAM buffer according to an embodiment of the present disclosure.

[0042] Fig.16 is a diagram illustrating an example of application of a cache management method according to an embodiment of the present disclosure.

[0043] Fig.17 is a block diagram illustrating a cache management device according to an embodiment of the present disclosure.

[0044] Fig.18 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following specific embodiments are provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be clear after understanding the disclosure of the present disclosure. For example, the order of operations described herein is only an example and is not limited to those orders set forth herein, but can be changed as will be clear after understanding the disclosure of the present disclosure, except for operations that must occur in a specific order. In addition, for greater clarity and conciseness, descriptions of features known in the art may be omitted.

[0046] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein have been provided to illustrate only some of the many possible ways to implement the methods, devices, and / or systems described herein, many of which will be clear after understanding the disclosure of the present disclosure.

[0047] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more.

[0048] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions should not be limited by these terms. Instead, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first member, first component, first region, first layer, or first portion referred to in the examples may also be referred to as the second member, second component, second region, second layer, or second portion.

[0049] In the specification, when an element (such as a layer, a region, or a substrate) is described as being “on”, “connected to”, or “coupled to” another element, the element may be directly “on”, “connected to”, or “coupled to” another element, or one or more other elements may be present therebetween. Conversely, when an element is described as being “directly on”, “directly connected to”, or “directly coupled to” another element, there may be no other elements present therebetween.

[0050] The terms used herein are only used to describe various examples and are not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" indicate the presence of the described features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by a person of ordinary skill in the art to which the present disclosure belongs after understanding the present disclosure. Unless explicitly defined as such herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal manner.

[0052] Furthermore, in the description of examples, when it is considered that a detailed description of a well-known related structure or function would cause vague interpretation of the present disclosure, such a detailed description will be omitted.

[0053] The LFU algorithm and the LRU algorithm described above both have certain defects.

[0054] First, in the LFU algorithm, high-frequency data will reside in the cache for a long time, occupying cache space, so that the data with high recent access frequency cannot reside in the cache, but is frequently swapped in and out, and the access frequency of the swapped-out data cannot be accumulated, further causing it to be swapped in and out all the time. On the other hand, if the accessed data is not in the cache, it is necessary to load the data into the cache before accessing it, which greatly prolongs the time to access the data. At the same time, a large amount of resources will be consumed when data is frequently swapped in and out.

[0055] Figure 4 is a diagram showing an example of a defect of the LFU algorithm. Figure 4 , when accessing data F, since data F is not in the cache, the least frequently accessed data E is swapped out from the cache, and data F is loaded into (i.e., swapped into) the cache. Thereafter, when accessing data E, since data E is not in the cache, the least frequently accessed data F is swapped out from the cache, and data E is swapped into the cache, and then this process is repeated 40 times. During this period, data E and F are frequently swapped in and out, while data A, B, C, and D have not been accessed, but have been occupying cache space.

[0056] Secondly, in the LRU algorithm, if a large amount of new data is accessed once, the frequently accessed data in the cache will be swapped out of the cache, while the new data that is only accessed once cannot be evicted from the cache in time and occupies cache space. This results in all data being unable to be accessed through the cache, which greatly prolongs the data access time and reduces the data access efficiency, while also consuming a large amount of software and hardware resources.

[0057] Figure 5 is a diagram showing an example of a defect of the LRU algorithm. Figure 5 Although the LRU algorithm does not record the access frequency of data, in order to explain the defects of the LRU algorithm, the number of cache hits is calculated here by the access frequency. When accessing data F, since data F is not in the cache, the data A at the end of the queue with a higher access frequency is swapped out of the cache, and data F is swapped into the cache. Later, when accessing data A, it is found that data A has been swapped out of the cache, so it is necessary to swap data B at the end of the queue out of the cache, and then swap data A into the cache. Later, when accessing data B, it is found that data B has been swapped out of the cache, and it is necessary to swap data C at the end of the queue out of the cache, and then swap data B into the cache. However, in this process, data F, which is only accessed once, has never been swapped out of the cache, but has been occupying cache space in the cache.

[0058] In addition, both the LFU algorithm and the LRU algorithm are usually run in the CPU or in a simple logic processing unit. However, in order to run the algorithm in the CPU, data needs to be loaded into the CPU, which consumes CPU resources. On the other hand, the logic processing unit can generally only perform extremely simple calculations and cannot perform slightly more complex calculations.

[0059] To solve the above problems and / or disadvantages, embodiments of the present disclosure provide a cache management method, a cache management device, and an electronic device.

[0060] Figure 6 is a diagram illustrating a computing framework of a cache according to an embodiment of the present disclosure.

[0061] Reference Figure 6 , a cache computing framework 100 includes a dynamic random access memory (DRAM) buffer 101 and a non-volatile memory 102 (for example, but not limited to, an SSD NAND flash memory). The DRAM buffer 101 may include / serve as a cache, and the cache may be used to store frequently accessed data (including data to be written to or read from the non-volatile memory 102), and the non-volatile memory 102 may be used to store data. The cache management algorithm and PIM (Processing in Memory) according to an embodiment of the present disclosure may be implemented in the DRAM buffer 101.

[0062] Figure 7 is a flow chart showing a cache management method according to an embodiment of the present disclosure. Figure 6 As shown, the cache management method can be executed in the DRAM buffer 101.

[0063] Reference Figure 7 In step S701 , a data access request is received. When data needs to be read from the non-volatile memory 102 or written to the non-volatile memory 102 , a data access request is generated and sent to the DRAM buffer 101 .

[0064] In step S702, in response to the first data (ie, data to be accessed) targeted by the data access request being stored in the cache, the activity of the first data is increased, and the priority of the first data is adjusted based on the increased activity of the first data.

[0065] Here, the activity may include the access frequency of the data, but the present disclosure is not limited thereto. For example, the activity may also include the update frequency of the predetermined data or the importance of the data. The following description is made by taking the activity as the access frequency of the data as an example. When the first data is stored in the cache, the access frequency of the first data may increase by N, where N is a positive integer, which may be limited according to the actual application, for example, N may be 1.

[0066] According to an embodiment of the present disclosure, the priority and activity of data stored in the cache may be reflected by a priority list. Here, the priority list may include multiple priority queues. Figure 8 is a diagram showing a priority queue according to an embodiment of the present disclosure, referring to Figure 8 , each priority queue has a unique priority and each priority queue includes at least one node, each node includes the activity of the data corresponding to the node. In addition, each node may also include a data address, a front pointer and a back pointer, the data address indicates the address of the data corresponding to the node in the cache, the front pointer points to the previous node of the current node, and the back pointer points to the next node of the current node. The first priority queue is the queue with the lowest priority, and its priority can be 0, the priority of the second priority queue can be 1, and the priorities of other priority queues are analogous. Optionally, the nodes in each priority queue can be arranged from new to old according to the access time, and when the data corresponding to any node is accessed, the position of the any node in the queue can be adjusted. The nodes in each priority queue can be arranged from high to low according to the access frequency, and when the data corresponding to any node is accessed, the position of the any node in the queue can be adjusted. The nodes in each priority queue can be arranged by comprehensively considering the access time and the access frequency, and when the data corresponding to any node is accessed, the position of the any node in the queue can be adjusted.

[0067] According to an embodiment of the present disclosure, in step S702, adjusting the priority of the first data based on the increased activity of the first data may include: in response to the increased activity of the first data being greater than or equal to a preset activity threshold, moving the node corresponding to the first data from the current i-th priority queue to the head of the i+1-th priority queue to adjust the priority of the first data, where i is an integer greater than or equal to 1. On the other hand, when the increased activity of the first data is less than the preset activity threshold, the priority of the first data may be kept unchanged. Here, the preset activity threshold may be determined according to actual needs, and the present disclosure does not impose any limitation on this.

[0068] Fig. 9 is a diagram showing an example of adjusting the priority of first data according to an embodiment of the present disclosure, referring to Fig. 9When the increased activity of the first data is greater than or equal to the preset activity threshold, the first data can be moved from the i-th priority queue to the head of the (i+1)-th priority queue, thereby increasing the priority of the first data.

[0069] Return to reference Figure 7 In step S703, in response to the first data not being stored in the cache and the cache being full, the second data in the data with the lowest priority in the cache is deleted, the first data is loaded into the cache, and the priority and activity of the first data are set. Alternatively, in response to the first data not being stored in the cache and the cache being not full, the first data is loaded into the cache, and the priority and activity of the first data are set.

[0070] Fig.10 is a diagram illustrating an example of deleting second data among data with the lowest priority in a cache and setting the priority and activity of first data according to an embodiment of the present disclosure.

[0071] Reference Fig.10 , when the cache is full, the node at the end of the first priority queue can be deleted, and the second data corresponding to the node at the end of the first priority queue can be deleted from the cache. Here, the node at the end of the queue with a priority of 0 can be deleted, and the data corresponding to the node can be deleted. At the same time, the node corresponding to the first data can be inserted into the head of the second priority queue (a queue with a priority of 1), and the activity included in the inserted node can be assigned a value. Alternatively, when the cache is not full, the node corresponding to the first data can be directly inserted into the head of the second priority queue (a queue with a priority of 1), and the activity included in the inserted node can be assigned a value without deleting any node. When assigning a value to the activity, the activity can be set to, for example, 1, but the present disclosure is not limited to this. As described above, the activity can represent the access frequency of the data.

[0072] According to an embodiment of the present disclosure, the cache management method also includes: in response to the arrival of a time slice, determining the number of cache accesses; in response to the number of accesses being greater than a preset access threshold, lowering the priority of each data stored in the cache, and lowering the activity of each data stored in the cache; in response to the number of accesses being less than or equal to the preset access threshold, keeping the priority and activity of each data stored in the cache unchanged.

[0073] As an example, when the time slice arrives, the sum of the access times of all data in the cache can be determined as the access times of the cache. When the access times are greater than the preset access threshold, the priority and activity of all data in the cache can be reduced. Here, the preset access threshold can be determined according to actual needs, and the present disclosure does not make any limitation on this.

[0074] Optionally, in order to ensure the normal operation of the cache, the number of accesses to the cache may be reduced when another time slice different from the time slice related to the above-mentioned determination of the number of accesses to the cache arrives. For example, the number of accesses to each data in the cache may be reduced when the other time slice arrives to reduce the number of accesses to the cache. In addition, after determining the number of accesses to each data, if the number of accesses to a certain (or some) data is less than the minimum access threshold of its current priority, the priority of the data may be reduced. However, the present disclosure is not limited thereto, and the number of accesses to the cache may also be reduced in other ways. In addition, the time slice related to the above-mentioned determination of the number of accesses to the cache may be the same or different in duration from the above-mentioned other time slice. When the durations of the two are different, it may happen that two time slices arrive at the same time. In this case, the number of accesses to the cache may be reduced first, and then it may be determined whether the number of accesses to the cache exceeds the preset access threshold, but the present disclosure is not limited thereto.

[0075] According to an embodiment of the present disclosure, the step of lowering the priority of each data stored in the cache may include: connecting the first priority queue to the tail of the second priority queue; updating the priority of the i-th priority queue to i-1, and updating the priority of the first priority queue to N, where N is the number of priorities, i is an integer greater than 1 and less than or equal to N, and the priorities from the N-th priority queue to the first priority queue decrease successively.

[0076] Fig.11 and Fig.12 is a diagram illustrating an example of managing a priority queue according to an embodiment of the present disclosure.

[0077] Reference Fig.11 , showing the operation of connecting the first priority queue to the end of the second priority queue. Specifically, the node at the head of the first priority queue (i.e., the queue with priority 0) can be connected to the node at the end of the second priority queue (i.e., the queue with priority 1). For example, the front pointer of node 3 can be pointed to node 2, and the back pointer of node 2 can be pointed to node 3. In this way, node 3 is connected to the back of node 2, and the first priority queue is linked to the back of the second priority queue.

[0078] Reference Fig.12, showing the operation of updating the priority of the i-th priority queue to i-1. The priorities of all priority queues can be updated by changing the three pointers head, tail and cur. Specifically, the initial head pointer points to the N-th priority queue (i.e., the queue with the highest priority), the tail pointer points to the first priority queue (i.e., the queue with the lowest priority), and the cur pointer points to the second priority queue. When all priority queues need to be downgraded, the head pointer can be pointed to the previous first priority queue, the tail pointer can be pointed to the previous second priority queue, and the cur pointer can be pointed to the previous third priority queue. In this way, when the time slice arrives, the priority of all data will be reduced, so that when the cache space is insufficient, it can be ensured that older data and less active data are swapped out of the cache.

[0079] According to an embodiment of the present disclosure, the activity included in each node is in array form. In this case, the step of reducing the activity of each data stored in the cache may include: performing subtraction and / or shift operations on the activity included in each node to reduce the activity of each data stored in the cache.

[0080] Fig.13 is a diagram showing an example of reducing the activity of each data stored in a cache according to an embodiment of the present disclosure, referring to Fig.13 ,The activities of all data in the cache are stored in the form of an array. When the time slice arrives, the activity of each data is reduced by performing ,subtraction and / or shift operations on all the activities in the array form.

[0081] Fig.14 is a diagram showing an example of implementing activity management through PIM in a DRAM buffer according to an embodiment of the present disclosure. Fig.14 ,PIM can perform addition, subtraction, shift and assignment operations, thereby achieving increase activity, decrease activity and pointer assignment.

[0082] Fig.15 is a diagram showing another example of implementing activity management through PIM in a DRAM buffer according to an embodiment of the present disclosure. Fig.15 The algorithm framework 1100 of the cache management method includes an activation management module 1101, a priority management module 1102, and a cache access management module 1103. The activity management module 1101 uniformly processes the activity of all data when the time slice arrives. For example, when the time slice arrives, the activity of all data is uniformly reduced (such as Fig.13 The activity management module 1101 may be implemented by PIM. The priority management module 1102 performs priority upgrade and downgrade processing. For example, if the activity of the data is greater than or equal to a preset activity threshold, the priority upgrade processing is performed (such as Fig. 9 If the time slice arrives and the number of cache accesses is greater than the preset access threshold, the downgrade process is performed (as shown in Fig.11 and Fig.12 ). The cache access management module 1101 increases the activity of the corresponding data when the cache hits (Hit), swaps the data with the lowest activity out of the cache when the cache misses (Miss), swaps the corresponding data into the cache, and sets the activity of the corresponding data.

[0083] Fig.16 2 is a diagram showing an example of application of a cache management method according to an embodiment of the present disclosure. Fig.16 At time T1, data A, B, C, and D are accessed. At this time, the cache is empty, so data A, B, C, and D are directly loaded into the cache. At time T2, data A, C, D, and E are accessed. At this time, data A, C, and D are in the cache, so the activity and priority of data A, C, and D can be improved. In this embodiment, it is defaulted that the activity of the data (such as the number of accesses) is increased by 1 for each access, and the priority is increased by one level. Whether the activity and priority are increased and / or how much they are increased can be set according to the specific situation. At time T3, data A, C, F, and G are accessed. At this time, data A and C are in the cache, so the activity and priority of data A and C can be improved, and data F and G are loaded into the cache. At time T4, data A, B, D, and F are accessed, and data A, B, D, and F are all in the cache, so the activity and priority of data A, B, D, and F can be improved. At time T5, the time slice arrives, the activity of all data decreases, and the priority will be low. Data with a priority of 0 (i.e., the priority of the first priority queue) is data to be swapped out of the cache, so priority 0 cannot be lowered, and the remaining priorities are all lowered by 1 level. At time T6, data A, F, H, and I are accessed. At this time, data A and F are in the cache, so the activity and priority of data A and F can be improved. Since the cache has only 8 locations, data E is swapped out of the cache, and then data H and I are swapped into the cache. Moreover, the priority of each data swapped into the cache is 1, and the corresponding node is at the head of the queue with a priority of 1 (i.e., the second priority queue).

[0084] According to the cache management method disclosed in the present invention, the activity and priority of the data in the cache can be managed so that the data with high access frequency and new data can be stored in the cache, thereby improving the cache hit rate and data access efficiency. At the same time, it can reduce the burden on the processor and improve the speed of cache management.

[0085] Fig.17 is a block diagram illustrating a cache management device according to an embodiment of the present disclosure.

[0086] Reference Fig.17 According to an embodiment of the present disclosure, a cache management device 1700 includes a data request receiving unit 1701, a first data processing unit 1702 and a second data processing unit 1703.

[0087] The data request receiving unit 1701 receives a data access request. In response to the first data targeted by the data access request being stored in the cache, the first data processing unit 1702 increases the activity of the first data, and adjusts the priority of the first data based on the increased activity of the first data. In response to the first data not being stored in the cache and the cache being full, the second data processing unit 1703 deletes the second data in the data with the lowest priority in the cache, loads the first data into the cache, and sets the priority and activity of the first data.

[0088] According to an embodiment of the present disclosure, in response to the first data not being stored in the cache and the cache being not full, the second data processing unit 1703 may load the first data into the cache and set the priority and activity of the first data.

[0089] According to an embodiment of the present disclosure, the cache management device 1700 further includes a third data processing unit 1704. The third data processing unit 1704 may determine the number of accesses to the cache in response to the arrival of the time slice; in response to the number of accesses being greater than a preset access threshold, reduce the priority of each data stored in the cache and reduce the activity of each data stored in the cache; in response to the number of accesses being less than or equal to the preset access threshold, keep the priority and activity of each data stored in the cache unchanged.

[0090] According to an embodiment of the present disclosure, the priority and activity of data stored in a cache are reflected by a priority list, wherein the priority list includes a plurality of priority queues, each priority queue having a unique priority and each priority queue including at least one node, each node including the activity of data corresponding to the node.

[0091] According to an embodiment of the present disclosure, the first data processing unit 1702 may move the node corresponding to the first data from the current i-th priority queue to the head of the i+1-th priority queue in response to the increased activity of the first data being greater than or equal to a preset activity threshold, so as to adjust the priority of the first data, where i is an integer greater than or equal to 1.

[0092] According to an embodiment of the present disclosure, the second data processing unit 1703 may delete the node at the tail of the first priority queue, and delete the second data corresponding to the node at the tail of the first priority queue from the cache.

[0093] According to an embodiment of the present disclosure, the second data processing unit 1703 may insert a node corresponding to the first data into the head of the second priority queue, and assign a value to the activity included in the inserted node.

[0094] According to an embodiment of the present disclosure, the third data processing unit 1704 may connect the first priority queue to the tail of the second priority queue; update the priority of the i-th priority queue to i-1, and update the priority of the first priority queue to N, where N is the number of priorities, i is an integer greater than 1 and less than or equal to N, and the priorities of the N-th priority queue to the first priority queue decrease in sequence.

[0095] According to an embodiment of the present disclosure, the activity included in each node is in array form, and the third data processing unit 1704 can perform subtraction and / or shift operations on the activity included in each node to reduce the activity of each data stored in the cache.

[0096] Fig.18 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Fig.18 The electronic device 1800 includes: a processor 1801, a cache 1802 and a memory 1803. The memory 1803 can store computer executable instructions. When the computer executable instructions are executed by the processor 1801, the processor 1801 is prompted to perform the cache management method according to the exemplary embodiment of the present disclosure.

[0097] As an example, electronic device 1800 can be a PC computer, a tablet device, a personal digital assistant, a smart phone or other device capable of executing the above-mentioned instruction set. Here, electronic device 1800 is not necessarily a single electronic device, but can also be any device or circuit capable of executing the above-mentioned instruction (or instruction set) individually or jointly. Electronic device 1800 can also be a part of an integrated control system or a system manager, or can be configured as a portable electronic device interconnected with an interface locally or remotely (for example, via wireless transmission). In addition, electronic device 1800 may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, a mouse, a touch input device, etc.). All components of electronic device 1800 can be connected to each other via a bus and / or a network.

[0098] Processor 1801 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller or a microprocessor. As an example and not limitation, processor 1801 may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0099] The processor 1801 may execute instructions or codes stored in the memory 1803, wherein the memory 1803 may also store data. Instructions and data may also be sent and received over a network via a network interface device, wherein the network interface device may employ any known transmission protocol.

[0100] The memory 1803 may be integrated with the processor 1801, for example, by placing RAM or flash memory within an integrated circuit microprocessor or the like. In addition, the memory 1803 may include a separate device, such as an external disk drive, a storage array, or any other storage device that can be used by a database system. The memory 1803 and the processor 1801 may be operatively coupled, or may communicate with each other, such as through an I / O port, a network connection, etc., so that the processor 1801 can read files stored in the memory 1803.

[0101] According to an embodiment of the present disclosure, a computer-readable storage medium is provided. When instructions in the computer-readable storage medium are executed by a processor, the processor is prompted to execute a cache management method according to an exemplary embodiment of the present disclosure.

[0102] The cache management method according to the embodiment of the present disclosure can be written as a computer program and stored on a computer-readable storage medium. Examples of computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-RLT H, BD-RE, Blu-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), card storage (such as, multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device, any other device is configured to store computer program and any associated data, data files and data structures in a non-transitory manner and provide computer program and any associated data, data files and data structures to a processor or computer so that the processor or computer can execute the computer program. In one example, the computer program and any associated data, data files and data structures are distributed on a networked computer system so that the computer program and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

[0103] According to the cache management method, cache management device and electronic device disclosed in the present invention, it is possible to solve the problem that old data with a high access frequency cannot be swapped out of the cache in time and new data cannot be swapped into the cache in the LFU algorithm, and it is possible to solve the problem that new data with a low access frequency will quickly replace data with a high access frequency in the LRU algorithm.

[0104] In addition, according to the cache management method, cache management device and electronic device disclosed in the present invention, most operations can be performed through PIM, thereby avoiding the waste of software and hardware resources and time.

[0105] In addition, according to the cache management method, cache management device and electronic device disclosed in the present invention, the cache hit rate can be improved, the processor burden can be reduced, and the speed of cache management can be improved.

[0106] The specific implementation methods of the present disclosure have been described in detail above. Although some embodiments have been shown and described, those skilled in the art should understand that these embodiments may be modified and varied without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents. These modifications and variations should also be within the scope of protection of the claims of the present disclosure.

Claims

1. A cache management method, It is characterized in that The cache management method comprises: receiving data access requests; In response to first data targeted by the data access request being stored in a cache, increasing activity of the first data, and adjusting a priority of the first data based on the increased activity of the first data; In response to the first data not being stored in the cache and the cache being full, deleting second data from the data with the lowest priority in the cache, loading the first data into the cache, and setting the priority and activity of the first data.

2. The cache management method according to claim 1, It is characterized in that The cache management method further comprises: In response to the first data not being stored in the cache and the cache being not full, the first data is loaded into the cache, and a priority and activity of the first data are set.

3. The cache management method according to claim 1, It is characterized in that The cache management method further comprises: In response to the arrival of the time slice, determining the number of accesses to the cache; In response to the number of accesses being greater than a preset access threshold, lowering the priority of each data stored in the cache and lowering the activity of each data stored in the cache; In response to the number of accesses being less than or equal to the preset access threshold, the priority and activity of each data stored in the cache are kept unchanged.

4. The cache management method according to any one of claims 1 to 3, It is characterized in that The priority and activity of the data stored in the cache is reflected by a priority list, The priority list includes a plurality of priority queues, each priority queue has a unique priority and each priority queue includes at least one node, and each node includes the activity of data corresponding to the node.

5. The cache management method according to claim 4, It is characterized in that The step of adjusting the priority of the first data based on the increased activity of the first data includes: In response to the increased activity of the first data being greater than or equal to a preset activity threshold, the node corresponding to the first data is moved from the current i-th priority queue to the head of the i+1-th priority queue to adjust the priority of the first data, where i is an integer greater than or equal to 1.

6. The cache management method according to claim 4, It is characterized in that The step of deleting the second data in the cache with the lowest priority includes: The node at the tail of the first priority queue is deleted, and the second data corresponding to the node at the tail of the first priority queue is deleted from the cache.

7. The cache management method according to claim 4, It is characterized in that The step of setting the priority and activity of the first data includes: A node corresponding to the first data is inserted into the head of the second priority queue, and the activity included in the inserted node is assigned a value.

8. The cache management method according to claim 4, It is characterized in that The step of reducing the priority of each data stored in the cache comprises: Connect the first priority queue to the tail of the second priority queue; Update the priority of the i-th priority queue to i-1, and update the priority of the first priority queue to N, where N is the number of priorities, i is an integer greater than 1 and less than or equal to N, and the priorities of the N-th priority queue to the first priority queue decrease in sequence.

9. The cache management method according to claim 4, It is characterized in that The activity included in each node is in array form, The step of reducing the activity of each data stored in the cache comprises: Subtraction and / or shift operations are performed on the activity included in each node to reduce the activity of each data stored in the cache.

10. A cache management device, It is characterized in that The cache management device comprises: A data request receiving unit, configured to receive a data access request; A first processing unit is configured to, in response to first data targeted by the data access request being stored in a cache, increase activity of the first data, and adjust a priority of the first data based on the increased activity of the first data; The second processing unit is further configured to, in response to the first data not being stored in the cache and the cache being full, delete the second data among the data with the lowest priority in the cache, load the first data into the cache, and set the priority and activity of the first data.

11. An electronic device, It is characterized in that include: at least one processor; Cache; at least one memory storing computer executable instructions, When the computer executable instructions are executed by the at least one processor, the at least one processor is prompted to execute the cache management method according to any one of claims 1 to 9.

12. A computer-readable storage medium storing instructions, It is characterized in that When the instructions are executed by a processor, the cache management method according to any one of claims 1 to 9 is implemented.

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