Photoetching method and semiconductor equipment

Abstract

The invention provides a photoetching method and semiconductor equipment, and the photoetching method comprises the steps: obtaining the charge type of the accumulated charge of a wafer; applying an ion gas to the wafer; wherein the ion gas is opposite to the accumulated charge in charge type; and performing a photoetching process on the wafer. That is to say, the present disclosure neutralizes the accumulated charges on the wafer by applying the ion gas of the opposite charge type before the photolithography process is performed on the wafer. Therefore, in the subsequent developing operation process of the wafer, developing residues are avoided, so that damage to a device on the wafer caused by the developing residues is avoided, the yield of the wafer is improved, and the performance of the device is improved. Moreover, the operation of removing development residues after the photoetching process is not needed, so that the production period can be shortened, and the production efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a photolithography method and a semiconductor device. Background Art

[0002] In the semiconductor integrated circuit manufacturing process, photolithography plays a pivotal role. Before ion implantation or etching, a photoresist pattern needs to be formed through photolithography to predefine the area to be etched or ion implanted. However, with the continuous development of the semiconductor industry, the manufacturing process is cumbersome, and the surface of the wafer is prone to static charge accumulation, which seriously affects production efficiency. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a photolithography method and a semiconductor device to shorten the production cycle and improve production efficiency.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] An embodiment of the present disclosure provides a photolithography method, comprising: obtaining a charge type of accumulated charges of a wafer; applying ion gas to the wafer; wherein the charge type of the ion gas is opposite to that of the accumulated charges; and performing a photolithography process on the wafer.

[0006] In the above solution, applying the ion gas to the wafer includes: applying the ion gas to the wafer and baking the wafer.

[0007] In the above scheme, obtaining the charge type of the accumulated charges includes: obtaining the process type of the wafer before the photolithography process; and determining the charge type of the accumulated charges based on the process type.

[0008] In the above scheme, applying the ion gas to the wafer further includes: applying the ion gas to the surface of the insulating dielectric layer of the wafer; wherein the photolithography process forms a photoresist pattern on the surface of the insulating dielectric layer.

[0009] In the above scheme, the ion gas is generated by ionization of water vapor.

[0010] In the above solution, the ion gas is applied for a time greater than 1 second.

[0011] In the above scheme, the baking temperature ranges from 90° to 220°.

[0012] An embodiment of the present disclosure also provides a semiconductor device, comprising: a process chamber and an ion gas generating unit; wherein the ion gas generating unit is configured to obtain the charge type of the accumulated charge of the wafer and apply ion gas to the wafer in the process chamber; wherein the ion gas is opposite to the charge type of the accumulated charge.

[0013] In the above solution, the semiconductor device further includes: a hot plate; wherein the hot plate is disposed in the process chamber and is configured to carry the wafer and bake the wafer.

[0014] In the above scheme, the ion gas generating unit includes: an ion source and a focusing deflection plate; wherein the ion source is configured to generate ion gas; the focusing deflection plate is configured to generate a deflection field, and based on the deflection field, focus some positively charged particles or some negatively charged particles in the ion gas to form a charged particle beam, and output the charged particle beam to the process chamber.

[0015] The disclosed embodiment provides a photolithography method, comprising: obtaining the charge type of the accumulated charge of a wafer; applying ion gas to the wafer; wherein the ion gas is opposite to the charge type of the accumulated charge; and performing a photolithography process on the wafer. That is, before performing a photolithography process on the wafer, the disclosed embodiment neutralizes the accumulated charge on the wafer by applying ion gas of the opposite charge type. In this way, in the subsequent development operation of the wafer, the generation of development residues is avoided, thereby avoiding damage to the devices on the wafer caused by the development residues, improving the wafer yield, and improving the device performance. In addition, the disclosed embodiment does not require the operation of removing the development residues after the photolithography process, which can shorten the production cycle and improve production efficiency. At the same time, the disclosed embodiment can avoid the development residues from blurring the edges of the photoresist pattern during the development process, thereby improving the accuracy of the pattern transfer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The process of the photolithography method provided in the embodiment of the present disclosure Figure 1 ;

[0017] Figure 2 Schematic diagram of the structure of the wafer provided in the embodiment of the present disclosure Figure 1 ;

[0018] Figure 3 Schematic diagram of the structure of the wafer provided in the embodiment of the present disclosure Figure 2 ;

[0019] Figure 4 Schematic diagram of the structure of the wafer provided in the embodiment of the present disclosure Figure 3 ;

[0020] Figure 5 Schematic diagram of the structure of the wafer provided in the embodiment of the present disclosure Figure 4 ;

[0021] Figure 6 The process of the photolithography method provided in the embodiment of the present disclosure Figure 2 ;

[0022] Figure 7 The process of the photolithography method provided in the embodiment of the present disclosure Figure 3 ;

[0023] Figure 8 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0025] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] If similar descriptions of “first / second” appear in the application documents, the following description is added. In the following description, the terms “first / second / third” involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that “first / second / third” can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0028] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, lithography method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, lithography method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, lithography method, article or device including the element.

[0029] Figure 1 is a schematic flow chart of an optional photolithography method provided by an embodiment of the present disclosure, which is combined with Figure 1 The steps shown are explained.

[0030] S101 . Obtain the charge type of the accumulated charges of the wafer.

[0031] Figure 2 is a schematic diagram of an optional wafer structure provided by an embodiment of the present disclosure. It should be noted that: Figure 2 Shallow Trench Isolation (STI) 20 in the substrate is used to separate adjacent active regions to prevent current leakage.

[0032] In the embodiments of the present disclosure, reference Figure 2 , the surface of the wafer 10 that has undergone the semiconductor manufacturing process usually accumulates some positive or negative charges. For example, after the wafer 10 is subjected to a dry etching process (Dry Etching), positive charges accumulate on the surface of the wafer 10. After the wafer 10 is subjected to electron beam metrology (Electron Beam Metrology), negative charges usually accumulate on the surface of the wafer 10. In the subsequent photolithography process, these charge accumulations are prone to adsorb photoresist residues and produce development residues, which ultimately affect the yield of the product. Therefore, the embodiment of the present disclosure can obtain the charge type of the accumulated charge of the wafer, so as to facilitate the clearing of the accumulated charge of the wafer in subsequent operations.

[0033] S102, applying ion gas to the wafer; wherein the ion gas has a charge type opposite to that of the accumulated charges.

[0034] Figure 3 is a schematic diagram of an optional wafer structure provided by an embodiment of the present disclosure. It should be noted that: Figure 3 The removal process of accumulated negative charges is shown in Figure 2. The removal process of positive charges can be referred to in Figure 2. Figure 3 The examples in , will not be repeated here.

[0035] In the present disclosure, in combination Figure 2 and Figure 3In the process of removing the accumulated charge of the wafer 10, the wafer 10 can be placed on a wafer stage in a processing chamber. Then, the present disclosure can use an ion source and other equipment to apply an ion gas of a charge type opposite to the accumulated charge into the processing chamber. For example, Figure 3 If the charge type of the accumulated charge of the wafer 10 is negative charge, positively charged ion gas is applied to the wafer 10. The ion gas may be ionized water vapor, and the positively charged hydrogen ions (H+) in the water vapor may neutralize the negative charges.

[0036] S103, performing a photolithography process on the wafer.

[0037] Figure 4 and Figure 5 is a schematic diagram of the structure of an optional wafer provided in an embodiment of the present disclosure. It should be noted that: Figure 4 and Figure 5 The example shows the lithography process of the wafer. It should be noted that the lithography process can be one of a dry lithography process and a wet lithography process, which is not limited here.

[0038] In the present disclosure, in combination Figure 3 and Figure 4 After neutralizing the accumulated charge on the wafer 10, the present disclosure can Figure 3 The wafer 10 is coated with a layer of photoresist (PR) 30 by spin coating or other methods.

[0039] In the present disclosure, in combination Figure 4 and Figure 5 , a lithography system or other equipment can expose the wafer 10. Then, a developer system or other equipment performs a development operation on the exposed wafer 10 to form a Figure 5 The photoresist pattern 31 is shown. Figure 4 There is no charge accumulated in the wafer 10, so Figure 5 The wafer 10 will not generate charge adsorption, and further, there will be no developer residue on the wafer 10 .

[0040] It is understandable that the embodiment of the present disclosure neutralizes the accumulated charge on the wafer by applying ion gas of the opposite charge type before the wafer is subjected to the photolithography process. In this way, in the subsequent process of developing the wafer, the generation of development residues is avoided, thereby avoiding damage to the devices on the wafer caused by the development residues, improving the wafer yield, and improving the device performance. In addition, the embodiment of the present disclosure does not require the operation of removing the development residues after the photolithography process, which can shorten the production cycle and improve production efficiency. At the same time, the embodiment of the present disclosure can avoid the development residues from blurring the edges of the photoresist pattern during the development process, thereby improving the accuracy of the pattern transfer.

[0041] In some embodiments of the present disclosure, S201 can be implemented Figure 1 S102 will be described in conjunction with each step.

[0042] S201, applying ion gas to the wafer, and baking the wafer.

[0043] In the embodiments of the present disclosure, the temperature of the wafer can affect the activity of the gas molecules, thereby affecting the rate and uniformity of charge neutralization. In the process of applying ion gas to the wafer, the present disclosure can use a hot plate (Hot Plate) and other equipment to bake the wafer. In this way, the embodiments of the present disclosure can accelerate the neutralization speed of the accumulated charge, thereby further shortening the production cycle and improving production efficiency.

[0044] In some embodiments of the present disclosure, Figure 6 S301 to S302 shown are implemented Figure 1 S101 will be described in conjunction with each step.

[0045] S301, obtaining the process type of the wafer before the photolithography process.

[0046] S302: Determine the charge type of the accumulated charges based on the process type.

[0047] In the disclosed embodiment, before the wafer is subjected to the photolithography process, the wafer is subjected to processes such as dry etching process, electron beam measurement and cleaning process. The materials and operation steps used in the process type are determined, and thus, after the corresponding process is completed, the charge type of the accumulated charge of the wafer can also be determined. For example, the dry etching process mainly uses gas plasma to etch semiconductor materials. The etched materials generally include hydrogen fluoride (HF) and carbon tetrafluoride (CF4). When hydrogen fluoride (HF) and carbon tetrafluoride (CF4) act on the wafer, positive charge accumulation will be generated on the wafer. The electron beam measurement process uses an electron beam to scan the surface of the wafer. Due to the interaction between the electron beam and the wafer, charge accumulation may be caused on the surface of the wafer, which is generally negative charge. The cleaning process uses a chemical solution to remove particles, organic matter, metal ions and oxides on the wafer. The cleaning solutions mainly used generally include acidic cleaning solutions and alkaline cleaning solutions. The acidic cleaning solution generally includes hydrogen chloride (HCl). When the hydrogen chloride in the cleaning solution acts on the wafer, the wafer will be positively charged. Alkaline cleaning solutions usually include ammonium hydroxide (NH4OH). When the ammonium hydroxide in the cleaning solution acts on the wafer, the wafer will be negatively charged. In this way, the embodiment of the present disclosure can obtain the process type of the wafer before the photolithography process, and confirm the charge type of the accumulated charge based on the process type before the photolithography process. Therefore, the present disclosure does not need to use additional measurement equipment to measure the charge type of the accumulated charge of the wafer, thereby further shortening the production cycle and improving production efficiency.

[0048] In some embodiments of the present disclosure, S401 can be used to implement Figure 1 S102 will be described in conjunction with each step.

[0049] S401, applying ion gas to the surface of the insulating dielectric layer of the wafer; wherein a photolithography process forms a photoresist pattern on the surface of the insulating dielectric layer.

[0050] In the embodiments of the present disclosure, reference Figure 2 , the wafer 10 includes a substrate 11 and an insulating dielectric layer 12. The substrate 11 may be a semiconductor substrate; specifically, it includes at least one single semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, a SiC substrate, etc.

[0051] In the embodiments of the present disclosure, reference Figure 2The insulating dielectric layer 12 may be made of silicon dioxide (SiO2). The insulating dielectric layer 12 is grown on the substrate 11. The insulating dielectric layer 12 may be formed on the substrate 11 by a process such as plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). A photolithography process forms a photoresist pattern on the surface of the insulating dielectric layer 12.

[0052] In the embodiments of the present disclosure, Figure 2 and Figure 3 The insulating dielectric layer 12 is an insulator and is easy to absorb charges, so that the surface of the insulating dielectric layer 12 is easy to accumulate charges. In the embodiment of the present disclosure, ion gas can be applied to the surface of the insulating dielectric layer 12 until the accumulated charges on the surface of the insulating dielectric layer 12 are neutralized. In this way, the surface of the insulating dielectric layer 12 will not accumulate charges. In addition, the photolithography process forms a photoresist pattern on the surface of the insulating dielectric layer 12. Therefore, in the subsequent process of developing the wafer, the generation of development residues on the surface of the insulating dielectric layer 12 is avoided.

[0053] In some embodiments of the present disclosure, the ionized gas is generated by ionizing water vapor.

[0054] In the disclosed embodiment, water vapor will produce positively charged hydrogen ions (H+) and negatively charged hydroxide ions (OH-) during the ionization process. The accumulated charge on the surface of the wafer may be positively charged or negatively charged. The ions in the ionized water vapor can interact with the charge on the surface of the wafer and achieve neutralization through charge transfer. In other words, the ion gas that removes the positive charge accumulation and the negative charge accumulation is formed by water vapor. Thereby, the stability of the process is improved.

[0055] It should be noted that the ionized gas is not limited to ionized water vapor, but may be other types, which are not limited here.

[0056] In some embodiments of the present disclosure, the ion gas is applied for a time greater than 1 s.

[0057] In the disclosed embodiment, in order to ensure the repeatability and stability of the process, the application time of the ion gas can be greater than 1 second. In other words, 1 second can be the minimum time for the ion gas to be introduced to ensure the consistency of each operation. It should be noted that in the actual semiconductor manufacturing process, the time for introducing the ion gas may also need to be optimized according to the specific process requirements and experimental conditions to achieve effective charge neutralization while minimizing the impact on the wafer material and device performance.

[0058] In some embodiments of the present disclosure, the baking temperature ranges from 90° to 220°.

[0059] It should be noted that in the actual semiconductor manufacturing process, the baking temperature may also need to be optimized according to specific process requirements and experimental conditions to achieve effective charge neutralization while minimizing the impact on wafer materials and device performance.

[0060] In the embodiment of the present disclosure, high temperature helps to release or dissipate the charge through the ion gas. In the process of applying the ion gas to the wafer, the present disclosure can use a hot plate or other equipment to bake the wafer, and the baking temperature range is 90° to 220°. In this way, the embodiment of the present disclosure can accelerate the neutralization speed of the accumulated charge, thereby further shortening the production cycle and improving production efficiency.

[0061] Figure 7 is a schematic flow chart of another optional photolithography method provided by the embodiment of the present disclosure, which will be combined with Figure 7 The steps in are described below.

[0062] S501, heating and introducing charged gas.

[0063] In the embodiment of the present disclosure, in the process of removing the accumulated charge of the wafer, the present disclosure can heat and pass a charged gas (i.e., ion gas). For example, if the charge type of the accumulated charge of the wafer is negative charge, a positively charged ion gas is passed into the wafer. The ion gas can be water vapor containing positively charged hydrogen ions (H+), and the positively charged hydrogen ions (H+) in the water vapor can neutralize the negative charge accumulated on the surface of the wafer. If the charge type of the accumulated charge of the wafer is positive charge, a negatively charged ion gas is passed into the wafer. The ion gas can be water vapor containing hydroxide ions (OH-), and the hydroxide ions (OH-) in the water vapor can provide additional electrons to neutralize the positive charge accumulated on the surface of the wafer. As a result, there is no charge accumulation on the wafer.

[0064] In the embodiment of the present disclosure, during the process of introducing ion gas into the wafer, the present disclosure can heat (bake) the wafer. In this way, the embodiment of the present disclosure can accelerate the neutralization speed of the accumulated charge, thereby further shortening the production cycle and improving production efficiency.

[0065] S502: Charge neutralization.

[0066] In the embodiments of the present disclosure, debugging is usually performed in the actual production of semiconductors. Therefore, in the embodiments of the present disclosure, a feedback control system can be established during the debugging process to feed back the detection results of the lithography process to the process of neutralizing the accumulated charge of the wafer to achieve closed-loop control. For example, the embodiments of the present disclosure can adjust the process parameters for neutralizing the accumulated charge of the wafer according to the results of the subsequent lithography process. First, optical and electron microscopes, mass spectrometers and other equipment are used to collect parameter information such as the degree of development residue of the wafer after the lithography process. Then, data analysis techniques such as statistical process control (SPC) or computer simulation software are used to predict the effects of different process parameters for neutralizing the accumulated charge of the wafer on the development residue of the lithography process. Finally, optimization is performed according to specific process requirements and experimental conditions to achieve effective charge neutralization.

[0067] S503, glue application.

[0068] S504: Exposure.

[0069] S505: Development.

[0070] In the disclosed embodiment, the photolithography process generally includes coating, exposure and development. After completing S501 and S502, there is no charge accumulation on the wafer. The coating, exposure and development operations are performed on the wafer without accumulated charge to form a photoresist pattern. In this way, during the development operation, the wafer will not generate charge adsorption, and then, there is no development residue on the wafer. Therefore, the disclosed embodiment does not need to perform the operation of cleaning the development residue after the photolithography process, which can shorten the production cycle and improve production efficiency.

[0071] Figure 8 is a schematic diagram of the structure of an optional semiconductor device 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 8 Only one wafer 10 and one heating plate 130 are illustrated in the figure, and the number of heating plates 130 and wafers 10 may be other numbers, which is not limited here.

[0072] In some embodiments of the present disclosure, reference Figure 8 The semiconductor device 100 includes a process chamber 110 and an ion gas generating unit 120. The ion gas generating unit 120 is configured to obtain the charge type of the accumulated charge of the wafer and apply ion gas to the wafer 10 in the process chamber 110. The charge type of the ion gas is opposite to that of the accumulated charge.

[0073] In the embodiments of the present disclosure, reference Figure 8, the wafer 10 can be charged neutralized in the process chamber 110. The ion gas generating unit 120 can introduce ion gas of a charge type opposite to the accumulated charge into the process chamber 110, and then the ion gas is applied to the wafer to neutralize the accumulated charge of the wafer. Therefore, the embodiment of the present disclosure does not need to perform the operation of cleaning the residual development after the photolithography process, which can further shorten the production cycle and improve the production efficiency.

[0074] In some embodiments of the present disclosure, reference Figure 8 The semiconductor device 100 further includes a heat plate 130 . The heat plate 130 is disposed in the process chamber 110 . The heat plate 130 is configured to carry the wafer 10 and bake the wafer 10 .

[0075] In the embodiments of the present disclosure, reference Figure 8 The hot plate 130 can heat the wafer 10. In this way, the embodiment of the present disclosure can accelerate the neutralization process of the accumulated charges. Thus, the embodiment of the present disclosure can further shorten the production cycle and improve the production efficiency.

[0076] In some embodiments of the present disclosure, reference Figure 8 The hot plate 130 is further configured to bake the wafer 10 during the process of applying the ion gas to the wafer 10 .

[0077] In some embodiments of the present disclosure, reference Figure 8 , the baking temperature of the hot plate 130 ranges from 90° to 220°.

[0078] In some embodiments of the present disclosure, reference Figure 8 The ion gas generating unit 120 includes an ion source 121 and a focusing deflection plate 122. The ion source 121 is configured to generate ion gas.

[0079] In the embodiments of the present disclosure, reference Figure 8 The ion source 121 may include a gas source, a radio frequency power supply (RF Power Supply), an electrode assembly, and other devices. The gas source is used to generate a reactive gas for plasma, for example, the reactive gas may be water vapor. The RF power supply may provide a high-frequency alternating electric field through the electrode assembly to excite and ionize the reactive gas molecules to form ionized gas.

[0080] In the embodiments of the present disclosure, reference Figure 8The focusing deflection plate 122 is configured to generate a deflection field, and based on the deflection field, focus some positively charged particles or some negatively charged particles in the ion gas to form a charged particle beam, and output the charged particle beam to the process chamber 110. The focusing deflection plate 122 can also control and guide the movement of the charged particle beam, so that the ion gas can be directly applied to the surface of the wafer 10, avoiding expanding the coverage of the ion gas and affecting the performance of other devices. For example, if the charge type of the accumulated charge of the wafer 10 is positive charge, a charged particle beam of negatively charged particles is sprayed onto the surface of the wafer 10. If the charge type of the accumulated charge of the wafer 10 is negative charge, a charged particle beam of positively charged particles is sprayed onto the surface of the wafer 10. In other words, the focusing deflection plate 122 can guide the distribution and movement of the charge, and control the charge type. Thus, the embodiment of the present disclosure can provide an ion gas of the opposite charge type to the accumulated charge.

[0081] In some embodiments of the present disclosure, reference Figure 8 The ion gas generating unit 120 is further configured to obtain a process type of the wafer 10 before photolithography, and determine a charge type of accumulated charges based on the process type.

[0082] In some embodiments of the present disclosure, reference Figure 8 The ion gas generating unit 120 is further configured to apply ion gas to the surface of the insulating dielectric layer of the wafer 10; wherein the photolithography process forms a photoresist pattern on the surface of the insulating dielectric layer.

[0083] In some embodiments of the present disclosure, reference Figure 8 The semiconductor device 100 is further configured to perform a photolithography process on the wafer 10 .

[0084] In some embodiments of the present disclosure, reference Figure 8 , the application time of the ion gas of the ion gas generating unit 120 is greater than 1 second.

[0085] In some embodiments of the present disclosure, reference Figure 8 The ion gas of the ion gas generating unit 120 is generated by ionizing water vapor.

[0086] The above description of the semiconductor device is similar to the description of the above-mentioned photolithography method embodiment, and has similar beneficial effects as the photolithography method embodiment. For technical details not disclosed in the semiconductor device embodiment of the present disclosure, please refer to the description of the photolithography method embodiment of the present disclosure for understanding.

[0087] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, lithography method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, lithography method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, lithography method, article or device including the element.

[0088] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The lithography methods disclosed in the several lithography method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new lithography method embodiments. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several lithography method or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new lithography method embodiments or device embodiments.

[0089] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A photolithography method, characterized in that: include: Obtaining the charge type of the accumulated charge of the wafer; applying an ion gas to the wafer; wherein the ion gas has a charge type opposite to that of the accumulated charge; A photolithography process is performed on the wafer.

2. The photolithography method according to claim 1, characterized in that: Applying the ion gas to the wafer comprises: The ion gas is applied to the wafer, and the wafer is baked.

3. The photolithography method according to claim 2, characterized in that: Obtaining the charge type of the accumulated charge includes: Acquire the process type of the wafer before the photolithography process; Based on the process type, a charge type of the accumulated charge is determined.

4. The photolithography method according to claim 1, characterized in that: Applying the ion gas to the wafer further comprises: The ion gas is applied to the surface of the insulating dielectric layer of the wafer; wherein the photolithography process forms a photoresist pattern on the surface of the insulating dielectric layer.

5. The photolithography method according to claim 1, characterized in that: The ionized gas is generated by ionization of water vapor.

6. The photolithography method according to claim 1, characterized in that: The ion gas is applied for a time greater than 1 s.

7. The photolithography method according to claim 2, characterized in that: The baking temperature ranges from 90° to 220°.

8. A semiconductor device, characterized in that: include: A process chamber and an ion gas generating unit; wherein, The ion gas generating unit is configured to obtain a charge type of accumulated charges of a wafer and apply ion gas to the wafer in the process chamber; wherein the ion gas is opposite to the charge type of the accumulated charges.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device further comprises: a heat plate; wherein, The hot plate is disposed in the process chamber and is configured to carry the wafer and bake the wafer.

10. The semiconductor device according to claim 9, characterized in that The ion gas generating unit comprises: an ion source and a focusing deflection plate; wherein, The ion source is configured to generate an ion gas; The focusing deflection plate is configured to generate a deflection field, focus some positively charged particles or some negatively charged particles in the ion gas based on the deflection field to form a charged particle beam, and output the charged particle beam to the process chamber.

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