Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of low yield of the semiconductor structure. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged; forming a groove in the first surface; injecting preset ions into the substrate at the bottom of the groove to form an injection region; preset ions react with the substrate, so that a mark layer is formed in the injection region; and thinning the second surface until the mark layer is exposed. The mark layer is used as a stop mark when the second surface of the substrate is thinned, and the thinning thickness can be controlled, so that the thinned substrate has the required thickness, a device structure can be manufactured on the substrate, and the yield of a semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of science and technology, the application of semiconductor structures is becoming more and more extensive. In the fields of computers, communications, etc., semiconductor structures with different functions are needed. The semiconductor structure includes a substrate, and the device structure is made on the front and / or back of the substrate. During the manufacturing process, the back of the substrate usually needs to be thinned. However, the thickness of the thinned back of the substrate is often difficult to control, so that the device structure inside the thinned substrate is exposed, or the thickness of the substrate after thinning is insufficient, making it difficult to make the required device structure inside the substrate, and the yield rate of the semiconductor structure is low. Summary of the invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to control the thinning thickness of the substrate and improve the yield of the semiconductor structure.

[0004] According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0005] Providing a substrate having a first surface and a second surface disposed opposite to each other;

[0006] forming a groove on the first surface;

[0007] Implanting predetermined ions into the substrate at the bottom of the trench to form an implantation region;

[0008] The predetermined ions react with the substrate to form a marking layer in the implanted area;

[0009] The second surface is thinned until the marking layer is exposed.

[0010] In some possible embodiments, the substrate is annealed to allow the preset ions to react with the substrate to form the marking layer.

[0011] In some possible embodiments, before the predetermined ions are implanted into the substrate at the bottom of the trench, the method further includes:

[0012] A first protection layer is formed on the sidewall of the trench, and the bottom of the trench covered with the first protection layer exposes the substrate.

[0013] In some possible embodiments, forming the first protection layer on the sidewall of the trench includes:

[0014] forming the first protective layer on the sidewalls and bottom of the trench and the first surface;

[0015] The first protection layer on the first surface and at the bottom of the trench is removed, the first protection layer on the sidewall of the trench is retained, and the bottom of the trench covered with the first protection layer exposes the substrate.

[0016] In some possible embodiments, after forming the first protection layer on the sidewall of the trench and before implanting the preset ions into the substrate at the bottom of the trench, the method further includes:

[0017] The substrate is etched along the trench covered with the first protection layer so that the depth of the trench increases.

[0018] In some possible embodiments, forming the groove on the first surface includes:

[0019] The first surface is etched to form a groove; wherein the groove includes at least two areas arranged along a first direction, each of the areas includes a first section and a second section arranged at intervals along the first direction, the first section includes at least two first channels extending along the second direction and arranged at intervals along the first direction, the second section includes at least two second channels extending along the first direction and arranged at intervals along the second direction, and in two adjacent areas, the first channel is adjacent to the second channel along the first direction.

[0020] In some possible embodiments, implanting predetermined ions into the substrate at the bottom of the trench includes:

[0021] The preset ions are injected into the substrate at the bottom of the first channel and the second channel to form the injection region; wherein the injection region includes a plurality of first partitions arranged at intervals along the first direction, and a plurality of second partitions arranged at intervals along the second direction, the plurality of first partitions are opposite to the plurality of first channels, and the plurality of second partitions are opposite to the plurality of second channels.

[0022] In some possible embodiments, the substrate is provided, wherein the substrate has the first surface and the second surface which are arranged opposite to each other, including:

[0023] providing a substrate;

[0024] forming a second protective layer on the substrate, and forming a barrier layer on the second protective layer, wherein a surface of the barrier layer facing away from the substrate is the first surface, and a surface of the substrate facing away from the second protective layer is the second surface;

[0025] Accordingly, etching the first surface includes:

[0026] The barrier layer, the second protection layer and the substrate are etched to form the trench, which penetrates the barrier layer and the second protection layer and extends into the substrate.

[0027] In some possible embodiments, the material of the substrate includes silicon, silicon carbide, gallium nitride, germanium, silicon boride or silicon phosphide, the preset ions are oxygen ions, and the marking layer is an oxide layer.

[0028] In some possible embodiments, thinning the second surface includes: thinning the second surface by a chemical mechanical polishing process until the marking layer is identified.

[0029] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

[0030] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure forms a groove on the first surface of the substrate, injects preset ions into the interior of the substrate at the bottom of the groove to form an implantation area, and converts the implantation area into a marking layer by reacting the preset ions with the substrate. The marking layer is used as a stop mark when thinning the second surface of the substrate, and the thinning thickness can be controlled so that the substrate after thinning has a desired thickness to ensure that the device structure can be manufactured on the substrate, thereby improving the yield of the semiconductor structure.

[0031] According to some embodiments, a second aspect of the present disclosure provides a semiconductor structure, comprising:

[0032] A substrate, the substrate having a first surface and a second surface arranged opposite to each other, the first surface being provided with grooves;

[0033] A marking layer is located inside the substrate at the bottom of the groove, and the marking layer is exposed on the second surface of the substrate.

[0034] In some possible embodiments, the first surface of the substrate further has a groove, and a plurality of active pillars are disposed in the groove, and the plurality of active pillars are arranged at intervals along the first direction and at intervals along the second direction;

[0035] The semiconductor structure also includes a plurality of bit lines disposed in the substrate, the plurality of bit lines are located on the side of the active pillars facing the second surface and are arranged at intervals along the first direction, and each of the bit lines contacts a plurality of the active pillars located in the same column along the second direction.

[0036] In some possible embodiments, the semiconductor structure further includes a plurality of isolation layers disposed in the groove, the plurality of isolation layers extending along the first direction and arranged at intervals along the second direction, and the isolation layers are disposed between two adjacent columns of the active pillars along the second direction.

[0037] In some possible embodiments, the semiconductor structure further includes a plurality of word lines disposed between adjacent isolation layers, the plurality of word lines extending along the first direction, and each of the word lines covering a portion of outer peripheral surfaces of a corresponding plurality of active pillars.

[0038] In some possible embodiments, the semiconductor structure further includes a data storage unit correspondingly disposed on each of the active pillars, and the data storage unit is located on a top surface of the active region away from the second surface of the substrate.

[0039] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0040] The semiconductor structure provided by the embodiment of the present disclosure includes a substrate and a marking layer, wherein the substrate has a first surface and a second surface arranged opposite to each other, the first surface is provided with a groove, the marking layer is located inside the substrate at the bottom of the groove, and the marking layer is exposed on the second surface of the substrate. By exposing the marking layer on the second surface of the substrate, the position of the second surface can be calibrated, thereby controlling the thickness of the substrate, avoiding the thickness of the substrate being too thick or too thin, thereby ensuring that the device structure can be manufactured on the substrate, and improving the yield rate of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

[0042] Figure 2 is a schematic structural diagram of a substrate in an embodiment of the present disclosure;

[0043] Figure 3 is a top view of a substrate in an embodiment of the present disclosure;

[0044] Figure 4 is a schematic diagram of the structure of a groove in an embodiment of the present disclosure;

[0045] Figure 5 is a schematic structural diagram of the second section of the groove in one embodiment of the present disclosure;

[0046] Figure 6 is a schematic structural diagram of the first section of a groove in an embodiment of the present disclosure;

[0047] Figure 7 It is a schematic diagram of the second stage when injecting preset ions in one embodiment of the present disclosure;

[0048] Figure 8 It is a schematic diagram of the first stage when injecting preset ions in one embodiment of the present disclosure;

[0049] Fig. 9 is a schematic diagram of the injection region of the second section in one embodiment of the present disclosure;

[0050] Fig.10 is a schematic diagram of the injection region of the first section in one embodiment of the present disclosure;

[0051] Fig.11 is a schematic diagram of the second stage when the preset ions react with the substrate in one embodiment of the present disclosure;

[0052] Fig.12 is a schematic diagram of the first stage of the reaction between the preset ions and the substrate in one embodiment of the present disclosure;

[0053] Fig.13 is a schematic diagram of a marking layer of the second section in one embodiment of the present disclosure;

[0054] Fig.14 is a schematic diagram of a marking layer of the first section in one embodiment of the present disclosure;

[0055] Fig.15 is a schematic diagram of the second section after thinning in one embodiment of the present disclosure;

[0056] Fig.16 is a schematic diagram of the first section after thinning in one embodiment of the present disclosure;

[0057] Fig.17 It is a schematic diagram of the second stage after forming the first protective layer in one embodiment of the present disclosure;

[0058] Fig.18 It is a schematic diagram of the first section after forming the first protective layer in one embodiment of the present disclosure;

[0059] Fig.19 It is a schematic diagram of the second section after a portion of the first protective layer is removed in one embodiment of the present disclosure;

[0060] Fig. 20 It is a schematic diagram of the first section after a portion of the first protective layer is removed in one embodiment of the present disclosure;

[0061] Fig.21 is a schematic diagram of the second section after the groove is deepened in one embodiment of the present disclosure;

[0062] Fig. 22 It is a schematic diagram of the first section after the groove is deepened in one embodiment of the present disclosure;

[0063] Fig.23 is a schematic diagram of an injection region in an embodiment of the present disclosure;

[0064] Fig.24 is a schematic diagram of a marking layer in an embodiment of the present disclosure;

[0065] Fig.25 The figure is a connection diagram of active pillars, bit lines, word lines, and data storage units in one embodiment of the present disclosure.

[0066] Description of reference numerals:

[0067] 10-substrate; 11-first surface;

[0068] 12- second surface; 13- substrate;

[0069] 14-second protective layer; 15-barrier layer;

[0070] 16-groove; 17-active column;

[0071] 20-groove; 21-first section;

[0072] 22-second section; 23-first channel;

[0073] 24-second channel; 30-first protective layer;

[0074] 40-injection area; 41-first partition;

[0075] 42-second partition; 50-marking layer;

[0076] 51-first layer; 52-second layer;

[0077] 60-word line; 70-bit line;

[0078] 80-Data storage unit. DETAILED DESCRIPTION

[0079] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, in which preset ions are injected into the interior of a substrate along a groove formed on a first surface of the substrate, and a marking layer is formed by the reaction of the preset ions with the substrate. The marking layer serves as a stop layer for thinning the second surface of the substrate, and can control the thickness of the substrate to ensure the yield of the semiconductor structure.

[0080] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0081] See also Figure 1 The present disclosure provides a method for manufacturing a semiconductor structure, the method comprising the following steps:

[0082] Step S100: providing a substrate, wherein the substrate has a first surface and a second surface that are oppositely disposed.

[0083] See also Figure 2 The substrate 10 has a first surface 11 and a second surface 12, and the first surface 11 and the second surface 12 are arranged opposite to each other along the thickness direction of the substrate 10. For example, the first surface 11 is the front surface (top surface) of the substrate 10, and the second surface 12 is the back surface (bottom surface) of the substrate 10. A device structure can be formed on at least one of the first surface 11 and the second surface 12, for example, a device structure is formed on the first surface 11.

[0084] In some examples, such as Figure 2 As shown, the base 10 includes a substrate 13, a second protective layer 14 and a barrier layer 15 stacked in sequence. The material of the substrate 13 includes silicon, silicon carbide, gallium nitride, germanium, silicon boride or silicon phosphide, the second protective layer 14 can be an oxide layer, such as silicon oxide, and the barrier layer 15 can be a nitride layer, such as silicon nitride. The surfaces of the barrier layer 15 and the substrate 13 facing away from each other are the first surface 11 and the second surface 12 respectively. Of course, the base 10 can also include the substrate 13 and the second protective layer 14 on the substrate 13.

[0085] In some possible implementations, a substrate 10 is provided, wherein the substrate 10 has a first surface 11 and a second surface 12 disposed opposite to each other, including:

[0086] A substrate 13 is provided; a second protective layer 14 is formed on the substrate 13, and a barrier layer 15 is formed on the second protective layer 14, wherein the surface of the barrier layer 15 facing away from the substrate 13 is the first surface 11, and the surface of the substrate 13 facing away from the second protective layer 14 is the second surface 12. The second protective layer 14 can be formed together with the shallow trench isolation structure in the substrate 13, and the barrier layer 15 can be formed by a deposition process.

[0087] Step S200: forming a first groove on the first surface.

[0088] See also Figure 3 , Figure 5 and Figure 6, etching the first surface 11 of the substrate 10 to form a groove 20 on the first surface 11, the bottom of the groove 20 is located in the substrate 10, that is, the groove 20 does not penetrate the substrate 10. In the example where the substrate 10 includes a substrate 13, a protective layer and a barrier layer 15, forming the groove 20 on the first surface 11 includes: etching the barrier layer 15, the second protective layer 14 and the substrate 13 to form the groove 20, the groove 20 penetrates the barrier layer 15 and the second protective layer 14, and extends into the substrate 13. Figure 5 and Figure 6 As shown, the bottom of the trench 20 is located in the substrate 13 .

[0089] Step S300: implanting predetermined ions into the substrate at the bottom of the first trench to form an implantation region.

[0090] See also Figure 7 and Figure 8 The preset ions are ions that react with the substrate 10. For example, the groove 20 extends into the substrate 13, the material of the substrate 13 is silicon, and the preset ions can be oxygen ions. Figure 8 As shown, the ions are implanted vertically and implanted into a certain depth of the substrate 10 at the bottom of the trench 20. Fig. 9 and Fig.10 As shown, the implantation region 40 is opposite to the trench 20 and is located inside the substrate 10 , so that the implantation region 40 is at a certain distance from the bottom of the trench 20 .

[0091] The depth of the implantation region 40 from the first surface 11 is the depth of the groove 20 plus the implantation depth of the preset ions. By forming the groove 20 on the first surface 11, the bottom of the groove 20 is at a certain distance from the first surface 11, and then the preset ions are implanted into the bottom of the groove 20 to form the implantation region 40 at a certain distance from the bottom of the groove 20, so that the implantation region 40 is at a greater distance from the first surface 11 of the substrate 10, and the difficulty of directly implanting the preset ions at the distance (depth) can be reduced, so as to reduce the difficulty of forming the implantation region 40.

[0092] Step S400: reacting the preset ions with the substrate to form a marking layer in the implanted area.

[0093] See also Figures 11 to 14 The implanted region 40 is transformed into the marking layer 50 by the reaction of the preset ions with the substrate 10. The material of the marking layer 50 is a compound formed by the reaction of the preset ions with the substrate 10. For example, the preset ions are oxygen ions, which are easy to react with other materials, and the marking layer 50 is an oxide layer.

[0094] Exemplarily, the substrate 10 is annealed to allow the predetermined ions to react with the substrate 10 to form the marking layer 50. The reaction between the predetermined ions and the substrate 10 can be promoted by thermal reaction. Fig.13and Fig.14 As shown, the marking layer 50 is located in the substrate 10 below the groove 20, that is, located on the side of the groove 20 away from the first surface 11 of the substrate 10. The marking layer 50 may be spaced from the bottom of the groove 20, that is, the marking layer 50 is not exposed in the groove 20.

[0095] Step S500: thinning the second surface until the marking layer is exposed.

[0096] See also Fig.15 and Fig.16 , the second surface 12 of the substrate 10 is thinned, and the marking layer 50 is used as a stop layer. When the marking layer 50 is exposed, the thinning is stopped so that the substrate 10 has a desired thickness. Exemplarily, the second surface 12 is thinned, including: thinning the second surface 12 by a chemical mechanical polishing (CMP) process until the marking layer is identified. After the marking layer 50 is identified, the polishing of the substrate 10 is stopped, and the surface of the substrate 10 exposed with the marking layer 50 forms a new second surface 12, and the new second surface 12 is arranged opposite to the first surface 11 of the substrate 10 along the thickness direction of the substrate 10.

[0097] In summary, the method for manufacturing a semiconductor structure in the embodiment of the present disclosure forms a groove 20 on the first surface 11 of the substrate 10, injects preset ions into the interior of the substrate 10 at the bottom of the groove 20 to form an implantation region 40, and converts the implantation region 40 into a marking layer 50 by reacting the preset ions with the substrate 10. The marking layer 50 is used as a stop mark when the second surface 12 of the substrate 10 is thinned, and the thinned thickness can be controlled so that the thinned substrate 10 has a desired thickness to ensure that the device structure can be manufactured on the substrate 10, thereby improving the yield of the semiconductor structure.

[0098] For some possible examples, see Figures 17 to 20 Before injecting preset ions into the substrate 10 at the bottom of the trench 20 , the method further includes: forming a first protective layer 30 on the sidewall of the trench 20 , and exposing the substrate 10 at the bottom of the trench 20 covered with the first protective layer 30 .

[0099] like Fig.19 and Fig. 20 As shown, the first protective layer 30 covers the sidewalls of the trench 20, but does not cover the bottom of the trench 20, and the substrate 10 is exposed in the trench 20 covered with the first protective layer 30, and the material of the first protective layer 30 can be an oxide. By providing the first protective layer 30, the sidewalls of the trench 20 are protected, and the preset ions can be prevented from entering the sidewalls of the trench 20 when the preset ions are subsequently injected, thereby ensuring that the injection area 40 is formed below the trench 20.

[0100] Wherein, forming a first protective layer 30 on the sidewall of the groove 20 includes: forming a first protective layer 30 on the sidewall and bottom of the groove 20, and on the first surface 11; removing the first protective layer 30 located on the first surface 11 and at the bottom of the groove 20, retaining the first protective layer 30 located on the sidewall of the groove 20, and exposing the substrate 10 at the bottom of the groove 20 covered with the first protective layer 30.

[0101] It is understandable that if Fig.17 and Fig.18 As shown, by depositing the first protective layer 30 and etching back, the first protective layer 30 located on the first surface 11 of the substrate 10 and the first protective layer 30 at the bottom of the groove 20 can be removed to expose the first surface 11 and the bottom of the groove 20, thereby preparing for the subsequent deepening of the groove 20.

[0102] Accordingly, see Fig.21 and Fig. 22 After forming the first protective layer 30 on the sidewall of the groove 20, before injecting preset ions into the substrate 10 at the bottom of the groove 20, it also includes: etching the substrate 10 along the groove 20 covered with the first protective layer 30 to increase the depth of the groove 20.

[0103] like Fig.21 and Fig. 22 As shown, the substrate 10 exposed in the groove 20 is etched to increase the depth of the groove 20. The increased depth of the groove 20 allows subsequent preset ion implantation to be implanted at a position farther from the first surface 11, thereby further increasing the depth of the implantation region 40 from the first surface 11.

[0104] Continue reading Figure 3 , Figure 4 , Figure 5 and Figure 6 In some possible examples, forming a groove 20 on the first surface 11 includes: etching the first surface 11 to form the groove 20; wherein the groove 20 includes at least two regions arranged along the first direction, each region includes a first section 21 and a second section 22 arranged at intervals along the second direction, the first section 21 extends along the second direction and includes at least two first channels 23 arranged at intervals along the first direction, the second section 22 includes at least two second channels 24 extending along the first direction and arranged at intervals along the second direction, and in two adjacent regions, the first channel 23 is adjacent to the second channel 24 along the first direction.

[0105] like Figure 3 and Figure 4 As shown, the first surface 11 of the substrate 10 forms a groove 20, and the groove 20 includes at least two regions, for example, two regions, each region as shown in FIG. Figure 3 and Figure 4As shown in A in the figure. At least two regions are arranged along a first direction, and the first direction is as shown in Figure 3 and Figure 4 X direction shown.

[0106] Each region includes a first section 21 (such as Figure 4 The area indicated by the mid-point dashed line) and the second section 22 (such as Figure 4 The first section 21 and the second section 22 are arranged along the second direction and are spaced apart. The second direction intersects the first direction, for example, is perpendicular to the first direction. Figure 3 and Figure 4 The first section 21 includes at least two first channels 23, for example, five, and at least two first channels 23 extend along the second direction and are arranged at intervals along the first direction. The second section 22 includes a plurality of second channels 24, for example, four, and the plurality of second channels 24 extend along the first direction and are arranged at intervals along the second direction.

[0107] like Figure 4 As shown, in two adjacent regions, the first channel 23 in one region is adjacent to the multiple second channels 24 in the other region along the first direction, that is, the positions of the first segment 21 and the second segment 22 in the two adjacent regions are different, providing a basis for the pattern of the marking layer 50 formed subsequently.

[0108] Accordingly, see Fig.23 and Figure 3 , injecting preset ions into the substrate 10 at the bottom of the groove 20, including: injecting preset ions into the substrate 10 at the bottom of the first channel 23 and the second channel 24 to form an injection area 40; wherein the injection area 40 includes a plurality of first partitions 41 arranged at intervals along the first direction, and a plurality of second partitions 42 arranged at intervals along the second direction, the plurality of first partitions 41 are opposite to the first channel 23, and the plurality of second partitions 42 are opposite to the plurality of second channels 24.

[0109] Preset ions are implanted into the substrate 10 at the bottom of the first channel 23 and the substrate 10 at the bottom of the second channel 24 to form an implantation region 40. The implantation region 40 includes a plurality of first partitions 41 and a plurality of second partitions 42, and the first partitions 41 and the second partitions 42 are both in the shape of long strips. The plurality of first partitions 41 are arranged at intervals along the first direction and are opposite to the first channel 23, that is, the plurality of first partitions 41 extend along the second direction and are located below the first channel 23. The plurality of second partitions 42 are arranged at intervals along the second direction and are opposite to the plurality of second channels 24, that is, each second partition 42 extends along the first direction and is located below the corresponding second channel 24.

[0110] See also Fig.23 and Fig.24The first partition 41 forms the first layer 51 of the marking layer 50, and the second partition 42 forms the second layer 52 of the marking layer 50. By controlling the shape and position of the first partition 41 and the second partition 42, the shape and position of the first layer and the second layer can be controlled, thereby controlling the pattern of the marking layer 50.

[0111] For some possible examples, see Fig.25 , the method for manufacturing the semiconductor structure in the embodiment of the present disclosure further includes:

[0112] A plurality of active pillars 17 and grooves 16 surrounding each active region are formed on the first surface 11 of the substrate 10, wherein the plurality of active pillars 17 are arranged at intervals along the first direction and at intervals along the second direction;

[0113] A plurality of bit lines 70 spaced apart along the first direction are formed on the side of the active pillars 17 away from the first surface 11 of the substrate 10 , and each bit line 70 contacts a plurality of active pillars 17 located in the same column along the second direction.

[0114] Among them, the active pillar 17 can be a cylinder, an elliptical cylinder or a rectangular cylinder, and each active pillar 17 includes a source region, a channel region and a drain region that are stacked. A plurality of active pillars 17 are arranged along the first direction and along the second direction at intervals to form an array. The first direction can be the row direction of the array, and the second direction can be the column direction of the array, that is, the active pillars 17 in the same row are arranged along the first direction, and the active pillars 17 in the same column are arranged along the second direction.

[0115] Each bit line 70 contacts a plurality of active regions in the same column along the second direction. The bit line 70 may be formed by an implantation process on the second surface 12 of the substrate 10, or may be formed by a patterning process on the second surface 12 of the substrate 10, so as to facilitate the manufacture of the bit line 70 and ensure the quality of the bit line 70. The bit line 70 may be located inside the substrate 10, or may be exposed on the second surface 12 of the substrate 10.

[0116] In some possible examples, after forming a plurality of active pillars 17 and grooves 16 surrounding each active region on the first surface 11 of the substrate 10, the method further includes:

[0117] A plurality of isolation layers extending along the first direction and arranged at intervals along the second direction are formed in the groove 16, and each isolation layer is located between two adjacent columns of active pillars 17 along the second direction;

[0118] A plurality of word lines 60 are formed between adjacent isolation layers. The plurality of word lines 60 extend along a first direction, and each word line 60 covers a portion of the outer circumference of a corresponding plurality of active pillars 17 .

[0119] The isolation layer may be an insulating layer, such as a silicon nitride layer or a silicon nitride oxide layer, and the isolation layer separates two adjacent columns of active pillars 17, that is, the multiple active pillars 17 between two adjacent isolation layers are arranged only along the first direction. The isolation layer does not contact the active pillars 17 to leave space for forming the word line 60. The word line 60 extends along the first direction and covers a portion of the outer peripheral surface of the corresponding multiple active pillars 17, such as covering the channel region, so that the word line 60 is used as a gate structure to form a vertical transistor, so as to improve the gate control capability of the transistor and the storage density of the semiconductor structure.

[0120] The present disclosure also provides a semiconductor structure. Figure 3 , Fig.15 , Fig.16 , Fig.24 and Fig.25 The semiconductor structure includes a substrate 10 and a marking layer 50, wherein the substrate 10 has a first surface 11 and a second surface 12, and the first surface 11 and the second surface 12 are arranged opposite to each other along the thickness direction of the substrate 10. For example, the first surface 11 is the front side of the substrate 10, and the second surface 12 is the back side of the substrate 10.

[0121] In some examples, the base 10 may include a substrate 13, a second protective layer 14, and a barrier layer 15 stacked in sequence. The material of the substrate 13 includes silicon, silicon carbide, gallium nitride, germanium, silicon boride, or silicon phosphide, the second protective layer 14 may be an oxide layer, such as silicon oxide, and the barrier layer 15 may be a nitride layer, such as silicon nitride. The surface of the barrier layer 15 facing away from the substrate 13 is the first surface 11, and the surface of the substrate 13 facing away from the second protective layer 14 is the second surface 12.

[0122] A groove 20 is provided on the first surface 11 of the substrate 10. In the example where the substrate 10 includes a substrate 13, a protective layer and a barrier layer 15, the groove 20 penetrates the barrier layer 15 and the second protective layer 14 and extends into the substrate 13, that is, the bottom of the groove 20 is located in the substrate 13, and the substrate 13 is exposed in the groove 20.

[0123] In some examples, the groove 20 includes a plurality of regions, and the plurality of regions are arranged along the first direction, for example, adjacent to each other. Each region includes a first section 21 and a second section 22, and the first section 21 and the second section 22 are arranged along the second direction and are arranged at intervals. The first section 21 includes at least two first channels 23, and the at least two first channels 23 extend along the second direction and are arranged at intervals along the first direction. The second section 22 includes a plurality of second channels 24, and the plurality of second channels 24 extend along the first direction and are arranged at intervals along the second direction.

[0124] like Figure 4As shown, in two adjacent regions, the first channel 23 in one region is adjacent to the plurality of second channels 24 in the other region along the first direction, that is, the positions of the first segment 21 and the second segment 22 in the two adjacent regions are different.

[0125] See also Fig.15 and Fig.16 , the marking layer 50 is located inside the substrate 10 at the bottom of the groove 20, and the marking layer 50 is exposed on the second surface 12 of the substrate 10. By exposing the marking layer 50 on the second surface 12 of the substrate 10, the position of the second surface 12 can be calibrated, thereby controlling the thickness of the substrate 10, avoiding the thickness of the substrate 10 to be too thick or too thin, thereby ensuring that the device structure can be manufactured on the substrate 10, and improving the yield rate of the semiconductor structure.

[0126] In some examples, such as Fig.24 As shown, the marking layer 50 includes a plurality of first layers 51 and a plurality of second layers 52, and the first layers 51 and the second layers 52 are both in strip shape. The plurality of first layers 51 are arranged at intervals along the first direction and are opposite to the first channels 23, that is, the plurality of first layers 51 extend along the second direction and are located below the first channels 23. The plurality of second layers 52 are arranged at intervals along the second direction and are opposite to the plurality of second channels 24, that is, each second layer 52 extends along the first direction and is located below the corresponding second channel 24.

[0127] The material of the marking layer 50 may be oxide, and is formed by injecting predetermined ions (such as oxygen ions) into the substrate 10 and reacting the predetermined ions with the substrate 10. The specific process may refer to the above example, and will not be described in detail here.

[0128] Continue reading Figure 3 and Fig.25 The first surface 11 of the substrate 10 further has a groove 16, and a plurality of active pillars 17 are arranged in the groove 16. The plurality of active pillars 17 are arranged at intervals along the first direction and at intervals along the second direction, that is, the plurality of active pillars 17 are arranged in an array. The active pillars 17 may be cylindrical, elliptical or rectangular.

[0129] The groove 16 is spaced apart from the trench 20, and a plurality of isolation layers are disposed in the groove 16. The plurality of isolation layers extend along the first direction and are spaced apart along the second direction, and an isolation layer is disposed between two adjacent columns of active pillars 17 along the second direction, and the isolation layer is spaced apart from the active pillars 17. The isolation layer may be an insulating layer, such as a silicon nitride layer or a silicon oxynitride layer, and the isolation layer separates two adjacent columns of active pillars 17, that is, the plurality of active pillars 17 between two adjacent isolation layers are only arranged along the first direction.

[0130] A plurality of word lines 60 are disposed between adjacent isolation layers, and the plurality of word lines 60 extend along a first direction, and each word line 60 covers a portion of the outer circumference of a corresponding plurality of active pillars 17. The word lines 60 extend along the first direction and cover a portion of the outer circumference of a corresponding plurality of active pillars 17, such as covering a channel region, so that the word lines 60 are used as a gate structure to form a vertical transistor, so as to improve the gate control capability of the transistor and the storage density of the semiconductor structure.

[0131] Continue reading Fig.25 The semiconductor structure further includes a plurality of bit lines 70 disposed in the substrate 10. The plurality of bit lines 70 are located on the side of the active pillars 17 facing the second surface 12 and are arranged at intervals along the first direction. Each bit line 70 contacts a plurality of active pillars 17 located in the same column along the second direction. The bit lines 70 are buried bit lines, and the bit lines 70 contact the corresponding active pillars 17 to achieve electrical connection with the source region.

[0132] In some examples, the semiconductor structure further includes a data storage unit 80 correspondingly disposed on each active pillar 17, and the data storage unit 80 is located on the top surface of the active region away from the second surface 12 of the substrate 10. The data storage unit 80 is a capacitor, and the bottom surface of the capacitor is in contact with the top surface of the corresponding active pillar 17 to achieve electrical connection with the drain region.

[0133] In summary, the embodiment of the present disclosure provides a semiconductor structure, which includes a substrate 10 and a marking layer 50, wherein the substrate 10 has a first surface 11 and a second surface 12 that are arranged opposite to each other, the first surface 11 is provided with a groove 20, the marking layer 50 is located inside the substrate 10 at the bottom of the groove 20, and the marking layer 50 is exposed on the second surface 12 of the substrate 10. By exposing the marking layer 50 on the second surface 12 of the substrate 10, the position of the second surface 12 can be calibrated, thereby controlling the thickness of the substrate 10, avoiding the thickness of the substrate 10 being too thick or too thin, thereby ensuring that the device structure can be manufactured on the substrate 10, and improving the yield rate of the semiconductor structure.

[0134] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate having a first surface and a second surface disposed opposite to each other; forming a groove on the first surface; Implanting predetermined ions into the substrate at the bottom of the trench to form an implantation region; The predetermined ions react with the substrate to form a marking layer in the implanted area; The second surface is thinned until the marking layer is exposed.

2. The method according to claim 1, characterized in that: The substrate is annealed to allow the preset ions to react with the substrate to form the marking layer.

3. The production method according to claim 1 or 2, characterized in that: Before injecting the preset ions into the substrate at the bottom of the groove, the method further includes: A first protection layer is formed on the sidewall of the trench, and the bottom of the trench covered with the first protection layer exposes the substrate.

4. The method according to claim 3, characterized in that: Forming the first protection layer on the sidewall of the trench includes: forming the first protective layer on the sidewalls and bottom of the trench and the first surface; The first protection layer on the first surface and at the bottom of the trench is removed, the first protection layer on the sidewall of the trench is retained, and the bottom of the trench covered with the first protection layer exposes the substrate.

5. The manufacturing method according to claim 3, characterized in that: After forming the first protective layer on the sidewall of the trench and before injecting the preset ions into the substrate at the bottom of the trench, the method further includes: The substrate is etched along the trench covered with the first protection layer so that the depth of the trench increases.

6. The method according to claim 1 or 2, characterized in that: The step of forming the groove on the first surface comprises: The first surface is etched to form a groove; wherein the groove includes at least two areas arranged along a first direction, each of the areas includes a first section and a second section arranged at intervals along a second direction, the first section includes at least two first channels extending along the second direction and arranged at intervals along the first direction, the second section includes at least two second channels extending along the first direction and arranged at intervals along the second direction, and in two adjacent areas, the first channel is adjacent to the second channel along the first direction.

7. The manufacturing method according to claim 6, characterized in that: Implanting predetermined ions into the substrate at the bottom of the trench comprises: The preset ions are injected into the substrate at the bottom of the first channel and the second channel to form the injection region; wherein the injection region includes a plurality of first partitions arranged at intervals along the first direction, and a plurality of second partitions arranged at intervals along the second direction, the plurality of first partitions are opposite to the plurality of first channels, and the plurality of second partitions are opposite to the plurality of second channels.

8. The manufacturing method according to claim 6, characterized in that: The substrate is provided, wherein the substrate has the first surface and the second surface which are arranged opposite to each other, including: providing a substrate; forming a second protective layer on the substrate, and forming a barrier layer on the second protective layer, wherein a surface of the barrier layer facing away from the substrate is the first surface, and a surface of the substrate facing away from the second protective layer is the second surface; Accordingly, etching the first surface includes: The barrier layer, the second protection layer and the substrate are etched to form the trench, which penetrates the barrier layer and the second protection layer and extends into the substrate.

9. The manufacturing method according to claim 8, characterized in that: The material of the substrate includes silicon, silicon carbide, gallium nitride, germanium, silicon boride or silicon phosphide, the preset ions are oxygen ions, and the marking layer is an oxide layer.

10. The production method according to claim 1 or 2, characterized in that: Thinning the second surface includes: thinning the second surface by a chemical mechanical polishing process until the marking layer is identified.

11. A semiconductor structure, characterized in that: include: A substrate, the substrate having a first surface and a second surface arranged opposite to each other, the first surface being provided with grooves; A marking layer is located inside the substrate at the bottom of the groove, and the marking layer is exposed on the second surface of the substrate.

12. The semiconductor structure according to claim 11, characterized in that: The first surface of the substrate also has a groove, and a plurality of active pillars are arranged in the groove, and the plurality of active pillars are arranged at intervals along the first direction and at intervals along the second direction; The semiconductor structure also includes a plurality of bit lines disposed in the substrate, the plurality of bit lines are located on the side of the active pillars facing the second surface and are arranged at intervals along the first direction, and each of the bit lines contacts a plurality of the active pillars located in the same column along the second direction.

13. The semiconductor structure according to claim 12, characterized in that: The semiconductor structure further includes a plurality of isolation layers disposed in the grooves, the plurality of isolation layers extending along the first direction and arranged at intervals along the second direction, and the isolation layers are disposed between two adjacent columns of the active pillars along the second direction.

14. The semiconductor structure according to claim 13, characterized in that: The semiconductor structure further includes a plurality of word lines disposed between adjacent isolation layers, the plurality of word lines extending along the first direction, and each of the word lines covering a portion of the outer circumference of a corresponding plurality of active pillars.

15. The semiconductor structure according to any one of claims 12 to 14, characterized in that: The semiconductor structure further includes a data storage unit correspondingly disposed on each of the active pillars, wherein the data storage unit is located on a top surface of the active region away from the second surface of the substrate.

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