Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a sacrificial layer on the substrate, wherein the thickness of the sacrificial layer ranges from 500 angstroms to 5000 angstroms; forming a photoresist layer with a shallow trench isolation structure pattern on the sacrificial layer; sequentially etching the sacrificial layer and the substrate by taking the photoresist layer as a mask, and forming shallow trenches in the sacrificial layer and the substrate; filling the shallow trench with an insulating material; and etching to remove the sacrificial layer and a part of the insulating material until the surface of the substrate is exposed to form a shallow trench isolation structure. A sacrificial layer is formed on a substrate, the sacrificial layer and the substrate are etched to form a shallow trench, the height of the shallow trench is increased, a cavity is formed in the top of the shallow trench, a shallow trench isolation structure with the cavity at the top of the shallow trench is removed through etching subsequently, the integrity of the shallow trench isolation structure is guaranteed, and the shallow trench isolation structure is formed. And the yield, the reliability and the performance of the semiconductor device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In semiconductor manufacturing processes, shallow trench isolation (STI) is formed by depositing, patterning, and etching silicon using a silicon nitride mask, and then filling the trench with deposited oxide for isolation from silicon.

[0003] However, the existing shallow trench isolation is prone to premature sealing during the filling process, which in turn causes voids, resulting in low yield and low reliability for semiconductor devices, and reduces the performance of semiconductor devices. Summary of the invention

[0004] The technical problem solved by the present invention is how to solve the problem of reduced yield, reliability and performance of semiconductor devices.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a sacrificial layer on the substrate, wherein the thickness of the sacrificial layer is in the range of 500 angstroms to 5000 angstroms; forming a photoresist layer having a shallow trench isolation structure pattern on the sacrificial layer; using the photoresist layer as a mask, sequentially etching the sacrificial layer and the substrate to form shallow trenches in the sacrificial layer and in the substrate; filling the shallow trenches with insulating material; etching and removing the sacrificial layer and part of the insulating material until the surface of the substrate is exposed to form a shallow trench isolation structure.

[0006] Optionally, the process for forming the sacrificial layer is: a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: a deposition rate of 2000 angstroms to 3000 angstroms per minute, and a deposition time of 3 seconds to 10 seconds; a deposition rate of 400 angstroms to 600 angstroms per minute, and a deposition time of 5 seconds to 10 seconds.

[0007] Optionally, the density range of the sacrificial layer is 3.24 g / cm 3 Up to 3.26g / cm 3 The stress range of the sacrificial layer is 100MPa to 500MPa, and the thermal expansion coefficient of the sacrificial layer is 2.8*10 -6 / ℃ to 3.1*10 -6 / °C, and the thickness of the sacrificial layer ranges from 500 angstroms to 5000 angstroms.

[0008] Optionally, the material of the sacrificial layer is a combination of one or more of silicon oxide, APF film, silicon nitride and tetraethyl orthosilicate oxide.

[0009] Optionally, the process for forming a shallow trench isolation structure in the shallow trench is: a high-density plasma chemical vapor deposition process, and the parameters of the high-density plasma chemical vapor deposition process are a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute and a deposition time of 3 seconds to 10 seconds.

[0010] Optionally, before the step of forming a sacrificial layer on the substrate, the method further includes: forming an etch stop layer on the substrate.

[0011] Optionally, the etch stop layer is a single layer or a plurality of layers stacked together, and the material of the etch stop layer is a combination of one or more of silicon nitride, silicon oxide, and carbon-rich silicon nitride.

[0012] Optionally, the step of forming a shallow groove includes: using the photoresist layer as a mask, etching the sacrificial layer and etching the stop layer until the substrate surface is exposed to form a first shallow groove; continuing to use the photoresist layer as a mask to etch the substrate to form a shallow groove.

[0013] Optionally, the process of etching the sacrificial layer, the etch stop layer and the substrate is a dry etching process, and the process parameters for etching the sacrificial layer and the etch stop layer are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, and the etching pressure is 10mTor. r to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds.

[0014] Optionally, the step of etching away the sacrificial layer and a portion of the insulating material includes: etching away the sacrificial layer and a portion of the insulating material until the etch stop layer is exposed; etching away the etch stop layer until the substrate surface is exposed.

[0015] Optionally, the process of etching away the sacrificial layer and part of the insulating material is a combination of one or both of a dry etching process and a planarization process, and the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0017] The present invention forms a sacrificial layer on the substrate, and etches the sacrificial layer and the substrate to form a shallow groove, thereby increasing the height of the shallow groove, so that in the subsequent process of depositing a shallow trench isolation structure in the shallow groove, the contact area of ​​the deposition is increased, and a shallow trench isolation structure with good morphology is formed. In the process of depositing the shallow trench isolation structure, since the speed at which the filling gas reaches the bottom of the shallow trench is slow, that is, the filling rate of the bottom of the shallow trench is slow, and the filling of the top of the shallow trench is faster than that of the bottom of the shallow trench, it is easier to seal in advance to form a filled cavity, so that the cavity is formed at the top of the shallow trench, and the shallow trench isolation structure with the cavity at the top of the shallow trench is subsequently removed by etching, thereby ensuring the integrity of the shallow trench isolation structure, thereby improving the yield, reliability and performance of the semiconductor device.

[0018] Furthermore, the present invention forms an etch stop layer on the substrate, so that when the sacrificial layer and part of the shallow trench isolation structure are subsequently etched, the substrate is prevented from being damaged by etching, thereby ensuring the integrity of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 3 is a schematic diagram of a process for forming a semiconductor structure in one embodiment;

[0020] Figures 4 to 10 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention;

[0021] Fig.11 Schematic diagram of wafer scanning of a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0022] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0023] Figures 1 to 3 is a schematic diagram of a process of forming a semiconductor structure in one embodiment.

[0024] For the current memory process flow, please refer to Figures 1 to 3 , Figure 1 is a top view of the memory, Figure 2 yes Figure 1 Cross-sectional view along AA1 direction, Figure 3 yes Figure 1 In the cross-sectional view along the BB1 ​​direction, due to process requirements, the active area 101 of the memory 100 needs to be made into a grid shape, shallow trenches (not shown in the figure) are formed between adjacent active areas 101, and the shallow trenches are filled to form an isolation structure 102. However, when forming the isolation structure 102, when filling the shallow trench in the middle part between adjacent active areas 101, it is easier to form a filling void 103 (Void) than when filling the shallow trench at both end parts between adjacent active areas 101. These voids will bring low yield and low reliability to the product, causing adjacent storage units to interfere with each other during operation, resulting in product failure.

[0025] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, wherein the sacrificial layer is formed on the substrate to increase the height of the shallow trench formed subsequently, and then in the process of depositing a shallow trench isolation structure in the shallow trench, the contact area of ​​the shallow trench surface is increased to form a shallow trench isolation structure with good morphology, and the cavity is formed at the top of the shallow trench, and the shallow trench isolation structure with the cavity at the top of the shallow trench is subsequently removed by etching to ensure the integrity of the shallow trench isolation structure, thereby improving the yield, reliability and performance of semiconductor devices.

[0026] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figures 4 to 10 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention.

[0028] Please refer to Figure 4 , providing a substrate 200.

[0029] In this embodiment, the material of the substrate 200 is silicon.

[0030] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0031] Please refer to Figure 5 , a sacrificial layer 203 is formed on the substrate 200 .

[0032] The process for forming the sacrificial layer 203 is: chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: deposition rate of 2000 angstroms per minute to 3000 angstroms per minute, deposition time of 3 seconds to 10 seconds; deposition rate of 400 angstroms per minute to 600 angstroms per minute, deposition time of 5 seconds to 10 seconds.

[0033] In this embodiment, the density range of the sacrificial layer 203 is 3.24 g / cm 3 Up to 3.26g / cm 3 The stress range of the sacrificial layer 203 is 100 MPa to 500 MPa, and the thermal expansion coefficient range of the sacrificial layer 203 is 2.8*10 -6 / ℃ to 3.1*10 -6 / °C, the thickness of the sacrificial layer 203 ranges from 500 angstroms to 5000 angstroms.

[0034] Specifically, the thickness of the sacrificial layer 203 is 800 angstroms, 1000 angstroms or 2000 angstroms.

[0035] In this embodiment, the thickness of the sacrificial layer 203 is selected through testing. Specifically, a group of experiments are conducted on the thickness of the sacrificial layer 203 with different thicknesses. Subsequently, the number of voids at different thicknesses of the sacrificial layer 203 is counted through the fixed-point shooting API method to determine the optimal thickness. For example, at a sacrificial layer thickness of 800 angstroms, the number of voids is the least, that is, a sacrificial layer of 800 angstroms is the optimal thickness.

[0036] In some embodiments, the material of the sacrificial layer 203 is a combination of one or more of silicon oxide, APF film, silicon nitride and tetraethyl orthosilicate oxide.

[0037] As can be seen from the above, the density of the sacrificial layer 203 is relatively low, so that the sacrificial layer 203 is easy to be removed later; the sacrificial layer 203 has a high thermal expansion coefficient and low stress, that is, it is a material with good thermal stability and high-temperature performance. Therefore, it can maintain structural stability in a high-temperature environment and avoid warping, deformation or even fragmentation of the wafer, thereby ensuring the integrity of the wafer.

[0038] Due to the increase in the thickness of the sacrificial layer 203, the depth of the shallow trench 207 formed subsequently increases, so that in the subsequent process of depositing the shallow trench isolation structure 2081 in the shallow trench 207, the contact area of ​​the deposition is increased, and a shallow trench isolation structure with good morphology is formed. In the process of depositing the shallow trench isolation structure, since the filling gas reaches the bottom of the shallow trench 207 slowly, that is, the filling rate at the bottom of the shallow trench 207 is slow, and the filling of the top of the shallow trench 207 is faster than the bottom of the shallow trench 207, it is easier to seal in advance to form a filled void 209, so that the void 209 is formed at the top of the shallow trench 207, and the shallow trench isolation structure with the void 209 at the top of the shallow trench 207 is subsequently removed by etching to ensure the integrity of the shallow trench isolation structure, thereby improving the yield, reliability and performance of semiconductor devices.

[0039] In this embodiment, before forming the sacrificial layer 203 , the process further includes: forming a protection layer 201 on the substrate 200 ; and forming an etching stop layer 202 on the surface of the protection layer 201 .

[0040] In this embodiment, the material of the protection layer 201 is silicon oxide or silicon oxynitride.

[0041] In this embodiment, the thickness of the etch stop layer 202 is in a range of 30 angstroms to 50 angstroms.

[0042] In some embodiments, the etch stop layer 202 is a single layer or a stack of multiple layers.

[0043] When the etch stop layer 202 is a single layer, the material of the etch stop layer 202 is silicon nitride.

[0044] When the etch stop layer 202 is a multi-layer stack, the material of the etch stop layer 202 is a combination of one or more of silicon nitride, silicon oxide, and carbon-rich silicon nitride.

[0045] The etch stop layer 202 is used to protect the substrate 200 from being damaged during the subsequent removal of the sacrificial layer 203 .

[0046] It can be seen that the present invention forms an etch stop layer 202 on the substrate 200 to avoid etching damage to the substrate 200 during the subsequent etching of the sacrificial layer 203 and part of the shallow trench isolation structure, thereby ensuring the integrity of the substrate 200.

[0047] Please refer to Figure 6 , a photoresist layer 205 having an isolation structure pattern is formed on the sacrificial layer 203 .

[0048] In this embodiment, before forming the photoresist layer 205, it also includes: forming a hard mask layer 204 on the surface of the sacrificial layer 203; forming an initial photoresist layer (not shown in the figure) on the anti-reflective layer; exposing and developing the initial photoresist layer until the hard mask layer 204 is exposed to form the photoresist layer 205.

[0049] In this embodiment, the material of the hard mask layer 204 includes: one or more combinations of TiN, SiN, and SiO 2 .

[0050] In this embodiment, after the photoresist layer 205 is formed, the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202 and the protective layer 201 are etched in sequence using the photoresist layer 205 as a mask until the surface of the substrate 200 is exposed to form a first shallow groove 206.

[0051] In this embodiment, the process of etching the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202 and the protective layer 201 is a dry etching process, and the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds.

[0052] Please refer to Figure 7 , using the photoresist layer 205 as a mask, the substrate 200 is continuously etched to form a shallow trench 207 .

[0053] In this embodiment, an insulating layer 210 is formed on the surface of the substrate 200 in the shallow trench 207 and on the surface of the protection layer 201 .

[0054] The process for forming the insulating layer 210 is high temperature furnace tube annealing, and the process parameters of the high temperature furnace tube annealing are: annealing temperature is 1015 degrees Celsius, and annealing time is 18 seconds.

[0055] In this embodiment, the process of etching the substrate 200 is a dry etching process, and the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds.

[0056] In the above scheme, since the etching rates of the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202 and the protective layer 201 are close, and the etching selectivity ratio of the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202 and the protective layer 201 to the substrate 200 is 3:1, the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202 and the protective layer 201 and the substrate 200 cannot accurately control the depth of the shallow groove 207 under the same etching process parameters. Therefore, the present invention forms the shallow groove 207 by etching twice. Specifically, the first etching removes the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202 and the protective layer 201, and the second etching removes part of the substrate 200, so that the depth of the shallow groove 207 can be accurately controlled.

[0057] Please refer to Figure 8 , the shallow trench 207 is filled with insulating material to form an initial shallow trench isolation structure 208.

[0058] In this embodiment, the material of the initial shallow trench isolation structure 208 is silicon oxide.

[0059] Before filling the insulating material, the method further includes: removing the photoresist layer 205 and the hard mask layer 204 until the surface of the sacrificial layer 203 is exposed.

[0060] In this embodiment, during the process of filling the shallow trench 207 with the insulating material, a cavity 209 appears in the insulating material at the top of the shallow trench 207 .

[0061] The process for filling the shallow trench 207 with insulating material is a high-density plasma chemical vapor deposition process, and the parameters of the high-density plasma chemical vapor deposition process are a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute and a deposition time of 3 seconds to 10 seconds.

[0062] In the above scheme, since the void 209 appears in the sacrificial layer 203 at the top of the shallow trench 207, the void 209 is also removed in the subsequent process of removing the sacrificial layer 203, thereby ensuring that the shallow trench isolation structure 2081 at the bottom of the shallow trench 207 is relatively dense, avoiding the appearance of the void 209, ensuring the integrity of the shallow trench isolation structure 2081, and thus improving the yield, reliability and performance of semiconductor devices.

[0063] Please refer to Fig. 9 , the sacrificial layer 203 and part of the insulating material are etched away until the surface of the etch stop layer 202 is exposed, forming a shallow trench isolation structure 2081.

[0064] The thickness of the shallow trench isolation structure 2081 ranges from 2000 angstroms to 4000 angstroms, and the height of the shallow trench isolation structure 2081 above the surface of the substrate 200 ranges from 0 angstroms to 80 angstroms.

[0065] In this embodiment, the process of etching away the sacrificial layer 203 and part of the insulating material is a combination of one or both of a dry etching process and a planarization process. The process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds.

[0066] In this embodiment, the planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.

[0067] During the planarization process, the grinding rate ratio of the grinding liquid to the shallow trench isolation structure 2081 and the etching stop layer 202 is 2:1, that is, the grinding rate of the shallow trench isolation structure 2081 is greater than the grinding rate of the etching stop layer 202, and the following occurs: Fig. 9 In the figure, the top of the shallow trench isolation structure 2081 is lower than the top of the etch stop layer 202.

[0068] Please refer to Fig.10 , the etch stop layer 202 is removed by etching until the surface of the protection layer 201 is exposed.

[0069] In this embodiment, the process of etching and removing the etch stop layer 202 is a dry etching process, and the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds.

[0070] Fig.11Schematic diagram of wafer scanning of a semiconductor structure in one embodiment of the present invention.

[0071] Depend on Fig.11 It can be seen that the shallow trench isolation structure 2081 is formed by adopting the above solution. After scanning the wafer, it is found that only one cavity 209 appears on the wafer, which reduces the possibility of the formation of the cavity 209.

[0072] In summary, the present invention forms a sacrificial layer 203 on the substrate 200, and etches the sacrificial layer 203 and the substrate 200 to form a shallow trench 207, thereby increasing the height of the shallow trench 207, so that in the subsequent process of depositing a shallow trench isolation structure 2081 in the shallow trench 207, the contact area of ​​the deposition is increased, and a shallow trench isolation structure 2081 with good morphology is formed. In addition, in the process of depositing the shallow trench isolation structure 2081, since the filling gas reaches the shallow trench 20 The filling speed at the bottom of the shallow trench 207 is slow, that is, the filling rate at the bottom of the shallow trench 207 is slow, while the filling rate at the top of the shallow trench 207 is faster than that at the bottom of the shallow trench 207, so that it is easier to seal in advance to form a filled cavity 209, so that the cavity 209 is formed at the top of the shallow trench 207, and then the shallow trench isolation structure 2081 with the cavity 209 at the top of the shallow trench 207 is removed by etching to ensure the integrity of the shallow trench isolation structure 2081, thereby improving the yield, reliability and performance of the semiconductor device.

[0073] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a sacrificial layer on the substrate, wherein the thickness of the sacrificial layer ranges from 500 angstroms to 5000 angstroms; forming a photoresist layer having a shallow trench isolation structure pattern on the sacrificial layer; Using the photoresist layer as a mask, sequentially etching the sacrificial layer and the substrate to form shallow trenches in the sacrificial layer and the substrate; Filling the shallow trench with insulating material; The sacrificial layer and a portion of the insulating material are removed by etching until the surface of the substrate is exposed, thereby forming a shallow trench isolation structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming the sacrificial layer is: chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: deposition rate of 2000 angstroms to 3000 angstroms per minute, and deposition time of 3 seconds to 10 seconds; deposition rate of 400 angstroms to 600 angstroms per minute, and deposition time of 5 seconds to 10 seconds.

3. The method for forming a semiconductor structure according to claim 2, wherein: The density range of the sacrificial layer is 3.24 g / cm 3 Up to 3.26g / cm 3 The stress range of the sacrificial layer is 100MPa to 500MPa, and the thermal expansion coefficient of the sacrificial layer is 2.8*10 -6 / ℃ to 3.1*10 -6 / °C, and the thickness of the sacrificial layer ranges from 500 angstroms to 5000 angstroms.

4. The method for forming a semiconductor structure according to claim 2, wherein: The material of the sacrificial layer is a combination of one or more of silicon oxide, APF film, silicon nitride and tetraethyl orthosilicate oxide.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming the shallow trench isolation structure in the shallow trench is: a high-density plasma chemical vapor deposition process, and the parameters of the high-density plasma chemical vapor deposition process are: a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute, and a deposition time of 3 seconds to 10 seconds.

6. The method for forming a semiconductor structure according to claim 1, wherein: Before the step of forming a sacrificial layer on the substrate, the method further includes: forming an etch stop layer on the substrate.

7. The method for forming a semiconductor structure according to claim 1, wherein: The etch stop layer is a single layer or a stack of multiple layers, and the material of the etch stop layer is a combination of one or more of silicon nitride, silicon oxide, and carbon-rich silicon nitride.

8. The method for forming a semiconductor structure according to claim 6, wherein: The steps of forming the shallow trench include: Using the photoresist layer as a mask, etching the sacrificial layer and the etching stop layer until the substrate surface is exposed to form a first shallow trench; The substrate is continuously etched using the photoresist layer as a mask to form a shallow trench.

9. The method for forming a semiconductor structure according to claim 7, wherein: The process for etching the sacrificial layer, the etch stop layer and the substrate is a dry etching process, and the process parameters for etching the sacrificial layer and the etch stop layer are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate are that the chamber pressure is 5mT to 15mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

10. The method for forming a semiconductor structure according to claim 7, wherein: The step of etching away the sacrificial layer and part of the insulating material comprises: Etching and removing the sacrificial layer and a portion of the insulating material until the etch stop layer is exposed; The etch stop layer is removed by etching until the substrate surface is exposed.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process of etching away the sacrificial layer and part of the insulating material is a combination of one or both of a dry etching process and a planarization process. The process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds.

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