Chip packaging structural member and manufacturing method
The chip packaging structure with a strip substrate and heat sink, packaged by injection molding, addresses the lack of heat sinks in chip-level packaging, enhancing heat dissipation and reducing production costs through efficient manufacturing processes.
Patent Information
- Application Number
- CN202310644163.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-05-31
- Publication Date
- 2024-12-10
AI Technical Summary
Chip-level packaging lacks heat sinks, and existing heat sinks for strip substrates require single-chip customization, leading to high production costs.
A chip packaging structure comprising a strip substrate with multiple chips and a strip heat sink, packaged by injection molding, which includes pre-cutting and etching to improve heat dissipation and reduce customization costs.
The structure achieves effective heat dissipation and reduces production costs by eliminating the need for single-chip customized heat sinks, while improving product quality and efficiency.
Smart Images
Figure CN119108359A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of integrated circuit packaging, and in particular, to a chip packaging structure and a manufacturing method thereof. Background Art
[0002] Storage chips have higher requirements for heat dissipation due to their fast reading and writing speeds, diversified functions, and complex structures. Therefore, timely dissipation of chip heat, increased transmission speed, reduced error rate, and extended chip life are current research hotspots.
[0003] In the prior art, the packaging forms using heat sinks are mostly ball grid array packaging structures (BGA) or land grid array packaging structures (LGA). This packaging type uses a single block substrate, and the types of heat sinks on the market are also designed for this single substrate. Figure 1 It is a schematic diagram of the packaging process of the ball grid array packaging structure in the related technology, such as Figure 1 As shown, when attaching the heat sink cover, it needs to be attached to the wafer and substrate through thermal conductive glue (Thermal Interface Material, TIM) and adhesive. Figure 2 It is a schematic diagram of the packaging process of the chip-level packaging structure in the related technology, such as Figure 2 As shown, the chip scale package (CSP) packaging type uses a strip substrate, and currently no heat sink is used.
[0004] Since most chips suitable for strip substrates are small-sized chips, they do not require much heat dissipation. However, with the development of chip heat dissipation requirements and the optimization of traditional processes, it is very necessary to introduce heat sinks in chip-level packaging. However, heat sinks with BGA structures are not suitable for strip substrates, and the shape design of heat sinks requires single-chip customization, which increases production costs. Summary of the invention
[0005] The embodiments of the present invention provide a chip packaging structure and a manufacturing method to at least solve the problem in the related art that the chip-level packaging has no heat sink and the existing heat sink has a high cost for single customization.
[0006] According to one embodiment of the present invention, there is provided a chip packaging structure, comprising: a strip substrate, a plurality of chips, and a strip heat sink, wherein the strip substrate comprises a plurality of unit substrates arranged in sequence along an extension direction of the strip substrate, each of the unit substrates is provided with one chip of the plurality of chips, the strip heat sink is provided on the strip substrate along an arrangement direction of the plurality of chips, and the strip heat sink, the plurality of chips and the strip substrate are packaged by injection molding.
[0007] According to another embodiment of the present invention, a method for manufacturing a chip packaging structure is provided, comprising: mounting a plurality of chips on each unit substrate of the strip substrate in sequence along an extension direction of the strip substrate, wherein one chip of the plurality of chips is mounted on each unit substrate; placing a strip heat sink on the strip substrate along an arrangement direction of the plurality of chips, and encapsulating the strip heat sink, the plurality of chips and the strip substrate by injection molding to obtain a chip packaging structure.
[0008] The present invention provides a chip packaging structure, including: a strip substrate, a plurality of chips, and a strip heat sink, wherein the strip substrate includes a plurality of unit substrates arranged in sequence along the extension direction of the strip substrate, each unit substrate is provided with one of the plurality of chips, the strip heat sink is arranged on the strip substrate along the arrangement direction of the plurality of chips, and the strip heat sink, the plurality of chips and the strip substrate are packaged by injection molding. The problem that the chip-level packaging in the related art has no heat sink and the existing heat sink has a high single-piece customization cost is solved, and the effect of good heat dissipation of the chip-level packaging structure and controlling the packaging cost is achieved. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 It is a schematic diagram of the packaging process of a ball grid array packaging structure in the related art;
[0010] Figure 2 It is a schematic diagram of the packaging process of a chip-level packaging structure in the related art;
[0011] Figure 3 is a schematic diagram of a chip packaging structure according to an embodiment of the present invention;
[0012] Figure 4 is a schematic flow chart of a method for manufacturing a chip packaging structure according to an embodiment of the present invention;
[0013] Figure 5 is a schematic structural diagram of a chip packaging structure according to a scenario embodiment of the present invention;
[0014] Figure 6 It is a process schematic diagram of a method for manufacturing a chip packaging structure according to a scenario embodiment of the present invention. DETAILED DESCRIPTION
[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.
[0016] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0017] In this embodiment, a chip packaging structure is provided. Figure 3 is a schematic diagram of a chip packaging structure according to an embodiment of the present invention. Figure 3 As shown, the chip packaging structure 30 includes: a strip substrate 310, a plurality of chips 320, and a strip heat sink 330, wherein the strip substrate 310 includes a plurality of unit substrates arranged in sequence along the extension direction of the strip substrate 310, each unit substrate is provided with one chip of the plurality of chips 320, the strip heat sink 330 is provided on the strip substrate 310 along the arrangement direction of the plurality of chips 3202, and the strip heat sink 330, the plurality of chips 320 and the strip substrate 310 are packaged by injection molding.
[0018] In an exemplary embodiment, the strip heat sink 330 is spaced from the multiple chips 320 by a predetermined distance. Specifically, in the actual implementation process, the predetermined distance between the strip heat sink 330 and the multiple chips 320 can be determined according to actual needs. If the heat dissipation requirement is not high, the predetermined distance can be greater than 0, so that the plastic packaging material is in contact with the strip heat sink 330. If the heat dissipation requirement is relatively high, the predetermined distance can be 0, that is, the strip heat sink 330 is in direct contact with the multiple chips 320 to achieve a better heat dissipation effect. Among them, there is no clear range for defining high and low heat dissipation requirements, which needs to be determined according to actual conditions and is not limited here.
[0019] In an exemplary embodiment, the strip-shaped heat sink 330 is in contact with the surfaces of the plurality of chips 320. That is, the strip-shaped heat sink 330 is in direct contact with the plurality of chips 320 to achieve a better heat dissipation effect.
[0020] In an exemplary embodiment, a metal protective layer is provided on the surface of the strip heat sink 330. In an exemplary embodiment, the metal protective layer is a nickel-chromium alloy plating layer. Specifically, the presence or absence of the metal protective layer and the material type of the metal protective layer can be determined according to actual conditions, and no specific restrictions are made here.
[0021] The embodiment of the present invention also provides a packaging method for a chip packaging structure. Figure 4 FIG. 1 is a flow chart of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. Figure 4 As shown, the following process is included:
[0022] Step S402, mounting a plurality of chips on each unit substrate of the strip substrate in sequence along the extension direction of the strip substrate, wherein each unit substrate is mounted with one chip among the plurality of chips;
[0023] Step S404: placing a strip heat sink on the strip substrate along the arrangement direction of the multiple chips, and encapsulating the strip heat sink, the multiple chips and the strip substrate by injection molding to obtain a chip packaging structure.
[0024] In an exemplary embodiment, after obtaining the chip packaging structure, it also includes: on the front side of the strip substrate, pre-cutting the strip heat sink of the chip packaging structure in a manner of dividing each unit substrate to cut a predetermined depth on the strip heat sink; and cutting on the back side of the strip substrate at a corresponding position of the pre-cutting to obtain multiple single chip packaging products.
[0025] In the actual implementation process, the front side pre-cutting and etching are introduced in the cutting process, and then the secondary cutting is completed from the substrate surface. Compared with the traditional CSP product cutting process that directly cuts from the substrate surface with one knife, the cutting method of the embodiment of the present invention can make the cutting surface smoother.
[0026] In an exemplary embodiment, after pre-cutting the strip heat sink of the chip packaging structure, the method further includes: micro-etching the pre-cut chip packaging structure to remove cutting burrs.
[0027] In an exemplary embodiment, before the back side of the strip substrate and the corresponding position of the pre-cut are cut, a photo mask is attached to the back side of the strip substrate, and after the cutting is completed, the photo mask of the chip packaging product is removed.
[0028] In an exemplary embodiment, before placing the strip heat sink on the strip substrate along the arrangement direction of the plurality of chips, the method further includes: coating the surface of the strip heat sink with a metal protective layer, wherein the metal protective layer is a nickel-chromium alloy coating. In the actual implementation process, the metal material of the metal protective layer can be set according to the actual situation, and is not limited here. By using the metal protective layer, the use effect of the heat sink can be extended and better heat dissipation performance can be obtained.
[0029] In order to enable those skilled in the art to better understand the technical solution of the present invention, it is described below in conjunction with specific scenario embodiments.
[0030] Scenario Example 1
[0031] Figure 5 is a schematic diagram of the structure of a chip packaging structure according to an embodiment of the present invention, such as Figure 5 As shown in (a) of FIG. 1 , the chip packaging structure includes: a substrate 1, a chip 2, a plastic packaging material 3, and a heat sink 4. The substrate 1 can be a strip-shaped substrate as described in the above embodiment, and the heat sink 4 can be a strip-shaped heat sink as described in the above embodiment. In different implementations, the specific shapes can be adjusted according to actual conditions. Figure 5As shown in (a), before the substrate 1 is cut, the upper layer is a storage chip 2. The wafer bumps and the substrate pads are reflowed by flip-chip mounting to achieve electrical connection. The upper layer of the chip 2 is a heat sink 4. The substrate 1, the chip 2 and the heat sink 4 are injection-molded with a plastic packaging material 3 to obtain a chip packaging structure. After the chip packaging structure is cut, it can be obtained. Figure 5 The single chip package product shown in (b) is shown in FIG.
[0032] like Figure 5 As shown in (a), the substrate 1 is a strip substrate, which includes a plurality of unit substrates. A plurality of chips 2 are arranged on the substrate 1, the same number as the unit substrates. The heat sink 4 is a strip heat sink, and the heat sink 4 is encapsulated with the chip 2 and the substrate 1 by a special plastic encapsulation machine with a plastic encapsulation material 3 to complete the structural connection. The heat sink 4 needs to be processed by a special stamping die and plated with a protective layer (Ni+Cr) before use. Figure 5 As shown in (a) in FIG. 1 , the substrate 1, the chip 2 and the heat sink 4 are parallel to each other. Figure 5 As shown in (b), after the strip substrate 1 is cut, a single chip package product can be seen in the cross section of the finished product.
[0033] Figure 6 is a schematic diagram of a process of manufacturing a chip packaging structure according to an embodiment of the present invention. Figure 6 As shown, the following steps are included:
[0034] Step (1) After the wafer surface is convex, the quantity is checked, the back is thinned (depending on the actual situation, it can be omitted if not necessary), and the wafer is cut into multiple single chips 2. The chip 2 is visually inspected for damage.
[0035] Step (2) prepares a strip-shaped substrate 1, which includes a plurality of unit substrates.
[0036] Step (3) Dip the chip 2 into the solder, and place the bump surface of the chip 2 on the center solder of the substrate 1. Check for deviation. If there is no abnormality, put it into the furnace for reflow soldering. After soldering, clean the excess solder with pure water and weak alkaline water. Put it in a 145-155℃ oven for pre-baking for 2-3 hours, then perform plasma cleaning and check the hydrophilic angle.
[0037] Step (4) After the sample is qualified, glue is dispensed multiple times to fill the gap between the chip 2 and the substrate 1, strengthen the connection and alleviate related problems caused by the different thermal expansion coefficients between the chip 2 and the substrate 1, and place it in an oven at ~160-170°C for ~1-2 hours.
[0038] Step (5) After curing, plasma cleaning is performed to remove impurities on the surface of the substrate 1 and the chip 2, roughen the surface, and enhance the bonding with the plastic packaging material. Prepare a heat sink 4 with a Ni / Cr coating, place the heat sink 4 above the substrate 1, and inject the plastic packaging material 3 between the heat sink 4 and the substrate 1 through a special plastic packaging machine. If the heat dissipation is high, the distance between the heat sink and the wafer needs to be controlled, the wafer is exposed, and is tightly connected to the heat sink, such as Figure 6 The second method of step (5) in the above method is as follows. After plastic sealing, the product is placed in a temperature box at 170-180°C for curing for 2-4 hours to stabilize the structure and release internal stress. After plastic sealing, the thickness and warpage are controlled.
[0039] Step (6) The package is screen printed and ball implanted.
[0040] Step (7) A photomask is attached to the bottom of the substrate 1, and pre-cutting is performed from one side of the heat sink 4. After cutting, the product is micro-etched to 10um to remove the cutting burrs. After completion, cutting is performed from the back side of the substrate 1 to divide the product into individual pieces and remove the film.
[0041] In summary, the present invention provides a chip packaging structure and a manufacturing method, which is suitable for a heat sink packaging structure and industrial production process of a strip substrate. Its structure is that the substrate and the chip are electrically connected by wire bonding or flip-chip core mounting. Based on the injection molding process, the substrate, chip and heat sink are laminated with a plastic molding material to form a three-layer structure of heat sink, chip and substrate from top to bottom. Taking flip-chip packaging as an example, its manufacturing method includes flip-chip core mounting, heat sink protective layer plating, injection molding, silk screen printing, ball planting, pre-cutting, etching, secondary cutting and post-baking, which achieves heat dissipation while optimizing the production process and improving product quality. Among them, the packaging structure suitable for storage chips uses a strip heat sink to dissipate heat, reducing the high bit error rate and short chip life caused by heat; the heat sink packaging structure suitable for strip substrates is different from the existing single substrate, and the shape of the heat sink does not need to be customized for a single chip, which reduces production costs and improves production efficiency; the heat sink packaging manufacturing method based on the injection molding process improves the defects caused by cutting in the plastic packaging, and is also applicable when the chip substrate size is changed.
[0042] The packaging structure and manufacturing process of the present invention are also applicable to the packaging with heat sinks for strip substrates and storage chips when the size of the chip substrate changes. The chip packaging structure provided by the present invention has the following structure: on the one hand, a heat sink is added to provide a heat dissipation channel to ensure the service life of the CSP product and reduce failures; on the other hand, the structure is simple and does not require a single customized design, which reduces processing costs; in terms of process: the traditional CSP product cutting process directly cuts from the substrate surface with one knife, while the present invention introduces front pre-cutting and etching during cutting, and then completes secondary cutting from the substrate surface. Traditional cutting has obvious burrs, while the present invention makes the product cutting surface smoother.
[0043] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A chip packaging structure, characterized in that: include: A strip substrate, a plurality of chips, and a strip heat sink, wherein the strip substrate comprises a plurality of unit substrates arranged in sequence along the extension direction of the strip substrate, each of the unit substrates is provided with one chip of the plurality of chips, the strip heat sink is provided on the strip substrate along the arrangement direction of the plurality of chips, and the strip heat sink, the plurality of chips and the strip substrate are packaged by injection molding.
2. The structural member according to claim 1, characterized in that: in, The strip heat sink is spaced a predetermined distance from the plurality of chips.
3. The structural member according to claim 1, characterized in that: in, The strip heat sink is in contact with surfaces of the plurality of chips.
4. The structural member according to claim 1, characterized in that: in, A metal protective layer is provided on the surface of the strip-shaped heat sink.
5. The structural member according to claim 4, characterized in that: in, The metal protective layer is a nickel-chromium alloy plating layer.
6. A method for manufacturing a chip packaging structure, characterized in that: include: Mounting a plurality of chips on each unit substrate of the strip substrate in sequence along the extension direction of the strip substrate, wherein one chip among the plurality of chips is mounted on each unit substrate; The strip heat sink is placed on the strip substrate along the arrangement direction of the multiple chips, and the strip heat sink, the multiple chips and the strip substrate are packaged by injection molding to obtain a chip packaging structure.
7. The method according to claim 6, characterized in that Also includes: On the front side of the strip substrate, pre-cutting the strip heat sink of the chip packaging structure in a manner of dividing each unit substrate, so as to cut a predetermined depth on the strip heat sink; Cutting is performed on the back side of the strip substrate at positions corresponding to the pre-cutting to obtain a plurality of single chip packaging products.
8. The method according to claim 7, characterized in that After pre-cutting the strip heat sink of the chip packaging structure, the method further includes: The pre-cut chip packaging structure is micro-etched to remove cutting burrs.
9. The method according to claim 7, characterized in that: Also includes: Before cutting the back side of the strip substrate and the corresponding position of the pre-cutting, a photo mask is attached to the back side of the strip substrate, and after the cutting is completed, the photo mask of the chip packaging product is removed.
10. The method according to claim 6, characterized in that Before placing the strip-shaped heat sink on the strip-shaped substrate along the arrangement direction of the plurality of chips, the method further includes: A metal protective layer is plated on the surface of the strip-shaped heat sink, wherein the metal protective layer is a nickel-chromium alloy plating layer.