Anti-fuse device using ferroelectric characteristics

Abstract

An anti-fuse device utilizing ferroelectric characteristics includes an active region including a source region, a drain region laterally spaced apart from the source region, and a channel located between the source region and the drain region, and a gate structure disposed between the source region and the drain region. The gate structure includes a ferroelectric layer formed on the channel and a gate electrode formed on the ferroelectric layer. A programming operation of the anti-fuse device is performed by applying a voltage to the gate electrode and applying a voltage to at least one of the source region and the drain region, causing a permanent polarization electric field to be established within the ferroelectric layer, thereby creating a conduction path along the channel. Via the programming operation, the anti-fuse device can be easily turned on when a critical voltage drops, even when a voltage applied to the gate electrode is a zero bias.

Description

Technical Field

[0001] The present invention relates to an anti-fuse device, in particular to an anti-fuse device utilizing ferroelectric characteristics. Background Art

[0002] For semiconductor devices, anti-fuse repair technology is used to repair faulty bits on integrated circuit chips (such as dynamic random access memory DRAM). An anti-fuse device is an electronic device that performs the opposite function of a fuse. Conventional anti-fuse devices, such as N-type metal oxide semiconductor field effect transistor (hereinafter referred to as NMOS) anti-fuse devices or P-type metal oxide semiconductor field effect transistor (hereinafter referred to as PMOS) anti-fuse devices, determine the switching state by causing the gate oxide layer to collapse. The NMOS anti-fuse device has an NMOS transistor, which has an N-type doped polysilicon gate, a channel region, and a source region / drain region formed by diffusing N-type dopants in a silicon substrate. The channel region separates the source region from the drain region in the lateral direction, and a dielectric material layer that prevents current from flowing separates the polysilicon gate from the channel region. Similarly, the PMOS anti-fuse device has a PMOS transistor with the same structure as the NMOS transistor, but it uses P-type dopants.

[0003] The dielectric material separating the polysilicon gate from the channel region (hereinafter referred to as the gate oxide layer) is usually composed of thermally generated silicon dioxide (SiO2) material, which leaks very little current through the Fowler-Nordheim tunneling effect under voltage stress. Once the voltage stress exceeds the critical electric field (the applied voltage divided by the thickness of the gate oxide layer), the transistor will be destroyed due to the collapse of the gate oxide layer.

[0004] The breakdown of the gate oxide depends on the proper pulse width duration and amplitude to limit the power through the gate oxide, thereby producing a reliable low resistance antifuse.

[0005] To perform a repair operation of the anti-fuse, the anti-fuse device is programmed by changing its state to be conductive. Figure 1A and Figure 1B A simplified diagram showing the state changes of an anti-fuse device utilizing a gate oxide breakdown method. Figure 1A The anti-fuse device 10 electrically connected to the repair circuit 100 is shown to have a high resistance and be in a non-conducting state when the gate oxide layer has not yet collapsed. Figure 1B It is shown that when the gate oxide collapse path is generated, the anti-fuse device 10 is in the on state and has a low resistance. That is, when the anti-fuse device 10 is blown (ie, the gate oxide collapses) and a permanent conductive path is generated, the anti-fuse device turns to a low resistance and the anti-fuse device is programmed.

[0006] Generally speaking, the blowing of the anti-fuse device depends on the thickness or area of ​​the gate oxide layer. Variations in the manufacturing process for manufacturing the anti-fuse device may change the breakdown voltage, thereby reducing the anti-fuse blowing efficiency. Summary of the invention

[0007] The present invention provides an anti-fuse device utilizing ferroelectric properties, wherein a ferroelectric layer is formed between a gate electrode and a channel of a metal oxide semiconductor field effect transistor (MOSFET) structure. After applying multiple voltage pulses at the gate electrode, a permanent polarization electric field induced in the ferroelectric layer is used to induce and establish a conduction path of the channel. The programming operation of the anti-fuse device can be performed by utilizing the natural ferroelectric properties to replace the gate oxide layer collapse method. Therefore, the disadvantage of the conventional anti-fuse device that the gate oxide layer collapse voltage changes due to manufacturing process changes during manufacturing can be avoided.

[0008] In one embodiment, the anti-fuse device utilizing ferroelectric properties provided by the present invention is configured into a MOSFET-type structure, which includes: an active region, the active region includes a source region, a drain region laterally separated from the source region, and a channel located between the source region and the drain region; and a gate structure, the gate structure includes a ferroelectric layer formed on the channel, and a gate electrode formed on the ferroelectric layer. By applying a voltage to the gate electrode and applying a voltage to at least one of the source region and the drain region, a permanent polarization electric field is established in the ferroelectric layer, thereby inducing a conduction path along the channel, and performing a programming operation of the anti-fuse device. Through the anti-fuse device utilizing ferroelectric properties of the present invention, even if the critical voltage applied to the gate electrode is reduced, the anti-fuse device configured into a MOSFET structure type of the present invention is easily turned on.

[0009] In one embodiment of the present invention, the gate electrode is a metal gate electrode.

[0010] In one embodiment of the present invention, the active region is lightly doped.

[0011] In one embodiment of the present invention, the gate structure further includes an interfacial layer formed between the ferroelectric layer and the channel.

[0012] In one embodiment of the present invention, the interface layer is a buffer layer.

[0013] In one embodiment of the present invention, the source region and the drain region are heavily doped with N-type dopants.

[0014] In one embodiment of the present invention, the source region and the drain region are heavily doped with P-type dopants.

[0015] In one embodiment of the present invention, the programming operation of the anti-fuse device is performed by applying a positive voltage pulse to the gate electrode with the source region and the drain region grounded.

[0016] In one embodiment of the present invention, the programming operation of the anti-fuse device is performed by applying a negative voltage pulse to the gate electrode with the source region and the drain region grounded.

[0017] The anti-fuse device using ferroelectric characteristics provided by the embodiment of the present invention can avoid the disadvantage of a conventional anti-fuse device that a gate oxide layer breakdown voltage varies due to a manufacturing process variation during manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other objects and advantages of the present invention will become apparent from a reading of the following detailed description and from a reference to the accompanying drawings, in which:

[0019] Figure 1A A simplified diagram showing an anti-fuse device in a non-conducting state when the gate oxide layer of the anti-fuse device has not yet collapsed.

[0020] Figure 1B A simplified diagram showing an anti-fuse device in an on state after its gate oxide has collapsed.

[0021] Figure 2 FIG. 4 is a schematic cross-sectional view of an NMOS anti-fuse device utilizing ferroelectric characteristics according to an embodiment of the present invention.

[0022] Figure 3A for Figure 2 The schematic cross-sectional view of the NMOS anti-fuse device utilizing ferroelectric properties without any voltage bias shows that the ferroelectric layer in the NMOS anti-fuse device has a random dipole direction.

[0023] Figure 3B for Figure 2 The schematic cross-sectional view of an NMOS anti-fuse device utilizing ferroelectric properties with multiple positive gate voltages applied thereto shows that all dipoles in the ferroelectric layer become stable and aligned in a consistent and constant direction.

[0024] Figure 4 for Figure 2 The schematic cross-sectional view of the NMOS anti-fuse device utilizing ferroelectric characteristics after multiple positive gate voltages are applied shows that a conduction path along the channel of the NMOS anti-fuse device is induced by the permanent polarization electric field established in the ferroelectric layer.

[0025] Figure 5The drain current (I) of the NMOS anti-fuse device using ferroelectric characteristics after programming operation of the present invention is compared with the conventional NMOS anti-fuse device using gate oxide layer breakdown mechanism. D ) and gate voltage (V G ) relationship diagram.

[0026] Fig. 6A FIG. 1 is a schematic cross-sectional view of a PMOS anti-fuse device utilizing ferroelectric characteristics according to another embodiment of the present invention without any voltage bias, showing that the ferroelectric layer in the PMOS anti-fuse device has a random dipole direction.

[0027] Figure 6B It is a schematic cross-sectional view of a PMOS anti-fuse device using ferroelectric characteristics according to another embodiment of the present invention when multiple negative gate voltages are applied, showing that all dipoles in the ferroelectric layer become stable and are aligned in a consistent and constant direction.

[0028] Figure 7 for Figure 6B The schematic cross-sectional view of a PMOS anti-fuse device utilizing ferroelectric characteristics with multiple negative gate voltages applied thereto shows that a conduction path is induced along the channel of the PMOS anti-fuse device by a permanent polarization electric field established in the ferroelectric layer.

[0029] Figure 8 The drain current (I) of the PMOS anti-fuse device using ferroelectric characteristics after programming operation of the present invention is compared with the conventional PMOS anti-fuse device using gate oxide layer breakdown mechanism. D ) and gate voltage (V G ) relationship diagram.

[0030] Fig. 9A Show Figure 2 Application of NMOS antifuse devices utilizing ferroelectric properties.

[0031] Fig. 9B Show Figure 6B Application of PMOS antifuse devices utilizing ferroelectric properties.

[0032] Reference Numbers

[0033] 10 Anti-fuse device

[0034] 100 Repair Circuit

[0035] 20 Active Zone

[0036] 20A source region

[0037] 20B drain region

[0038] Channel 20C

[0039] 21A Contact

[0040] 21B Contact

[0041] 22A Metal Wire

[0042] 22B Metal Wire

[0043] 23Interface Layer

[0044] 24Ferroelectric layer

[0045] 25Gate electrode

[0046] 25A contact

[0047] 25B metal wire

[0048] 30 Active Zone

[0049] 30A source region

[0050] 30B drain region

[0051] Channel 30C

[0052] 33Interface Layer

[0053] 34 Ferroelectric layer

[0054] 35 Gate electrode

[0055] 90a pulse generator

[0056] 90b pulse generator

[0057] I D Drain Current

[0058] V G Gate voltage DETAILED DESCRIPTION

[0059] The present invention will now be described by the best embodiment with reference to the accompanying drawings. The same reference numerals refer to the corresponding parts of the various drawings. Please note that existing circuits, structures and technologies may not be listed in detail to avoid confusing various aspects of the present disclosure. Various embodiments will be disclosed herein, however, it is to be understood that the disclosed embodiments are only used as examples that can be embodied in various forms. In addition, each example given in connection with the various embodiments is intended to be used as an example rather than a limitation. Furthermore, the drawings of the present case do not necessarily conform to the dimensional ratio, and some features are enlarged to show the details of specific components (and any dimensions, materials and similar details shown in the drawings are intended to be only examples rather than limitations). Therefore, the specific structural and functional details disclosed herein are not interpreted as limitations, but are only used to teach relevant technical personnel to implement the basis of the disclosed embodiments.

[0060] Figure 21 is a schematic cross-sectional view of an NMOS anti-fuse device utilizing ferroelectric properties according to an embodiment of the present invention. The NMOS anti-fuse device utilizing ferroelectric properties is hereinafter referred to as a FE NMOS anti-fuse device, which includes an active region 20 and a gate structure formed on the active region 20. The active region 20 includes a source region 20A, a drain region 20B laterally separated from the source region 20A, and a channel 20C located between the source region 20A and the drain region 20B. The source region 20A and the drain region 20B are heavily doped with N-type dopants. The gate structure includes a ferroelectric layer 24 formed on the channel 20C, and a gate electrode 25 formed on the ferroelectric layer 24. The gate structure further includes an interfacial layer 23 formed between the ferroelectric layer 24 and the channel 20C. In one embodiment of the present invention, due to the high dielectric constant of the ferroelectric layer 24, the gate electrode 25 can be a metal gate electrode. The active region 20 may be a lightly doped well, and the interface layer 23 may be a buffer layer to facilitate the formation of the ferroelectric layer 24 on the active region 20. The source region 20A may be applied with a source voltage through the contact 21A and the metal line 22A. The drain region 20B may be applied with a drain voltage through the contact 21B and the metal line 22B. The operating voltage of the FE NMOS anti-fuse device may be applied to the gate electrode 25 through the contact 25A and the metal line 25B.

[0061] Please refer to Figure 3A and Figure 3B , which respectively show schematic cross-sectional views of a FE NMOS anti-fuse device without any bias applied and a FE NMOS anti-fuse device with a pulse gate voltage applied. Figure 3A As shown, without any bias, the ferroelectric layer 24 has a random dipole direction. After applying a positive pulse amplitude to the gate electrode 25, for example, applying a positive pulse voltage of 1.5V to the gate electrode 25, and the source region 20A / drain region 20B are grounded, due to the positive bias of the gate electrode 25, the negative dipole in the ferroelectric layer 24 turns to the gate electrode 25, and the positive dipole in the ferroelectric layer 24 turns to the channel 20C. Then, all the dipoles in the ferroelectric layer 24 become stable and arranged in a consistent and constant direction, as shown in FIG. Figure 3B shown.

[0062] Please refer to Figure 4 After a positive pulse amplitude is applied to the FE NMOS anti-fuse device, all the dipoles in the ferroelectric layer 24 become stable and arranged in a consistent and constant direction, so that a permanent electric field polarization is established in the ferroelectric layer 24, and a conduction path along the channel 20C is induced. In this way, the FENMOS anti-fuse device can be easily turned on when the threshold voltage is reduced or even when the voltage applied to the gate electrode 25 is zero bias.

[0063] Figure 5 The drain current (I) of the FE NMOS anti-fuse device of the present invention after programming operation is compared with the conventional NMOS anti-fuse device using the gate oxide layer breakdown mechanism. D ) and gate voltage (V G ) The FE NMOS anti-fuse device of the present invention is G ~0V, i.e. VG(OFF)), it still has a high drain current (I D ).

[0064] Please refer to Fig. 9A , which shows the application of the FE NMOS anti-fuse device. The FE NMOS anti-fuse device is electrically connected to the repair circuit 100. The pulse generator 90a sends a plurality of voltage pulses, for example, with an amplitude of 1.5V, and applies them to the gate electrode 25 of the FE NMOS anti-fuse device to perform a programming operation on the FE NMOS anti-fuse device. After the programming operation, the FE NMOS anti-fuse device can be switched at a critical voltage (V T ) is reduced and can even be easily turned on when the voltage applied to the gate electrode 25 is zero bias.

[0065] According to another embodiment of the present invention, the anti-fuse device utilizing ferroelectric characteristics may be configured as a PMOS (FE PMOS) structure utilizing ferroelectric characteristics, such as Fig. 6A and Figure 6B As shown. The PMOS anti-fuse device utilizing ferroelectric properties is hereinafter referred to as a FE PMOS anti-fuse device, which includes an active region 30 and a gate structure formed on the active region 30. The active region 30 includes a source region 30A, a drain region 30B laterally separated from the source region 30A, and a channel 30C located between the source region 30A and the drain region 30B. The source region 30A and the drain region 30B are heavily doped with P-type dopants. The gate structure includes a ferroelectric layer 34 formed on the channel 30C and a gate electrode 35 formed on the ferroelectric layer 34. The gate structure further includes an interface layer 33 formed between the ferroelectric layer 34 and the channel 30C. In one embodiment of the present invention, due to the high dielectric constant of the ferroelectric layer 34, the gate electrode 35 can be a metal gate electrode, the active region 30 can be lightly doped, and the interface layer 33 can be a buffer layer to facilitate the formation of the ferroelectric layer 34 on the active region 30.

[0066] like Fig. 6AAs shown, without any bias, the ferroelectric layer 34 has a random dipole direction. After a negative pulse amplitude is applied to the gate electrode 35, for example, a negative pulse voltage of -1.5V is applied to the gate electrode 35, and the source region 30A / drain region 30B is grounded, due to the negative bias of the gate electrode 35, the positive dipole in the ferroelectric layer 34 turns to the gate electrode 35, and the negative dipole in the ferroelectric layer 34 turns to the channel 30C. Then, all the dipoles in the ferroelectric layer 34 become stable and arranged in a consistent and constant direction, as shown in FIG. Figure 6B shown.

[0067] Please refer to Figure 7 After a negative pulse amplitude is applied to the FE PMOS anti-fuse device, all the dipoles in the ferroelectric layer 34 become stable and arranged in a consistent and constant direction, so that a permanent polarization electric field is established in the ferroelectric layer 34, and a conduction path along the channel 30C is induced. Therefore, the FE NMOS anti-fuse device can be switched at a threshold voltage (V T ) is reduced and can even be easily turned on when the voltage applied to the gate electrode 35 is zero bias.

[0068] Figure 8 The drain current (I) of the FE PMOS anti-fuse device of the present invention after programming operation is compared with the conventional PMOS anti-fuse device using the gate oxide layer breakdown mechanism. D ) and gate voltage (V G ) The FE PMOS anti-fuse device of the present invention is G ~0V, i.e. VG(OFF)), it still has a high drain current (I D ).

[0069] Please refer to Fig. 9B , which shows the application of the FE PMOS anti-fuse device. The FE PMOS anti-fuse device is electrically connected to the repair circuit 100. The pulse generator 90b sends a plurality of voltage pulses, for example, with an amplitude of -1.5V, and applies them to the gate electrode 35 of the FE PMOS anti-fuse device to perform a programming operation on the FE PMOS anti-fuse device. After the programming operation, the FE NMOS anti-fuse device can be switched at a critical voltage (V T ) is reduced and can even be easily turned on when the voltage applied to the gate electrode 35 is zero bias.

[0070] The above embodiments of the present invention are exemplary and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, all changes or modifications made to achieve equivalent effects should be included in the scope of the accompanying patent applications.

Claims

1. An anti-fuse device utilizing ferroelectric properties, characterized in that: Include: an active region, the active region comprising a source region, a drain region laterally spaced from the source region, and a channel between the source region and the drain region; and a gate structure, the gate structure comprising a ferroelectric layer formed on the channel and a gate electrode formed on the ferroelectric layer; The programming operation of the anti-fuse device is performed by applying a voltage to the gate electrode and applying a voltage to at least one of the source region and the drain region to establish a permanent polarization electric field in the ferroelectric layer, thereby inducing a conduction path along the channel.

2. The anti-fuse device according to claim 1, wherein: The gate electrode is a metal gate electrode.

3. The anti-fuse device according to claim 1, wherein: The active region is a lightly doped well.

4. The anti-fuse device according to claim 1, wherein: The gate structure further includes an interface layer formed between the ferroelectric layer and the channel.

5. The anti-fuse device according to claim 4, wherein: The interface layer is a buffer layer.

6. The anti-fuse device according to claim 1, wherein: The source region and the drain region are heavily doped with N-type dopants.

7. The anti-fuse device according to claim 1, wherein: The source region and the drain region are heavily doped with P-type dopants.

8. The anti-fuse device according to claim 6, wherein: A programming operation of the anti-fuse device is performed by applying a positive voltage pulse to the gate electrode with the source region and the drain region grounded.

9. The anti-fuse device according to claim 8, wherein: The positive voltage pulse is 1.5V.

10. The anti-fuse device according to claim 7, wherein: A programming operation of the anti-fuse device is performed by applying a negative voltage pulse to the gate electrode with the source region and the drain region grounded.

11. The anti-fuse device according to claim 10, wherein: The negative voltage pulse is -1.5V.

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