Semiconductor device

Abstract

There is provided a semiconductor device including: a lower pattern layer including a first semiconductor material; a first conductivity type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity type impurity; a source / drain pattern disposed on the first conductivity type doped pattern layer and including a semiconductor material doped with a second conductivity type impurity different from the first conductivity type impurity; a channel pattern including semiconductor patterns connected between the source / drain patterns, stacked spaced apart from each other, and including a second semiconductor material different from the first semiconductor material; and a gate pattern disposed on the first conductivity type doping pattern layer and between the source / drain patterns, and surrounding the channel pattern.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0073507 filed in the Korean Intellectual Property Office on June 8, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0003] Semiconductors are materials that belong to the middle region between conductors and insulators and refer to materials that conduct electricity under certain conditions. Various semiconductor devices (e.g., memory devices) can be manufactured using these semiconductor materials. Such semiconductor devices can be used in various electronic devices.

[0004] With the rapid development of the electronics industry, the requirements for the characteristics of semiconductor devices are gradually increasing. For example, the requirements for high reliability, high speed and / or multifunctionality of semiconductor devices are gradually increasing. In order to meet these required characteristics, the structures within semiconductor devices are becoming more and more complex and integrated. Summary of the invention

[0005] In one aspect of the present disclosure, since etching can be deeply formed even in a device with a reduced size, the problem of unetched source / drain can be solved, and current leakage from the lower part of the source / drain can be prevented. When a back side power distribution network (BSPDN) structure is applied, the semiconductor device can easily realize a structure in which all lower substrates are removed by etching selectivity (BSPDN bulk-less).

[0006] According to one aspect, a semiconductor device includes: a lower pattern layer including a first semiconductor material; a first conductive type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with first conductive type impurities; a source / drain pattern disposed on the first conductive type doped pattern layer and including a semiconductor material doped with second conductive type impurities different from the first conductive type impurities; a channel pattern including a semiconductor pattern, the semiconductor pattern being connected between the source / drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; and a gate pattern disposed on the first conductive type doped pattern layer and between the source / drain patterns, and surrounding the channel pattern.

[0007] The first semiconductor material may include silicon (Si), germanium (Ge), or a combination thereof and include carbon (C).

[0008] The first semiconductor material may include germanium (Ge) of about 0 at % to about 31.5 at %, carbon (C) of greater than about 0 at % and less than or equal to about 2 at %, and the balance of silicon (Si).

[0009] The second semiconductor material may include silicon (Si), germanium (Ge), or a combination thereof.

[0010] The first conductive type impurity may be an n-type impurity, and the second conductive type impurity may be a p-type impurity.

[0011] The n-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof, and the p-type impurities may include boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof.

[0012] The first conductive type impurity may be a p-type impurity, and the second conductive type impurity may be an n-type impurity.

[0013] The n-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof, and the p-type impurities may include boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof.

[0014] The first conductive type doped pattern layer may be an epitaxial layer.

[0015] The gate pattern may have a main gate portion disposed on the semiconductor pattern and a sub gate portion disposed between the semiconductor patterns.

[0016] The semiconductor device may further include an inner gate spacer disposed between the sub-gate portion of the gate pattern and the source / drain pattern.

[0017] According to another embodiment, a semiconductor device includes: a lower pattern layer including a first semiconductor material; a first conductive type doped pattern layer, which is arranged on the lower pattern layer and includes a semiconductor material doped with first conductive type impurities; a source / drain pattern, which is arranged on the first conductive type doped pattern layer and includes a semiconductor material doped with second conductive type impurities different from the first conductive type impurities; a channel pattern, including a semiconductor pattern, the semiconductor patterns are connected between the source / drain patterns, are stacked apart from each other, and include a second semiconductor material different from the first semiconductor material; a gate pattern, which is arranged on the first conductive type doped pattern layer and between the source / drain patterns, and surrounds the channel pattern; and a lower contact electrode, which is arranged below the source / drain pattern and is connected to the source / drain pattern by penetrating the lower pattern layer and the first conductive type doped pattern layer.

[0018] The source / drain pattern may include a first source / drain structure and a second source / drain structure spaced apart from each other.

[0019] The semiconductor device may further include a first upper contact electrode disposed on and connected to the first source / drain structure.

[0020] A lower contact electrode may be disposed under the second source / drain structure and connected to the second source / drain structure.

[0021] The semiconductor device may further include a second upper contact electrode disposed on and connected to the gate pattern.

[0022] The semiconductor device may further include a lower interconnection structure disposed below the lower pattern layer.

[0023] The semiconductor device may further include an upper interconnection structure disposed on the source / drain patterns, the gate pattern, or a combination thereof.

[0024] The semiconductor device may further include a lower insulating layer disposed under the lower pattern layer.

[0025] The lower contact electrode may be connected to the source / drain pattern by penetrating the lower insulating layer.

[0026] According to another aspect, a semiconductor device includes: a first conductive type doped pattern layer, including a semiconductor material doped with a first conductive type impurity; a source / drain pattern, which is arranged on the first conductive type doped pattern layer and includes a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity; a channel pattern, including a semiconductor pattern connected between the source / drain patterns and spaced apart from each other; a gate pattern, which is arranged on the first conductive type doped pattern layer and between the source / drain patterns, and surrounds the channel pattern; and a lower contact electrode, which is arranged below the source / drain pattern and connected to the source / drain pattern by penetrating the first conductive type doped pattern layer.

[0027] The source / drain pattern may include a first source / drain structure and a second source / drain structure spaced apart from each other.

[0028] The semiconductor device may further include a first upper contact electrode disposed on and connected to the first source / drain structure.

[0029] A lower contact electrode may be disposed under the second source / drain structure and connected to the second source / drain structure.

[0030] The semiconductor device may further include a lower insulating layer disposed under the first conductive type doped pattern layer.

[0031] The lower contact electrode may be connected to the source / drain pattern by penetrating the lower insulating layer.

[0032] According to the embodiment, since etching can be deeply formed even in a device with a reduced size, the problem of unetched source / drain can be solved, and current leakage from the lower part of the source / drain can be prevented. When a back side power distribution network (BSPDN) structure is applied, a structure (BSPDN bodyless) in which all lower substrates are removed can also be easily realized by etching selectivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments.

[0034] Figure 2A It is along Figure 1 The cross-sectional view taken at X-X', Figure 2B It is along Figure 1 A cross-sectional view taken along the line Y-Y', and Figure 2C It is along Figure 1 Cross-sectional view taken along line Z-Z'.

[0035] Figure 3 is a diagram showing a semiconductor device according to another example embodiment and along Figure 1 The sectional view corresponding to the sectional view taken at XX'.

[0036] Figure 4A and Figure 4B FIG. 1 is a diagram showing a semiconductor device according to another example embodiment. Figure 2A and Figure 2B The cross-sectional view corresponding to the cross-sectional view.

[0037] FIG. 5A to FIG. 11B are cross-sectional views illustrating intermediate steps of a method of manufacturing a semiconductor device according to example embodiments.

[0038] FIG. 12A to FIG. 14B is a cross-sectional view illustrating an intermediate step of a method of manufacturing a semiconductor device according to another example embodiment.

[0039] Figures 15 to 19 is a cross-sectional view illustrating an intermediate step of a method of manufacturing a semiconductor device according to another example embodiment.

[0040] FIG. 20A to FIG. 28B are cross-sectional views illustrating intermediate steps of a method of manufacturing a semiconductor device according to example embodiments.

[0041] Fig.29A and Fig.29B is a cross-sectional view illustrating an intermediate step of a method of manufacturing a semiconductor device according to another example embodiment. DETAILED DESCRIPTION

[0042] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. As those skilled in the art will realize, the described embodiments can be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0043] The drawings and description are to be regarded as illustrative in nature and not restrictive.Throughout the specification, like reference numerals refer to like elements.

[0044] For better understanding and ease of description, the size and thickness of each constituent element as shown in the drawings are arbitrarily indicated, and the present disclosure is not necessarily limited to as shown. In the drawings, the thickness of layers, regions, etc. are exaggerated for clarity. In addition, in the drawings, the thickness of some layers and regions is exaggerated for better understanding and ease of description.

[0045] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "connected" or "coupled" to or "on" another element, the element may be directly connected or coupled to or directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to or "directly on" another element, or is referred to as "contacting" or "in contact with" another element (or any form of the word "contacting"), there are no intervening elements at the point of contact.

[0046] For ease of description, spatially relative terms such as "under", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figure. It will be understood that in addition to the orientation depicted in the figure, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "under" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the term "under" can cover both above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0047] As used herein, terms such as "same", "equal", "planar" or "coplanar" encompass approximate sameness including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0048] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” and “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0049] In addition, in this specification, the phrase "on a plane" means viewing the target portion from the top, and the phrase "on a cross section" means viewing the cross section formed by vertically cutting the target portion from the side.

[0050] In the drawings of semiconductor devices according to example embodiments, transistors including nanowires or nanosheets, multi-bridge channel field effect transistors (MBCFETs) are shown. TM ) and a fin transistor (FinFET) including a fin-shaped patterned channel region, but the present disclosure is not limited thereto. Of course, the semiconductor device according to some embodiments may include a tunneling transistor (tunneling FET), a 3D stacked field effect transistor (3DSFET), or a complementary field effect transistor (CFET).

[0051] Will refer to Figures 1 to 3 A semiconductor device according to example embodiments is described.

[0052] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments. Figure 2A It is along Figure 1 The cross-sectional view taken at X-X', Figure 2B It is along Figure 1 The cross-sectional view taken at Y-Y', Figure 2C It is along Figure 1 Cross-sectional view taken along line Z-Z'. Figure 3 is a diagram showing a semiconductor device according to another example embodiment and along Figure 1 The sectional view corresponding to the sectional view taken at XX'.

[0053] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C According to the embodiment, the semiconductor device 10 includes a lower insulating layer 330, a lower pattern layer 110 disposed on the lower insulating layer 330, a first conductive type doped pattern layer 115 disposed on the lower pattern layer 110, a source / drain pattern 150 disposed on the first conductive type doped pattern layer 115, a channel pattern CP disposed between the source / drain patterns 150, and a gate pattern GS configured to pass through and surround the channel pattern CP between the source / drain patterns 150.

[0054] The lower surface of the lower pattern layer 110 may contact the upper surface of the lower insulating layer 330 , the lower surface of the first conductive type doped pattern layer 115 may contact the upper surface of the lower pattern layer 110 , and the lower surface of the source / drain pattern 150 may contact the upper surface of the first conductive type doped pattern layer 115 .

[0055] Optionally, the semiconductor device 10 may further include a first spacer 130 and a second spacer 141 .

[0056] Optionally, the semiconductor device 10 may further include a gate spacer 140 , a capping layer 145 , an etch stop layer 185 , and an interlayer insulating layer 190 .

[0057] Optionally, the semiconductor device 10 may further include a lower contact electrode CT1 and a lower interconnection structure ML1 .

[0058] Optionally, the semiconductor device 10 may further include a first upper contact electrode UCT1 , a second upper contact electrode UCT2 , and an upper interconnection structure ML2 .

[0059] The lower insulating layer 330 may have an upper surface and a lower surface. The upper surface and the lower surface of the lower insulating layer 330 may be formed as planes parallel to the first direction D1 and the second direction D2 intersecting the first direction D1. The upper surface of the lower insulating layer 330 may be a surface opposite to the lower surface of the lower insulating layer 330 in the third direction D3. Here, the third direction D3 may be a direction intersecting the first direction D1 and the second direction D2. For example, the third direction D3 may be a thickness direction of the substrate 100. The lower surface of the lower insulating layer 330 may be referred to as the back side of the lower insulating layer 330. In some embodiments, the logic circuit of the unit region may be implemented on the upper surface of the lower insulating layer 330. Although the lower insulating layer 330 is shown as a single layer, this is only for ease of explanation and is not limited thereto.

[0060] As described later Fig.26A and Fig.27B As shown in FIG. 1 , the semiconductor device 10 according to the embodiment may be manufactured by removing the substrate 100 using the lower pattern layer 110 as an etch stop layer and then by forming the lower insulating layer 330 where the substrate 100 is located.

[0061] Therefore, the lower insulating layer 330 may have a shape similar to that of the substrate 100, but may be made of a material different from that of the substrate 100. For example, the substrate 100 may include bulk silicon, silicon on insulator (SOI), silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The lower insulating layer 330 may include, for example, oxide, nitride, oxynitride, or a combination thereof.

[0062] In addition, as described later Fig. 6A and Figure 6BAs shown in , the substrate 100 has a groove defining the sacrificial active pattern AP_P, and the field insulating layer 105 may be disposed in the groove. In the process of removing the substrate 100, the field insulating layer 105 may be removed together. In this case, the lower insulating layer 330 may not include the field insulating layer 105. However, when the field insulating layer 105 is not removed together in the process of removing the substrate 100, the lower insulating layer 330 may include the field insulating layer 105.

[0063] In addition, in the process of removing the substrate 100, even the sacrificial active pattern AP_P of the substrate 100 may be removed. The lower insulating layer 330 formed in the region where the substrate 100 is provided has an active shape corresponding to a portion of the sacrificial active pattern AP_P, for example, an active pattern AP having a shape corresponding to the sacrificial active pattern AP_P protruding on the field insulating layer 105. The semiconductor device 10 may include a plurality of active patterns AP. Each of the active patterns AP may have a sheet shape or a fin shape. The active patterns AP may extend longitudinally (longitudinally) along the first direction D1 and may be spaced apart from each other along the second direction D2. For example, the active pattern AP may be provided in a region where an NMOS is formed. As another example, the active pattern AP may be provided in a region where a PMOS is formed.

[0064] Like the lower insulating layer 330 , the active pattern AP may include, for example, oxide, nitride, oxynitride, or a combination thereof.

[0065] The lower pattern layer 110 is disposed on an upper surface of the lower insulating layer 330 .

[0066] The lower pattern layers 110 may longitudinally extend in the first direction D1 like the active patterns AP of the lower insulating layer 330, and may be spaced apart from each other in the second direction D2. The lower pattern layers 110 may contact an upper surface of the active patterns AP.

[0067] The first spacer 130 may be disposed on both side surfaces of the lower pattern layer 110 and both side surfaces of the active pattern AP in the second direction D2. The first spacer 130 may contact side surfaces of the lower pattern layer 110 and side surfaces of the active pattern AP.

[0068] The lower pattern layer 110 may overlap the source / drain pattern 150 to be described later in the third direction D3. The lower pattern layer 110 may extend in the first direction D1 to cross the gate pattern GS to be described later.

[0069] The lower pattern layer 110 may include a first semiconductor material having an etching selectivity with respect to the substrate 100 or the semiconductor patterns SP1, SP2, SP3, and SP4 described later. For example, the first semiconductor material may include silicon (Si), germanium (Ge), or a combination thereof, and carbon (C). For example, the first semiconductor material may include germanium (Ge) of about 0 at % to about 31.5 at %, carbon (C) of greater than about 0 at % and less than or equal to about 2 at %, and the remainder of silicon (Si).

[0070] As will be described later 7A to 11B As shown in the figure, when the source / drain groove 150R is formed and the sacrificial lower pattern UBP under the source / drain groove 150R is selectively removed, the lower pattern layer 110 may include a first semiconductor material having etching selectivity with respect to the substrate 100 or the semiconductor patterns SP1, SP2, SP3 and SP4, so the lower pattern layer 110 can be used as an etching stop layer (wet stopper) to prevent the substrate 100 or the semiconductor patterns SP1, SP2, SP3 and SP4 from being etched.

[0071] The first conductive type doped pattern layer 115 may be disposed on an upper surface of the lower pattern layer 110 .

[0072] The first conductive type doped pattern layers 115 may longitudinally extend along the first direction D1 like the lower pattern layers 110 , and may be spaced apart from each other along the second direction D2 .

[0073] The first conductive type doped pattern layer 115 may overlap a source / drain pattern 150 to be described later in the third direction D3. The first conductive type doped pattern layer 115 may extend in the first direction D1 to cross a gate pattern GS to be described later.

[0074] The first conductive type doped pattern layer 115 may include a semiconductor material doped with a first conductive type impurity. Meanwhile, the source / drain pattern 150, which will be described later, may include a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity. For example, the first conductive type doped pattern layer 115 may include a semiconductor material that is counter-doped with the source / drain pattern 150. The first conductive type doped pattern layer 115 may prevent current from leaking under the source / drain pattern 150, and therefore, there is no need to ensure a space for preventing leakage, so that the size of the semiconductor device 10 can be further reduced.

[0075] In addition, as will be described later 7A to 11BAs shown in FIG. 1 , after forming the source / drain groove 150R and selectively removing the sacrificial lower pattern UBP below the source / drain groove 150R, the first conductive type doped pattern layer 115 and the source / drain pattern 150 are formed together, or as will be described later FIG. 12A to FIG. 14B As shown in FIG. 1 , the source / drain pattern 150 may be formed after forming the first conductive type doped pattern layer 115. The current leakage under the source / drain pattern 150 may be prevented by the first conductive type doped pattern layer 115.

[0076] In addition, since the first conductive type doped pattern layer 115 is formed together with the source / drain pattern 150, the first conductive type doped pattern layer 115 does not hinder the growth of the source / drain pattern 150. Therefore, it is possible to prevent the productivity from being reduced due to the first conductive type doped pattern layer 115 inhibiting the growth of the source / drain pattern 150, and it is possible to prevent the performance from being degraded due to the reduced stress effect caused by defects in the source / drain pattern 150, reduced activation of dopants, and increased diffusion caused by crystal defects.

[0077] The first conductive type doping pattern layer 115 may include, for example, a semiconductor material doped with first conductive type impurities, such as at least one of silicon (Si) and silicon germanium (SiGe).

[0078] For example, when the semiconductor material doped with the second conductive type impurities included in the source / drain pattern 150 includes a semiconductor material doped with n-type impurities (i.e., when the source / drain pattern 150 is disposed in an NMOS region), the semiconductor material doped with the first conductive type impurities included in the first conductive type doped pattern layer 115 may include a semiconductor material doped with p-type impurities. In addition, when the semiconductor material doped with the second conductive type impurities included in the source / drain pattern 150 includes a semiconductor material doped with p-type impurities (i.e., when the source / drain pattern 150 is disposed in a PMOS region), the semiconductor material doped with the first conductive type impurities included in the first conductive type doped pattern layer 115 may include a semiconductor material doped with n-type impurities.

[0079] For example, the n-type impurity may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. For example, when phosphorus (P) is used as the n-type impurity, phosphorus (P) or phosphine (PH) may be used. 3 ) as an impurity gas by low-energy ion implantation, plasma ion implantation or pulsed laser ablation deposition.

[0080] The p-type impurity may include boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof. For example, when boron (B) is used as the p-type impurity, boron (B), boron difluoride (BF 2 ) or boron trifluoride (BF 3 ) as an impurity gas by low-energy ion implantation, plasma ion implantation or pulsed laser ablation deposition.

[0081] When the first conductive type doped pattern layer 115 is formed together with the source / drain pattern 150 , the first conductive type doped pattern layer 115 may be an epitaxial layer formed by a selective epitaxial growth process using the lower pattern layer 110 as a seed.

[0082] The second spacer 141 may be disposed on both side surfaces of the first spacer 130, both side surfaces of the first conductive type doped pattern layer 115, and both side surfaces of the source / drain pattern 150 in the second direction D2. For example, the second spacer 141 may contact the side surface of the first spacer 130, the side surface of the first conductive type doped pattern layer 115, and the side surface of the source / drain pattern 150. In this case, the second spacer 141 may cover the entire side surface of the source / drain pattern 150, but the present disclosure is not limited thereto, and the second spacer 141 may cover only a portion of the side surface of the source / drain pattern 150. For example, the height of the upper end of the second spacer 141 in the third direction D3 may be the same as the height of the upper end of the source / drain pattern 150 in the third direction D3, or may be lower than the height of the upper end of the source / drain pattern 150 in the third direction D3.

[0083] Meanwhile, in some embodiments, the second spacer 141 may not be disposed on both side surfaces in the second direction D2 of the source / drain pattern 150. In this case, the source / drain pattern 150 may also be laterally grown in the second direction D2 during epitaxial growth, and thus may have a rhombus shape with a convex left side surface and a convex right side surface.

[0084] The channel pattern CP may be disposed on an upper surface of the active pattern AP. The channel pattern CP may be spaced apart from the active pattern AP in the third direction D3.

[0085] The lower pattern layer 110 and the first conductive type doped pattern layer 115 may be disposed between the channel pattern CP and the active pattern AP. The channel pattern CP may also be spaced apart from the first conductive type doped pattern layer 115 in the third direction D3.

[0086] The channel pattern CP may include semiconductor patterns SP1, SP2, SP3, and SP4. For example, the channel pattern CP may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a fourth semiconductor pattern SP4. The first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 may be disposed higher than an upper surface of the first conductive type doped pattern layer 115.

[0087] The second semiconductor pattern SP2 may be disposed on the first semiconductor pattern SP1, the third semiconductor pattern SP3 may be disposed on the second semiconductor pattern SP2, and the fourth semiconductor pattern SP4 may be disposed on the third semiconductor pattern SP3. The second semiconductor pattern SP2 may be spaced apart from the first semiconductor pattern SP1 and the third semiconductor pattern SP3 in the third direction D3, and the third semiconductor pattern SP3 may be spaced apart from the second semiconductor pattern SP2 and the fourth semiconductor pattern SP4 in the third direction D3. The separation distances between the semiconductor patterns SP1, SP2, SP3, and SP4 may be substantially the same. However, the present disclosure is not limited thereto, and the separation distances between the semiconductor patterns SP1, SP2, SP3, and SP4 may be different.

[0088] The semiconductor patterns SP1 , SP2 , SP3 , and SP4 may have substantially the same thickness, but are not limited thereto, and the thickness of at least one of the semiconductor patterns SP1 , SP2 , SP3 , and SP4 may be different.

[0089] exist Figure 2A , Figure 2B and Figure 2C , four semiconductor patterns SP1, SP2, SP3 and SP4 are shown to be spaced apart from each other along the third direction D3, but this is for convenience of description and the present disclosure is not limited thereto. For example, three or five or more semiconductor patterns may be spaced apart from each other and stacked along the third direction D3.

[0090] The semiconductor patterns SP1 , SP2 , SP3 , and SP4 may include a second semiconductor material different from the first semiconductor material included in the lower pattern layer 110 .

[0091] In addition, each of the semiconductor patterns SP1 , SP2 , SP3 , and SP4 may include the same semiconductor material as the sacrificial active pattern AP_P of the substrate 100 or a semiconductor material different from the sacrificial active pattern AP_P of the substrate 100 .

[0092] Since the semiconductor patterns SP1, SP2, SP3, and SP4 include a second semiconductor material different from the first semiconductor material included in the lower pattern layer 110, as will be described later Figure 5A and Figure 5B As shown in FIG. 1 , the upper pattern U_AP for forming the semiconductor patterns SP1, SP2, SP3, and SP4 can be easily formed. In addition, as will be described later Fig.9A and Fig. 9B As shown in FIG. 1 , when removing the sacrificial lower pattern UBP, the lower pattern layer 110 serves as an etch stop layer (wet stop) to prevent the substrate 100 or the semiconductor patterns SP1, SP2, SP3, and SP4 from being etched. In addition, as described later Fig.26A and Fig.26B As shown in, in a method of manufacturing a semiconductor device 10 according to an example embodiment, in a process of removing the entire substrate 100 when applying a back-side power distribution network (BSPDN) structure, by using a lower pattern layer 110 as an etching stop layer (wet stop), a BSPDN bodyless structure (a structure in which all silicon substrates are removed) can be easily achieved through etching selectivity.

[0093] For example, the second semiconductor material included in the semiconductor patterns SP1, SP2, SP3, and SP4 may include an elemental semiconductor material such as silicon (Si) or germanium (Ge). In addition, the second semiconductor material may include a compound semiconductor such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0094] The Group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0095] The III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, and a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as III-group elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as V-group elements.

[0096] The gate pattern GS may be disposed on the lower insulating layer 330. The lower pattern layer 110 and the first conductive type doped pattern layer 115 may be disposed between the gate pattern GS and the lower insulating layer 330.

[0097] The gate patterns GS may extend longitudinally in the second direction D2. The gate patterns GS may be spaced apart from each other in the first direction D1.

[0098] For example, each of the gate patterns GS may be disposed on the first conductive type doped pattern layer 115 and may intersect the first conductive type doped pattern layer 115. A lower portion of the gate pattern GS may intersect an upper portion of the first conductive type doped pattern layer 115.

[0099] The gate pattern GS may have a sub-gate portion (or "sub-gate structure") S_GS and a main gate portion (or "main gate structure") M_GS. The sub-gate portion S_GS may be disposed between the semiconductor patterns SP1, SP2, SP3, and SP4 adjacent to each other in the third direction D3 and between the first conductive type doped pattern layer 115 and the semiconductor patterns SP1, SP2, SP3, and SP4. The main gate portion M_GS may be disposed on the semiconductor patterns SP1, SP2, SP3, and SP4 at the uppermost portion in the third direction D3, and may be disposed between the semiconductor patterns SP1, SP2, SP3, and SP4 spaced apart from each other in the second direction D2.

[0100] When the channel pattern CP includes a plurality of semiconductor patterns SP1, SP2, SP3, and SP4, the gate pattern GS may include a plurality of sub-gate portions S_GS. The number of the sub-gate portions S_GS may be proportional to the number of semiconductor patterns SP1, SP2, SP3, and SP4 included in the channel pattern CP. For example, the number of the sub-gate portions S_GS may be the same as the number of the semiconductor patterns SP1, SP2, SP3, and SP4.

[0101] The sub-gate portion S_GS may include a first sub-gate portion, a second sub-gate portion, a third sub-gate portion, and a fourth sub-gate portion. The first sub-gate portion, the second sub-gate portion, the third sub-gate portion, and the fourth sub-gate portion may be sequentially spaced apart in the third direction D3 and stacked on the lower insulating layer 330. In the following description, a case where the number of sub-gate portions S_GS is four will be described. However, the present disclosure is not limited thereto, and the sub-gate portion S_GS may include 3 or 5 or more sub-gate portions.

[0102] For example, the first sub-gate portion may be disposed between the upper surface of the first conductive type doped pattern layer 115 and the lower surface of the first semiconductor pattern SP1; the second sub-gate portion may be disposed between the upper surface of the first semiconductor pattern SP1 and the lower surface of the second semiconductor pattern SP2; the third sub-gate portion may be disposed between the upper surface of the second semiconductor pattern SP2 and the lower surface of the third semiconductor pattern SP3; and the fourth sub-gate portion may be disposed between the upper surface of the third semiconductor pattern SP3 and the lower surface of the fourth semiconductor pattern SP4.

[0103] The sub-gate portions S_GS may be spaced apart from each other along the first direction D1 between source / drain patterns 150 to be described later.

[0104] Each of the sub-gate portions S_GS may include a sub-gate electrode 120S, a sub-interface insulating layer 131S, and a sub-gate insulating layer 132S.

[0105] The sub-gate electrode 120S may be disposed on the first conductive type doped pattern layer 115. The sub-gate electrode 120S may cross the active pattern AP.

[0106] At least a portion of the sub-gate electrode 120S may be disposed on the stacked structure of the sub-gate electrode 120S and the channel pattern CP. In this case, a portion of the main gate electrode 120M may be disposed to cover both side surfaces of the stacked structure of the sub-gate electrode 120S and the channel pattern CP. Therefore, the four surfaces of the channel pattern CP may be surrounded by the sub-gate electrode 120S and the main gate electrode 120M.

[0107] The sub-gate electrode 120S may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. The sub-gate electrode 120S may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten The conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the above materials, but are not limited thereto.

[0108] The sub-interface insulating layer 131S may be disposed on the upper surface of the first conductive type doped pattern layer 115. The sub-interface insulating layer 131S may be disposed along the periphery of the channel pattern CP. The sub-interface insulating layer 131S may directly contact the first conductive type doped pattern layer 115, the source / drain pattern 150, and the channel pattern CP. The sub-interface insulating layer 131S may be disposed between the channel pattern CP and the sub-gate insulating layer 132S.

[0109] The sub-gate insulating layer 132S may be disposed on the upper surface of the sub-interface insulating layer 131S. The sub-gate insulating layer 132S may surround the channel pattern CP. The sub-gate insulating layer 132S may be disposed along the periphery of the channel pattern CP. The sub-gate insulating layer 132S may be disposed between the sub-gate electrode 120S and the sub-interface insulating layer 131S.

[0110] As described later Figure 3 As shown in , the sub-gate insulating layer 132S may be disposed between the sub-gate electrode 120S and the inner gate spacer 133 .

[0111] The sub-interface insulating layer 131S may include, for example, silicon oxide (SiO 2 The sub-gate insulating layer 132S may include, for example, a high dielectric constant material. The high dielectric constant material may include silicon oxide (SiO 2 )'s dielectric constant is a material with a high dielectric constant (such as hafnium oxide (HfO), aluminum oxide (AlO) or tantalum oxide (TaO)).

[0112] The main gate portion M_GS may be disposed on the uppermost fourth semiconductor pattern SP4 in a region crossing the active pattern AP, and may be disposed on the lower insulating layer 330 in a region not crossing the active pattern AP.

[0113] Thus, the gate pattern GS may surround the channel pattern CP. For example, surfaces (e.g., four surfaces) of the semiconductor patterns SP1, SP2, SP3, and SP4 that are not connected to the source / drain pattern 150 may be surrounded by the gate pattern GS. That is, the sub-gate portion S_GS may surround the upper and lower portions of the semiconductor patterns SP1, SP2, SP3, and SP4, and the main gate portion M_GS may surround the side surfaces of the semiconductor patterns SP1, SP2, SP3, and SP4 and the upper portion of the uppermost fourth semiconductor pattern SP4.

[0114] The main gate portion M_GS may include a main gate electrode 120M, a main interface insulating layer 131M, and a main gate insulating layer 132M.

[0115] The main gate electrode 120M may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal nitride, or a combination thereof. For example, the main gate electrode 120M may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten The conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the above materials, but are not limited thereto.

[0116] The main interface insulating layer 131M may extend along the upper surfaces of the semiconductor patterns SP1, SP2, SP3, and SP4 and the upper surface of the active pattern AP. The main interface insulating layer 131M may not extend along the side surfaces of the gate spacer 140 to be described later. However, the present disclosure is not limited thereto, and the main interface insulating layer 131M may extend along the side surfaces of the gate spacer 140.

[0117] The main interface insulating layer 131M may include, for example, silicon oxide (SiO 2 The main gate insulating layer 132M may include, for example, a high dielectric constant material. The high dielectric constant material may include a material having a dielectric constant greater than silicon oxide (SiO 2 )'s dielectric constant is a material with a high dielectric constant (such as hafnium oxide (HfO), aluminum oxide (AlO) or tantalum oxide (TaO)).

[0118] The main gate insulating layer 132M may extend along side surfaces and a lower surface of the main gate electrode 120M. The main gate insulating layer 132M may extend along side surfaces of the gate spacer 140 .

[0119] The main gate insulating layer 132M may include, for example, a high dielectric constant material. The high dielectric constant material may include a dielectric constant having a dielectric constant greater than silicon oxide (SiO 2 )'s dielectric constant is a material with a high dielectric constant (such as hafnium oxide (HfO), aluminum oxide (AlO) or tantalum oxide (TaO)).

[0120] The gate spacer 140 may be disposed on a side surface of the main gate electrode 120M. The gate spacer 140 may contact a side surface of the main gate insulating layer 132M of the main gate portion M_GS. The gate spacer 140 is not disposed between the active pattern AP and the semiconductor patterns SP1, SP2, SP3, and SP4. The gate spacer 140 is not disposed between the semiconductor patterns SP1, SP2, SP3, and SP4 adjacent in the third direction D3.

[0121] The gate spacer 140 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof. Although the gate spacer 140 is shown as a single layer, this is only for ease of description and is not limited thereto.

[0122] At the same time, if Figure 3 As shown in , the inner gate spacer 133 may be disposed between the sub-gate portion S_GS and the source / drain pattern 150 .

[0123] The inner gate spacer 133 may respectively contact the sub-gate structure S_GS and the source / drain pattern 150. The inner gate spacer 133 may be disposed between the first conductive type doped pattern layer 115 and the channel pattern CP and between the channel patterns CP adjacent to each other in the third direction D3.

[0124] The inner gate spacer 133 may include a low dielectric constant material. The low dielectric constant material may include silicon oxide or a material having a dielectric constant lower than that of silicon oxide. For example, the low dielectric constant material may include silicon oxide, silicon oxide doped with fluorine or carbon, porous silicon oxide, or an organic polymer dielectric. For another example, the inner gate spacer 133 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon oxycarbon nitride (SiOCN).

[0125] Return to reference Figure 1 , Figure 2A , Figure 2B and Figure 2C , the capping layer 145 may be disposed on the main gate portion M_GS and the gate spacer 140. For example, the capping layer 145 may contact the upper surface of the main gate electrode 120M of the main gate portion M_GS and the upper surface of the main gate insulating layer 132M of the main gate portion M_GS and the upper surface of the gate spacer 140. The upper surface of the capping layer 145 and the upper surface of the interlayer insulating layer 190 may be in the same plane. Unlike what is shown, the capping layer 145 may be disposed between the gate spacers 140.

[0126] The capping layer 145 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or a combination thereof. The capping layer 145 may include a material having an etching selectivity with respect to the interlayer insulating layer 190 .

[0127] The source / drain pattern 150 may be disposed on the active pattern AP.

[0128] The source / drain pattern 150 may be disposed in a source / drain groove 150R extending in the third direction D3. The source / drain groove 150R may be formed as described later. 7A to 11B 150R. The source / drain pattern 150 may fill the source / drain groove 150R. The bottom surface of the source / drain groove 150R may be defined by the first conductive type doped pattern layer 115. The side surface of the source / drain groove 150R may be defined by the semiconductor patterns SP1, SP2, SP3, and SP4 and the sub-gate portion S_GS. The bottom surface of the source / drain pattern 150 may contact the first conductive type doped pattern layer 115. The side surface of the source / drain pattern 150 may contact the semiconductor patterns SP1, SP2, SP3, and SP4.

[0129] The source / drain pattern 150 may be disposed on a side surface of the sub-gate portion S_GS. For example, the source / drain pattern 150 may contact a side surface of the sub-interface insulating layer 131S or the inner gate spacer 133 of the sub-gate portion S_GS. The source / drain pattern 150 may be disposed between the sub-gate portions S_GS adjacent along the first direction D1. For example, the source / drain pattern 150 may be disposed on both sides of the sub-gate portion S_GS.

[0130] The source / drain pattern 150 may be disposed on side surfaces of the semiconductor patterns SP1, SP2, SP3, and SP4 of the channel pattern CP. For example, the source / drain pattern 150 may contact side surfaces of the semiconductor patterns SP1, SP2, SP3, and SP4. The source / drain pattern 150 may be disposed between the semiconductor patterns SP1, SP2, SP3, and SP4 that are adjacent to each other along the first direction D1.

[0131] In example embodiments, the side surface of the source / drain pattern 150 may have an uneven wavy shape. For example, the side surface of the source / drain pattern 150 adjacent to the sub-gate portion S_GS may have a concave shape toward the sub-gate portion S_GS, and the side surface of the source / drain pattern 150 adjacent to the semiconductor patterns SP1, SP2, SP3, and SP4 may have a convex shape toward the semiconductor patterns SP1, SP2, SP3, and SP4.

[0132] The source / drain pattern 150 may be an epitaxial pattern formed by a selective epitaxial growth process. The source / drain pattern 150 may include, for example, at least one of silicon (Si) and silicon germanium (SiGe). The source / drain pattern 150 may be used as a source / drain of a transistor using the semiconductor patterns SP1, SP2, SP3, and SP4 as a channel region.

[0133] As described above, the source / drain pattern 150 may include a semiconductor material doped with second conductive type impurities different from a semiconductor material doped with first conductive type impurities included in the first conductive type doped pattern layer 115 .

[0134] The source / drain pattern 150 may include, for example, a semiconductor material doped with second conductive type impurities, such as at least one of silicon (Si) and silicon germanium (SiGe).

[0135] For example, when the semiconductor material doped with the second conductive type impurities included in the source / drain pattern 150 includes a semiconductor material doped with n-type impurities (i.e., when the source / drain pattern 150 is disposed in an NMOS region), the semiconductor material doped with the first conductive type impurities included in the first conductive type doped pattern layer 115 may include a semiconductor material doped with p-type impurities. In addition, when the semiconductor material doped with the second conductive type impurities included in the source / drain pattern 150 includes a semiconductor material doped with p-type impurities (i.e., when the source / drain pattern 150 is disposed in a PMOS region), the semiconductor material doped with the first conductive type impurities included in the first conductive type doped pattern layer 115 may include a semiconductor material doped with n-type impurities.

[0136] For example, the n-type impurity may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. For example, when phosphorus (P) is used as the n-type impurity, phosphorus (P) or phosphine (PH) may be used. 3 ) as an impurity gas by low-energy ion implantation, plasma ion implantation or pulsed laser ablation deposition.

[0137] The p-type impurity may include boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof. For example, when boron (B) is used as the p-type impurity, boron (B), boron difluoride (BF 2 ) or boron trifluoride (BF 3 ) as an impurity gas by low-energy ion implantation, plasma ion implantation or pulsed laser ablation deposition.

[0138] The source / drain pattern 150 may include a first source / drain structure 151 and a second source / drain structure 152 .

[0139] The first source / drain structure 151 and the second source / drain structure 152 may be connected to the first upper contact electrode UCT1 or the lower contact electrode CT1 to be described later. For example, the first source / drain structure 151 may be connected to the first upper contact electrode UCT1, and the second source / drain structure 152 may be connected to the lower contact electrode CT1. Hereinafter, the source / drain pattern 150 connected to the first upper contact electrode UCT1 is referred to as the first source / drain structure 151, and the source / drain pattern 150 connected to the lower contact electrode CT1 is referred to as the second source / drain structure 152.

[0140] The first and second source / drain structures 151 and 152 may be spaced apart from each other in the second direction D2 along the extension direction of the gate pattern GS. An interlayer insulating layer 190 to be described later may be disposed between the first and second source / drain structures 151 and 152.

[0141] The etch stop layer 185 may be disposed on the side surface of the gate spacer 140 and the upper surface of the source / drain pattern 150. The etch stop layer 185 may contact the side surface of the gate spacer 140 and the upper surface of the source / drain pattern 150. The etch stop layer 185 may include a material having an etching selectivity with respect to the interlayer insulating layer 190 to be described later. The etch stop layer 185 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0142] The interlayer insulating layer 190 may be disposed on the etch stop layer 185. The interlayer insulating layer 190 may contact the etch stop layer 185. The interlayer insulating layer 190 may be disposed on the source / drain pattern 150. The interlayer insulating layer 190 may not cover the upper surface of the capping layer 145.

[0143] The interlayer insulating layer 190 may include, for example, silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material. The low dielectric constant material may include, for example, tetraethyl fluoride orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (tonen SilaZen, Dongran Silazane), FSG (fluorinated silicate glass), nano foam (such as polypropylene oxide or polyimide), CDO (carbon-doped silicon oxide), OSG (organosilicate glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica or a combination thereof, but is not limited thereto.

[0144] The lower interconnection structure ML1 may be disposed below the lower surface of the lower insulating layer 330. The lower interconnection structure ML1 may contact the lower surface of the lower insulating layer 330. The lower interconnection structure ML1 may be, for example, a power delivery network supplying a voltage (eg, a power supply voltage, etc.) to the source / drain pattern 150.

[0145] The lower interconnection structure ML1 may include a lower interconnection 340 and a lower interconnection insulating layer 350 .

[0146] The lower interconnection 340 may be disposed on the lower surface of the lower insulating layer 330. The lower interconnection 340 may include a metal (eg, copper). The lower interconnection 340 may be electrically connected to the lower contact electrode CT1. A description thereof will be given later.

[0147] The lower interconnection insulating layer 350 may contact the upper surface and the side surface of the lower interconnection 340. The lower surface of the lower interconnection 340 and the lower surface of the lower interconnection insulating layer 350 may be coplanar.

[0148] In addition, Figure 1 , Figure 2A , Figure 2B and Figure 2C In the embodiment, the lower interconnection 340 longitudinally extends in a second direction D2 parallel to the direction in which the gate pattern GS extends, but is not limited thereto. For example, the lower interconnection 340 may extend in a first direction D1 intersecting the direction in which the gate pattern GS extends.

[0149] The lower interconnection insulating layer 350 may be disposed below the lower surface of the lower insulating layer 330. The lower interconnection insulating layer 350 may cover the lower interconnection 340, and the lower interconnection 340 may be disposed within the lower interconnection insulating layer 350. The lower interconnection insulating layer 350 may include, for example, silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material.

[0150] The lower contact electrode CT1 may be disposed between the source / drain pattern 150 and the lower interconnection structure ML1 .

[0151] The lower contact electrode CT1 may be connected to at least one source / drain pattern 150. For example, the lower contact electrode CT1 may be connected to the second source / drain structure 152. The lower contact electrode CT1 may contact the second source / drain structure 152. The lower contact electrode CT1 may not be connected to the first source / drain structure 151.

[0152] In the following description, a case where the lower contact electrode CT1 is connected to the second source / drain structure 152 but not to the first source / drain structure 151 will be described. In this case, the first source / drain structure 151 may be connected to the first upper contact electrode UCT1, and the second source / drain structure 152 may not be connected to the first upper contact electrode UCT1. However, the present disclosure is not limited thereto, and the lower contact electrode CT1 may be connected to the first source / drain structure 151. The lower contact electrode CT1 may not be connected to the second source / drain structure 152. In this case, the second source / drain structure 152 may be connected to the first upper contact electrode UCT1, and the first source / drain structure 151 may not be connected to the first upper contact electrode UCT1.

[0153] The lower contact electrode CT1 may be disposed between the second source / drain structure 152 and the lower interconnect structure ML1. The lower contact electrode CT1 may extend from the second source / drain structure 152 to the lower interconnect structure ML1 in the third direction D3. A lower surface of the lower contact electrode CT1 may be connected to the lower interconnect structure ML1. An upper surface of the lower contact electrode CT1 may be connected to the second source / drain structure 152. The lower contact electrode CT1 may penetrate the lower pattern layer 110 and the first conductive type doped pattern layer 115.

[0154] In addition, the lower contact electrode CT1 may be disposed within the lower insulating layer 330, and the lower contact electrode CT1 penetrates the lower insulating layer 330 so that an upper surface of the lower contact electrode CT1 may be connected to the second source / drain structure 152, and a lower surface of the lower contact electrode CT1 may be connected to the lower interconnection structure ML1. In example embodiments, the lower surface of the lower contact electrode CT1 may be coplanar with a lower surface of the lower insulating layer 330.

[0155] The second source / drain structure 152 and the lower interconnection structure ML1 may be electrically connected to each other through the lower contact electrode CT1. That is, a voltage (eg, a power supply voltage, etc.) may be applied from the lower interconnection structure ML1 to the second source / drain structure 152 through the lower contact electrode CT1.

[0156] The lower contact electrode CT1 may include a conductive pattern 230 and a barrier pattern 240 configured to surround the conductive pattern 230 .

[0157] The conductive pattern 230 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0158] The barrier pattern 240 may cover the sidewalls and the upper surface of the conductive pattern 230. For example, the barrier pattern 240 may contact the upper surface and the side surface of the conductive pattern 230. The barrier pattern 240 may include a metal, a metal alloy, or a conductive metal nitride. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0159] Although the lower contact electrode CT1 is illustrated as a double layer including the conductive pattern 230 and the barrier pattern 240 , this is merely for convenience of explanation, and the present disclosure is not limited thereto.

[0160] Although not shown in the drawings, according to some embodiments, a metal silicide layer may be further disposed between the second source / drain structure 152 and the lower contact electrode CT1 of the semiconductor device 10. For example, the metal silicide layer may be disposed along an interface of the lower contact electrode CT1 contacting the second source / drain structure 152. The metal silicide layer may include metal silicide.

[0161] The upper interconnection structure ML2 may be disposed on an upper surface of the interlayer insulating layer 190. The upper interconnection structure ML2 may be, for example, a power delivery network that supplies a voltage (eg, a power supply voltage, etc.) to the gate pattern GS or the source / drain pattern 150.

[0162] The upper interconnection structure ML2 may include an upper interconnection 320 and an upper interconnection insulating layer 310 .

[0163] The upper interconnection 320 may be disposed on the upper surface of the interlayer insulating layer 190. The upper interconnection 320 may include a metal (eg, copper). The upper interconnection 320 may be electrically connected to a first upper contact electrode UCT1 or a second upper contact electrode UCT2 described later. Figure 1 , Figure 2A , Figure 2B and Figure 2CIt is shown that the upper interconnect 320 is connected to the first upper contact electrode UCT1 described later, and is not connected to the second upper contact electrode UCT2 described later. However, the present disclosure is not limited thereto. For example, the upper interconnect 320 may be connected to the second upper contact electrode UCT2, and may not be connected to the first upper contact electrode UCT1. Alternatively, the upper interconnect 320 may be connected to the first upper contact electrode UCT1 and the second upper contact electrode UCT2, respectively.

[0164] In addition, Figure 1 , Figure 2A , Figure 2B and Figure 2C In the embodiment, the upper interconnection 320 extends in a second direction D2 parallel to the direction in which the gate pattern GS extends, but the present disclosure is not limited thereto. For example, the upper interconnection 320 may extend in a first direction D1 intersecting the direction in which the gate pattern GS extends.

[0165] The upper interconnection insulating layer 310 may be disposed on the upper surface of the interlayer insulating layer 190. The upper interconnection insulating layer 310 may contact the upper surface of the interlayer insulating layer 190. The upper interconnection insulating layer 310 may cover the upper interconnection structure ML2. For example, the upper interconnection insulating layer 310 may cover the upper interconnection 320, and the upper interconnection 320 may be disposed within the upper interconnection insulating layer 310. The upper interconnection insulating layer 310 may contact the lower surface and the side surface of the upper interconnection 320. The upper interconnection insulating layer 310 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material.

[0166] The first upper contact electrode UCT1 may be disposed between the source / drain pattern 150 and the upper interconnection structure ML2 .

[0167] The first upper contact electrode UCT1 may be connected to at least one source / drain pattern 150. For example, the first upper contact electrode UCT1 may be connected to the first source / drain structure 151. The first upper contact electrode UCT1 may not be connected to the second source / drain structure 152. In the following description, a case where the first upper contact electrode UCT1 is connected to the first source / drain structure 151 but not to the second source / drain structure 152 will be described.

[0168] The first upper contact electrode UCT1 may be disposed at one side of the main gate structure M_GS. The first upper contact electrode UCT1 may be disposed on the source / drain pattern 150. For example, the first upper contact electrode UCT1 may be disposed on the first source / drain structure 151. The first upper contact electrode UCT1 may not be disposed on the second source / drain structure 152.

[0169] The first upper contact electrode UCT1 may penetrate at least one interlayer insulating layer 190. For example, the first upper contact electrode UCT1 may penetrate the interlayer insulating layer 190 on the first source / drain structure 151 and be connected to the first source / drain structure 151. The first upper contact electrode UCT1 may contact the first source / drain structure 151. The first upper contact electrode UCT1 may not penetrate the interlayer insulating layer 190 on the second source / drain structure 152. That is, the first upper contact electrode UCT1 may not be connected to the second source / drain structure 152.

[0170] The lower surface of the first upper contact electrode UCT1 may be disposed at a level similar to that of the upper surface of the fourth semiconductor pattern SP4 disposed at, for example, the uppermost portion of the channel pattern CP. However, the present disclosure is not limited thereto, and the lower surface of the first upper contact electrode UCT1 may be higher or lower than the lower surface of the fourth semiconductor pattern SP4 disposed at the uppermost portion of the channel pattern CP. Alternatively, the lower surface of the first upper contact electrode UCT1 may be disposed between the lower surface of the first semiconductor pattern SP1 disposed at the lowermost portion of the channel pattern CP and the lower surface of the fourth semiconductor pattern SP4 disposed at the uppermost portion.

[0171] The first upper contact electrode UCT1 may include a conductive pattern 210 and a barrier pattern 220 configured to surround the conductive pattern 210 .

[0172] The conductive pattern 210 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0173] The barrier pattern 220 may cover the sidewall and lower surface of the conductive pattern 210. The barrier pattern 220 may contact the sidewall and lower surface of the conductive pattern 210. The barrier pattern 220 may include a metal, a metal alloy, or a conductive metal nitride. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0174] Although the first upper contact electrode UCT1 is illustrated as a double layer including the conductive pattern 210 and the barrier pattern 220 , this is merely for convenience of explanation, and the present disclosure is not limited thereto.

[0175] A metal silicide layer (not shown) may be further disposed between the source / drain pattern 150 and the first upper contact electrode UCT1. The metal silicide layer may include metal silicide.

[0176] Figure 1 , Figure 2A , Figure 2B and Figure 2C It is shown that the first upper contact electrode UCT1 is disposed on the first source / drain structure 151, but not on the second source / drain structure 152, but the present disclosure is not limited thereto. For example, the first upper contact electrode UCT1 may be disposed on the first source / drain structure 151 and the second source / drain structure 152, respectively. The first upper contact electrode UCT1 may be connected to the first source / drain structure 151 and the second source / drain structure 152, respectively. In this case, the first upper contact electrode UCT1 connected to the second source / drain structure 152 may be a dummy contact electrode to which no electrical signal is applied.

[0177] The second upper contact electrode UCT2 may be disposed between the gate pattern GS and the upper interconnection structure ML2 .

[0178] The second upper contact electrode UCT2 may be connected to at least one gate pattern GS.

[0179] The second upper contact electrode UCT2 may be disposed at one side of the first upper contact electrode UCT1. The second upper contact electrode UCT2 may be disposed on the main gate structure M_GS.

[0180] The second upper contact electrode UCT2 may penetrate at least one capping layer 145. At least one capping layer 145 may contact a side surface of the second upper contact electrode UCT2. For example, the second upper contact electrode UCT2 may penetrate the capping layer 145 on at least one main gate structure M_GS and be connected to the main gate structure M_GS. The second upper contact electrode UCT2 may not penetrate the interlayer insulating layer 190 on the source / drain pattern 150. For example, the second upper contact electrode UCT2 may not be connected to the source / drain pattern 150.

[0181] The lower surface of the second upper contact electrode UCT2 may be disposed at a level similar to that of the upper surface of the main gate structure M_GS, for example. However, the present disclosure is not limited thereto, and the lower surface of the second upper contact electrode UCT2 may be disposed between the lower and upper surfaces of the main gate structure M_GS.

[0182] The second upper contact electrode UCT2 may include a conductive pattern 250 and a barrier pattern 260 configured to surround the conductive pattern 250 .

[0183] The conductive pattern 250 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0184] The barrier pattern 260 may cover the sidewalls and lower surface of the conductive pattern 250. The barrier pattern 260 may contact the sidewalls and lower surface of the conductive pattern 250. The barrier pattern 260 may include a metal, a metal alloy, or a conductive metal nitride. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0185] Although the second upper contact electrode UCT2 is illustrated as a double layer including the conductive pattern 250 and the barrier pattern 260 , this is merely for convenience of explanation, and the present disclosure is not limited thereto.

[0186] A metal silicide layer (not shown) may be further disposed between the main gate structure M_GS and the second upper contact electrode UCT2. The metal silicide layer may include metal silicide.

[0187] In the following, reference will be made to Figure 4A and Figure 4B A semiconductor device 10 according to another embodiment is described.

[0188] Figure 4A and Figure 4B FIG. 1 is a diagram showing a semiconductor device 10 according to an embodiment of the present invention. Figure 2A and Figure 2B The corresponding cross-sectional view.

[0189] because Figure 4A and Figure 4B The embodiment shown in FIG. Figure 2A and Figure 2B The embodiments shown in FIG. 1 are substantially the same components, so repeated description thereof will be omitted, and the differences will be mainly described.

[0190] Figure 2A and Figure 2B It is shown that the lower pattern layer 110 is disposed on the lower insulating layer 330 , and the first conductive type doped pattern layer 115 is disposed on the lower pattern layer 110 .

[0191] exist Figure 4A and Figure 4B In the embodiment, the first conductive type doped pattern layer 115 is disposed on the lower insulating layer 330, and the lower pattern layer 110 is not included.

[0192] As described later Fig.26A and Fig.26BAs shown in FIG. 1 , when a back side power distribution network (BSPDN) structure is applied in a method for manufacturing a semiconductor device 10 according to an embodiment, the lower pattern layer 110 is used as an etching stop layer (wet stop) to remove the entire substrate 100, and then the lower pattern layer 110 may also be selectively removed. Therefore, the manufactured semiconductor device 10 may not include the lower pattern layer 110 between the lower insulating layer 330 and the first conductive type doped pattern layer 115.

[0193] In this case, the lower contact electrode CT1 may penetrate the first conductive type doping pattern layer 115 and be connected to the second source / drain structure 152. For example, the lower contact electrode CT1 may contact a lower surface of the second source / drain structure 152.

[0194] In the following, reference will be made to FIG. 5A to FIG. 29B A method of manufacturing the semiconductor device 10 according to example embodiments is described.

[0195] FIG. 12A to FIG. 14B is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device 10 according to another example embodiment, Figures 15 to 19 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device according to another example embodiment, and Fig.29A and Fig.29B is a cross-sectional view illustrating an intermediate step of a method of manufacturing a semiconductor device according to another example embodiment.

[0196] like Figure 5A and Figure 5B As shown in FIG. 1 , a preliminary lower pattern layer 110P is formed on a substrate 100 .

[0197] The substrate 100 may include bulk silicon or silicon on insulator (SOI). Alternatively, the substrate 100 may include a silicon substrate or other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0198] The preliminary lower pattern layer 110P may include a first semiconductor material having an etching selectivity with respect to the substrate 100. For example, the first semiconductor material may include silicon (Si), germanium (Ge), or a combination thereof, and carbon (C), for example, the first semiconductor material may include germanium (Ge) of about 0 at % to about 31.5 at %, carbon (C) of greater than about 0 at % and less than or equal to about 2 at %, and the remainder of silicon (Si). Carbon (C) may be included in an amount of about 0.1 at % to about 1 at %.

[0199] Subsequently, a preliminary sacrificial lower pattern UBP_P and an upper pattern U_AP are formed on the preliminary lower pattern layer 110P.

[0200] A preliminary sacrificial lower pattern UBP_P may be disposed on the preliminary lower pattern layer 110P, and an upper pattern U_AP may be disposed on the preliminary sacrificial lower pattern UBP_P. The upper pattern U_AP may include sacrificial layers SC_L and semiconductor layers ACT_L alternately stacked on the substrate 100 .

[0201] For example, the preliminary sacrificial lower pattern UBP_P may include silicon (Si), the sacrificial layer SC_L may include silicon germanium (SiGe), and the semiconductor layer ACT_L may include silicon (Si).

[0202] like Fig. 6A and Figure 6B As shown in FIG. 1 , a sacrificial active pattern AP_P is formed on a substrate 100 .

[0203] The substrate 100 has a trench defining the sacrificial active pattern AP_P, and a field insulation layer 105 may be disposed in the trench.

[0204] The sacrificial active patterns AP_P may have a sheet shape or a fin shape. The sacrificial active patterns AP_P may extend longitudinally along the first direction D1 and may be spaced apart from each other along the second direction D2.

[0205] The sacrificial active pattern AP_P may be formed by etching a portion of the substrate 100 , or may be formed by etching an epitaxial layer grown from the substrate 100 .

[0206] A field insulating layer 105 may be disposed on the substrate 100. The field insulating layer 105 may be disposed to fill the trench.

[0207] For example, a field insulating layer 105 may be provided on the sidewall of the sacrificial active pattern AP_P. The field insulating layer 105 is not provided on the upper surface of the sacrificial active pattern AP_P. The field insulating layer 105 may completely cover the side surface of the sacrificial active pattern AP_P. Alternatively, the field insulating layer 105 may cover a portion of the sidewall of the sacrificial active pattern AP_P. In this case, a portion of the sacrificial active pattern AP_P may protrude from the upper surface of the field insulating layer 105 in the third direction D3.

[0208] The field insulating layer 105 may include an insulating material, and may include, for example, oxide, nitride, oxynitride, or a combination thereof. Although the field insulating layer 105 is illustrated as a single layer, this is merely for convenience of explanation, and the present disclosure is not limited thereto.

[0209] As the sacrificial active pattern AP_P is formed, a lower pattern layer 110 and a sacrificial lower pattern UBP may be formed from the preliminary lower pattern layer 110P and the preliminary sacrificial lower pattern UBP_P.

[0210] Subsequently, a preliminary gate insulating layer 130P, a preliminary main gate electrode 120MP, and a preliminary capping layer 120_HM are formed on the upper pattern U_AP.

[0211] A preliminary gate insulating layer 130P may also be disposed on both side surfaces of the sacrificial active pattern AP_P and the upper pattern U_AP in the second direction D2.

[0212] The preliminary gate insulating layer 130P may include, for example, silicon oxide, but is not limited thereto. The preliminary main gate electrode 120MP may include, for example, polysilicon, but is not limited thereto. The preliminary capping layer 120_HM may include, for example, silicon nitride, but is not limited thereto.

[0213] A preliminary gate spacer 140P may be formed on both side surfaces of the preliminary main gate electrode 120MP.

[0214] The preliminary gate spacer 140P may also be disposed on both side surfaces of the sacrificial active pattern AP_P and the upper pattern U_AP in the second direction D2. In addition, when the preliminary gate insulating layer 130P is disposed on both side surfaces of the sacrificial active pattern AP_P and the upper pattern U_AP in the second direction D2, the preliminary gate spacer 140P may be disposed on the surface of the preliminary gate insulating layer 130P. The preliminary gate spacer 140P disposed on both side surfaces of the sacrificial active pattern AP_P and the upper pattern U_AP in the second direction D2 becomes a second spacer 141.

[0215] like Fig. 7A and Figure 7B As shown in FIG. 1 , at least a portion of the upper pattern U_AP is etched using the preliminary capping layer 120_HM and the preliminary gate spacer 140P as a mask to form a source / drain groove 150R. A portion of the source / drain groove 150R may be formed within the sacrificial active pattern AP_P.

[0216] When the source / drain grooves 150R are formed, the semiconductor layer ACT_L is separated to form semiconductor patterns SP1, SP2, SP3, and SP4, and the semiconductor patterns SP1, SP2, SP3, and SP4 may be disposed between the source / drain grooves 150R. The semiconductor patterns SP1, SP2, SP3, and SP4 and the sacrificial layer SC_L may be alternately stacked in the third direction D3.

[0217] Furthermore, when the source / drain grooves 150R are formed, the preliminary gate insulating layer 130P disposed on the side surfaces of the source / drain grooves 150R is removed together, and the preliminary gate insulating layer 130P remaining at the side surfaces of the sacrificial active pattern AP_P may become the first spacer 130 .

[0218] In addition, when the source / drain groove 150R is formed, a portion of the second spacer 141 may be etched. Therefore, the second spacer 141 may cover the entire surface of the source / drain pattern 150, but is not limited thereto, and the second spacer 141 may cover a portion of the side surface of the source / drain pattern 150. In other words, the top height of the second spacer 141 in the third direction D3 may be the same as the top height of the source / drain pattern 150 in the third direction D3, or lower than the top height of the source / drain pattern 150 in the third direction D3.

[0219] like Fig. 8A and Figure 8B As shown in FIG. 1 , third spacers 142 may be formed on side surfaces of the semiconductor patterns SP1 , SP2 , SP3 , and SP4 , the sacrificial layer SC_L, and the preliminary gate spacers 140P.

[0220] The third spacer 142 is formed by first forming a preliminary third spacer on the preliminary capping layer 120_HM, the semiconductor patterns SP1, SP2, SP3 and SP4, the sacrificial layer SC_L, the preliminary gate spacer 140P, the field insulating layer 105 and the sacrificial lower pattern UBP, and then removing the upper surface of the preliminary third spacer through an etching process.

[0221] The third spacer 142 may cover the side surfaces of the semiconductor patterns SP1, SP2, SP3, and SP4 and the side surface of the sacrificial layer SC_L in the source / drain groove 150R, but not cover the upper surface of the sacrificial lower pattern UBP. The third spacer 142 may cover the side surface of the preliminary gate spacer 140P, but not cover the upper surface of the preliminary capping layer 120_HM.

[0222] The third spacer 142 may include silicon nitride. However, the present invention is not limited thereto, and the material of the third spacer 142 may be variously changed. For example, the third spacer 142 may be formed of SiOCN or the like.

[0223] like Fig.9A and Fig. 9B As shown in FIG. 1 , the sacrificial under pattern UBP disposed under the source / drain recess 150R and under the semiconductor patterns SP1 , SP2 , SP3 , and SP4 is selectively removed.

[0224] Here, instead of removing the semiconductor patterns SP1 , SP2 , SP3 , and SP4 , the sacrificial layer SC_L, and the preliminary gate spacer 140P, the sacrificial under pattern UBP may be removed exclusively in the region not covered by the third spacer 142 .

[0225] In addition, when removing the sacrificial lower pattern UBP, since the lower pattern layer 110 includes the first semiconductor material having an etching selectivity to the sacrificial lower pattern UBP and the substrate 100 , the lower pattern layer 110 may function as an etch stop layer (wet stop) to prevent etching of the substrate 100 .

[0226] For example, the sacrificial lower pattern UBP may be removed by using a wet etching process.

[0227] Here, the etching solution may be selected not to remove the first semiconductor material included in the lower pattern layer 110 but to remove the second semiconductor material included in the sacrificial lower pattern UBP.

[0228] In other words, the etching solution for removing the sacrificial lower pattern UBP may have a relatively higher etching rate for the second semiconductor material of the sacrificial lower pattern UBP than for the first semiconductor material of the lower pattern layer 110 .

[0229] For example, the first semiconductor material of the lower pattern layer 110 may include silicon (Si), germanium (Ge), and carbon (C) (SiGe:C), and the second semiconductor material of the sacrificial lower pattern UBP may include silicon (Si).

[0230] Here, the etching process is performed by using an etching solution having a higher etching rate for Si than for SiGe:C, thereby specifically etching the sacrificial lower pattern UBP. Therefore, the lower pattern layer 110 and the substrate 100 below the lower pattern layer 110 are not removed, but the sacrificial lower pattern UBP may be specifically removed. An empty space SS may be formed where the sacrificial lower pattern UBP is located.

[0231] On the other hand, in the process of exclusively removing the sacrificial lower pattern UBP, the preliminary gate insulating layer 130P may be partially or entirely removed. Here, a dent is formed where the preliminary gate insulating layer 130P is removed, and since at least some of the dents are filled with the source / drain pattern 150, the source / drain pattern 150 may be disposed at both side surfaces of the lower pattern layer 110 in the second direction D2. Fig. 10A and Fig. 10B As shown in FIG. 4 , the third spacer 142 is removed by an etching process.

[0232] As the third spacers 142 are removed, side surfaces of the semiconductor patterns SP1, SP2, SP3, and SP4 and side surfaces of the sacrificial layer SC_L are exposed in the source / drain grooves 150R. In addition, the third spacers 142 covering side surfaces of the preliminary gate spacers 140P are removed.

[0233] like Fig.11A and Fig. 11BAs shown in FIG. 1 , the first conductive type doped pattern layer 115 and the source / drain pattern 150 may be sequentially formed through one process.

[0234] The first conductive type doped pattern layer 115 and the source / drain pattern 150 may be formed by an epitaxial growth method. The upper surface of the lower pattern layer 110 and the inner wall of the source / drain groove 150R may be used as seeds. The inner wall of the source / drain groove 150R is composed of the side surfaces of the semiconductor patterns SP1, SP2, SP3, and SP4, the side surface of the sacrificial layer SC_L, and the upper surface of the lower pattern layer 110.

[0235] A first conductive type doped pattern layer 115 is formed in the empty space SS where the sacrificial lower pattern UBP is located, and a source / drain pattern 150 is formed in the source / drain groove 150R.

[0236] Here, the first conductive type doped pattern layer 115 is first formed, and then the source / drain pattern 150 is formed by controlling the growth rate along the plane direction of the wafer. For example, when the plane (100) of the wafer has a higher growth rate than the plane (110), as the epitaxial layer grows in the third direction D3, the first conductive type doped pattern layer 115 can be grown in the empty space SS where the sacrificial lower pattern UBP is located, and when the plane (110) of the wafer has a higher growth rate than the plane (100), as the epitaxial layer grows in the first direction D1, the source / drain pattern 150 can be grown in the source / drain groove 150R.

[0237] As described above, the first conductive type doped pattern layer 115 may include a semiconductor material doped with first conductive type impurities, and the source / drain pattern 150 may include a semiconductor material doped with second conductive type impurities different from the first conductive type impurities.

[0238] For example, when the source / drain patterns 150 include a semiconductor material doped with n-type impurities, the first conductive type doped pattern layer 115 may include a semiconductor material doped with p-type impurities.

[0239] In addition, when the source / drain pattern 150 includes a semiconductor material doped with p-type impurities, the first conductive type doped pattern layer 115 may include a semiconductor material doped with n-type impurities.

[0240] For example, when the source / drain pattern 150 includes a semiconductor material doped with n-type impurities and the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities, at the beginning of epitaxial growth, boron (B) can be used as an impurity gas under the condition that the plane (100) has a dominant growth rate, but in the later epitaxial growth, phosphorus (P) can be used as an impurity gas under the condition that the plane (110) has a dominant growth rate.

[0241] On the other hand, the first conductive type doped pattern layer 115 and the source / drain pattern 150 are not formed in one process sequence, but as shown in FIG. FIG. 12A to FIG. 14B As shown in FIG. 1 , after forming the first conductive type doping pattern layer 115 , a source / drain pattern 150 may be formed in a subsequent process.

[0242] Here, the third spacer 142 is not removed, but the first conductive type doping pattern layer 115 may be formed in the presence of the third spacer 142 .

[0243] For example, when the source / drain pattern 150 includes a semiconductor material doped with n-type impurities and the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities, the first conductive type doped pattern layer 115 can be formed by epitaxial growth using boron (B) as an impurity gas under the condition that the plane (100) has a dominant growth rate.

[0244] Then, if Fig.13A and Fig. 13B As shown in FIG. 1 , the third spacer 142 is removed by an etching process, and as shown in FIG. Fig.14A and Fig. 14B As shown in FIG. 1 , a source / drain pattern 150 is formed in the source / drain groove 150R. Here, a bottom surface of the source / drain groove 150R may be an upper surface of the first conductive type doped pattern layer 115 .

[0245] For example, when the source / drain pattern 150 includes a semiconductor material doped with n-type impurities and the first conductive type doped pattern layer 115 includes a semiconductor material doped with p-type impurities, the source / drain pattern 150 can be formed by epitaxial growth using phosphorus (P) as an impurity gas under the condition that the plane (110) has a dominant growth rate.

[0246] On the other hand, Fig.15 As shown in FIG. 1 , after forming the source / drain recesses 150R, a dent process for the sacrificial layer SC_L may be performed.

[0247] In the dent process, the sacrificial layer SC_L may be etched using a wet etching method or a dry etching method to further reduce the length of the sacrificial layer SC_L in the first direction (D1), thereby forming the dent 155. Therefore, the surface of the sacrificial layer SC_L contacting the source / drain groove 150R has a concave shape toward the source / drain groove 150R.

[0248] For example, when a wet etching method is used, an etching solution such as ammonia water may be used.

[0249] Then, if Figures 16 to 19 As shown in the figure, a third spacer 142 is formed on the side surfaces of the semiconductor patterns SP1, SP2, SP3 and SP4, the side surface of the sacrificial layer SC_L and the side surface of the preliminary gate spacer 140P, and then the sacrificial lower pattern UBP under the source / drain groove 150R is specifically removed by using an etching process to remove the third spacer 142.

[0250] However, even if the third spacer 142 is removed, the third spacer 142 inside the dent 155 remains, thereby forming an inner gate spacer 133 .

[0251] Subsequently, when the first conductive type doped pattern layer 115 and the source / drain pattern 150 are formed, as shown in FIG. Figure 3 As shown in , the inner gate spacer 133 may be disposed between the sacrificial layer SC_L and the source / drain pattern 150. In addition, as described later Fig.21 and Fig. 22 As shown in , after removing the sacrificial layer SC_L, a sub-gate structure S_GS is formed where the sacrificial layer SC_L was located, and an inner gate spacer 133 may be located between the sub-gate structure S_GS and the source / drain pattern 150 .

[0252] The inner gate spacer 133 may include a low dielectric constant material. The low dielectric constant material may include silicon oxide or a material having a dielectric constant lower than that of silicon oxide. For example, the low dielectric constant material may include silicon oxide, silicon oxide doped with fluorine or carbon, porous silicon oxide, or an organic polymer dielectric material. For another example, the inner gate spacer 133 may include at least one selected from silicon nitride, silicon carbonitride, silicon oxycarbon nitride, and silicon oxynitride.

[0253] Next, if Fig. 20A and Fig. 20B As shown in FIG. 1 , an etch stop layer 185 and an interlayer insulating layer 190 are sequentially formed on the source / drain pattern 150 .

[0254] Subsequently, a portion of the interlayer insulating layer 190, a portion of the etch stop layer 185, and the preliminary capping layer 120_HM are removed to expose the upper surface of the preliminary main gate electrode 120MP. While the upper surface of the preliminary main gate electrode 120MP is exposed, the gate spacer 140 may be formed.

[0255] like Fig.21 As shown in FIG. 1 , the preliminary gate insulating layer 130P and the preliminary main gate electrode 120MP disposed on the upper pattern U_AP are removed to expose the upper pattern U_AP between the gate spacers 140. Subsequently, a gate trench 120t is formed between the semiconductor patterns SP1, SP2, SP3, and SP4 and under the first semiconductor pattern SP1.

[0256] like Fig. 22 As shown in FIG. 1 , a sub-interface insulating layer 131S, a sub-gate insulating layer 132S, and a sub-gate electrode 120S may be sequentially formed in the gate trench 120t. In addition, a main interface insulating layer 131M, a main gate insulating layer 132M, a main gate electrode 120M, and a capping layer 145 may be sequentially formed.

[0257] like Fig.23A and Fig. 23B As shown in FIG. 1 , the first upper contact electrode UCT1 is formed in the interlayer insulating layer 190 .

[0258] First, a contact hole may be formed by penetrating the interlayer insulating layer 190 to expose the source / drain pattern 150. For example, a contact hole may be formed by penetrating the interlayer insulating layer 190 to expose the first source / drain structure 151. A contact hole exposing the second source / drain structure 152 may not be formed, but is not limited thereto.

[0259] Subsequently, a first upper contact electrode UCT1 filling the contact hole and electrically connected to the first source / drain structure 151 is formed. For example, in the contact hole, a barrier pattern 220 and a conductive pattern 210 are sequentially formed. Therefore, the first upper contact electrode UCT1 can be electrically connected to the first source / drain structure 151 by penetrating the interlayer insulating layer 190.

[0260] In addition, in the capping layer 145 , a second upper contact electrode UCT2 is formed.

[0261] First, a contact hole may be formed by penetrating the capping layer 145 to expose the main gate structure M_GS.

[0262] Subsequently, a second upper contact electrode UCT2 may be formed to fill the contact hole and electrically connected to the main gate structure M_GS. For example, in the contact hole, a barrier pattern 260 and a conductive pattern 250 are sequentially formed. Thus, the second upper contact electrode UCT2 may be electrically connected to the main gate structure M_GS by penetrating the capping layer 145.

[0263] like Fig.24A and Fig. 24B As shown in FIG. 1 , an upper interconnection structure ML2 electrically connected to the first upper contact electrode UCT1 is formed on upper surfaces of the interlayer insulating layer 190 and the capping layer 145. However, the present invention is not limited thereto, but the upper interconnection structure ML2 may be electrically connected to the second upper contact electrode UCT2.

[0264] The upper interconnection structure ML2 may include an upper interconnection 320 and an upper interconnection insulating layer 310 covering the upper interconnection 320 .

[0265] like Fig.25A and Fig.25B As shown in FIG. 1 , the semiconductor device 10 according to the embodiment is rotated.

[0266] For example, the rotated semiconductor device 10 may be disposed on a carrier substrate (not shown). Here, after the upper surface of the semiconductor device 10 is positioned to face the carrier substrate, the semiconductor device 10 may be attached to the carrier substrate. In other words, the upper interconnect structure ML2 on the upper surface of the semiconductor device 10 may be attached to the carrier substrate. An adhesive member (not shown) may be disposed between the upper interconnect structure ML2 and the carrier substrate.

[0267] The carrier substrate has substantially the same area as or larger than that of the semiconductor device 10. The carrier substrate may be, for example, a semiconductor wafer, a ceramic substrate, or a glass substrate. The bonding member may be formed as a film.

[0268] The bonding member may include a base film and an adhesive layer attached to both surfaces of the base film. The base film may be, for example, a polyethylene film (such as polyethylene terephthalate (PET) or polyethylene 2,6-naphthalate (PEN)) or a polyolefin film. The base film may be formed by coating a polyethylene film or a polyolefin film with silicone or Teflon (TEFLON, tetrafluoroethylene). The adhesive layer may be made of, for example, an acrylic polymer resin, an epoxy resin, or a mixture thereof.

[0269] like Fig.26A and Fig.26B As shown in FIG. 1 , the substrate 100 may be removed by performing an etching process. For example, the etching process may be performed by a wet etching method, but is not limited thereto.

[0270] In this case, since the lower pattern layer 110 includes a first semiconductor material having an etching selectivity with respect to the substrate 100, the lower pattern layer 110 can be used as an etching stop layer. For example, in a process of etching the substrate 100, if the lower pattern layer 110 is exposed, the etching process can be stopped. In this way, even when a back side power distribution network (BSPDN) structure is applied in a method for manufacturing a semiconductor device 10 according to an embodiment, in a process of removing the entire substrate 100, a BSPDN bodyless structure (a structure in which all silicon substrates are removed) can be easily realized via etching selectivity by using the lower pattern layer 110 as an etching stop layer (wet stop).

[0271] The etching process of the substrate 100 may be performed by using an etching solution having a relatively high etching rate for the substrate 100. For example, when the substrate 100 includes Si and the lower pattern layer 110 includes SiGe:C, the etching process may be performed by using an etching solution having a relatively high etching rate for Si.

[0272] When the substrate 100 is removed, the lower pattern layer 110 may be exposed.

[0273] like Fig.27A and Fig.27B As shown in , the lower insulating layer 330 may be formed to cover the lower pattern layer 110. Thus, the lower insulating layer 330 may contact the lower pattern layer 110.

[0274] The lower insulating layer 330 may be formed by forming a preliminary lower insulating layer to cover the lower pattern layer 110 and performing chemical mechanical polishing (CMP) to planarize an upper surface of the lower insulating layer 330 , but the present invention is not limited thereto.

[0275] exist FIG. 26A to FIG. 27B In the embodiment, after the substrate 100 is removed by an etching process, the lower insulating layer 330 is formed at the place where the substrate 100 is removed, but the present invention is not limited thereto and may be omitted. FIG. 26A to FIG. 27B For example, the substrate 100 may not be completely removed by etching, but a portion of the substrate 100 may be selectively removed by etching. Here, the substrate 100 may be patterned by photolithography and etching processes to expose the lower pattern layer 110. Alternatively, the substrate 100 may not be completely removed by an etching process, but a portion of the substrate 100 may be selectively removed to expose the lower pattern layer 110.

[0276] Subsequently, a portion of the lower insulating layer 330 is removed by photolithography and etching processes to form a contact hole exposing the second source / drain structure 152. Here, the contact hole may penetrate the lower pattern layer 110 and the first conductive type doped pattern layer 115. The side surface of the contact hole may be surrounded by the lower insulating layer 330, for example.

[0277] Subsequently, a lower contact electrode CT1 is formed to fill the contact hole and electrically connected to the second source / drain structure 152. For example, in the contact hole, a barrier pattern 240 and a conductive pattern 230 are sequentially formed. Therefore, the lower contact electrode CT1 can be electrically connected to the second source / drain structure 152 by penetrating the lower pattern layer 110 and the first conductive type doped pattern layer 115.

[0278] like Fig.28A and Fig.28B As shown in FIG. , on the lower surface of the lower insulating layer 330 (ie, Fig.28A and Fig.28B A lower interconnection structure ML1 electrically connected to the lower contact electrode CT1 is formed on an upper surface of the substrate 100 . The lower interconnection structure ML1 may include a lower interconnection 340 and a lower interconnection insulating layer 350 covering the lower interconnection 340 .

[0279] Subsequently, after removing the carrier substrate and the bonding member, the semiconductor device 10 is rotated, thereby forming Figure 1 , Figure 2A , Figure 2B and Figure 2C A semiconductor device 10 is provided.

[0280] On the other hand, in Fig.26A and Fig.26B After removing the substrate 100 as shown in FIG. Fig.29A and Fig.29B The lower pattern layer 110 is selectively removed as shown in FIG.

[0281] For example, when a back side power distribution network (BSPDN) structure is applied in the method of manufacturing the semiconductor device 10 according to the embodiment, the entire substrate 100 is removed using the lower pattern layer 110 as an etch stop layer (wet stop), and then the lower pattern layer 110 may also be selectively removed.

[0282] The lower pattern layer 110 may be removed using an etching process. The etching process may be performed by, for example, a wet etching method, but is not limited thereto.

[0283] The etching process of the lower pattern layer 110 may be performed by using an etching solution having a relatively high etching rate for the lower pattern layer 110. For example, when the lower pattern layer 110 includes SiGe:C, the etching process may be performed using an etching solution having a relatively high etching rate for SiGe:C.

[0284] Subsequently, after forming a lower insulating layer 330 to cover the first conductive type doped pattern layer 115 exposed by removing the lower pattern layer 110, forming a lower contact electrode CT1 electrically connected to the second source / drain structure 152, and forming a lower interconnection structure ML1 electrically connected to the lower contact electrode CT1 on the lower surface of the lower insulating layer 330, the semiconductor device 10 is rotated to form Figure 4A and Figure 4B A semiconductor device 10 is provided.

[0285] It will be understood that the invention is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0286] <Description of symbols>

[0287] 10: Semiconductor devices

[0288] 100: Base

[0289] 105: Field insulation layer

[0290] 110: Lower pattern layer

[0291] 115: first conductive type doped pattern layer

[0292] AP: Active Pattern

[0293] CP: Channel Pattern

[0294] SP1, SP2, SP3, SP4: Semiconductor pattern

[0295] GS: Gate pattern

[0296] M_GS: Main gate

[0297] 120M: Main grid electrode

[0298] 131M: Main interface insulation layer

[0299] 132M: Main gate insulation layer

[0300] S_GS: Sub-gate

[0301] 120S: Sub-gate electrode

[0302] 131S: Sub-interface insulation layer

[0303] 132S: Sub-gate insulation layer

[0304] 133: Inner gate spacer

[0305] 140: Gate spacer

[0306] 141: Second spacer

[0307] 142: Third spacer

[0308] 130: First spacer

[0309] 145: Overlay

[0310] 150: Source / Drain Pattern

[0311] 151: First source / drain structure

[0312] 152: Second source / drain structure

[0313] 150R: Source / Drain Recesses

[0314] 185: Etch stop layer

[0315] 190: Interlayer insulation layer

[0316] CT1: Lower contact electrode

[0317] 230: Conductive pattern

[0318] 240: Blocking Pattern

[0319] UCT1: First upper contact electrode

[0320] 210: Conductive pattern

[0321] 220: Blocking pattern

[0322] UCT2: Second upper contact electrode

[0323] 250: Conductive pattern

[0324] 260: Blocking Pattern

[0325] ML1: Lower interconnect structure

[0326] 350: Lower interconnect insulation layer

[0327] 340: Lower interconnect

[0328] ML2: Upper interconnect structure

[0329] 310: Upper interconnect insulation layer

[0330] 320: Upper interconnect

[0331] 330: Lower insulation layer

[0332] AP_P: Sacrificial active pattern

[0333] U_AP: Upper pattern

[0334] SC_L: Sacrificial layer

[0335] ACT_L: Semiconductor layer

[0336] UBP: Sacrifice the next pattern

[0337] UBP_P: Prepare to sacrifice the next pattern

[0338] 110P: Prepare the lower pattern layer

[0339] 120MP: Prepare the main grid electrode

[0340] 120_HM: Preparatory covering layer

[0341] 130P: Prepare the gate insulation layer

[0342] 140P: Preparing gate spacers

[0343] 155: Dent.

Claims

1. A semiconductor device, the semiconductor device include: a lower pattern layer comprising a first semiconductor material; a first conductive type doped pattern layer disposed on the lower pattern layer and comprising a semiconductor material doped with first conductive type impurities; a source / drain pattern disposed on the first conductive type doped pattern layer and comprising a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity; a channel pattern including a semiconductor pattern connected between the source / drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; as well as The gate pattern is disposed on the first conductive type doped pattern layer and between the source / drain patterns, and surrounds the channel pattern.

2. The semiconductor device according to claim 1, in, The first semiconductor material includes silicon, germanium, or a combination thereof and includes carbon.

3. The semiconductor device according to claim 2, in, The first semiconductor material includes 0 at % to 31.5 at % of germanium, greater than 0 at % and less than or equal to 2 at % of carbon, and a balance of silicon.

4. The semiconductor device according to claim 1, in, The second semiconductor material includes silicon, germanium or a combination thereof.

5. The semiconductor device according to claim 1, in, The first conductivity type impurity is an n-type impurity, and the second conductivity type impurity is a p-type impurity.

6. The semiconductor device according to claim 5, in, The n-type impurities include phosphorus, arsenic, antimony or a combination thereof, and The p-type impurities include boron, aluminum, gallium, indium or a combination thereof.

7. The semiconductor device according to claim 1, in, The first conductivity type impurity is a p-type impurity, and the second conductivity type impurity is an n-type impurity.

8. The semiconductor device according to claim 7, in, The n-type impurities include phosphorus, arsenic, antimony or a combination thereof, and The p-type impurities include boron, aluminum, gallium, indium or a combination thereof.

9. The semiconductor device according to claim 1, in, The first conductive type doped pattern layer is an epitaxial layer.

10. The semiconductor device according to claim 1, in, The gate pattern has a main gate portion disposed on the semiconductor pattern and a sub-gate portion disposed between the semiconductor patterns, and The semiconductor device further includes an inner gate spacer disposed between the sub-gate portion of the gate pattern and the source / drain pattern.

11. A semiconductor device, the semiconductor device include: a lower pattern layer comprising a first semiconductor material; a first conductive type doped pattern layer disposed on the lower pattern layer and comprising a semiconductor material doped with first conductive type impurities; a source / drain pattern disposed on the first conductive type doped pattern layer and comprising a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity; a channel pattern including a semiconductor pattern connected between the source / drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; A gate pattern is disposed on the first conductive type doped pattern layer and between the source / drain patterns and surrounds the channel pattern; as well as The lower contact electrode is disposed below the source / drain pattern and connected to the source / drain pattern by penetrating the lower pattern layer and the first conductive type doped pattern layer.

12. The semiconductor device according to claim 11, in, The source / drain pattern includes a first source / drain structure and a second source / drain structure spaced apart from each other, and The semiconductor device further includes a first upper contact electrode disposed on and connected to the first source / drain structure.

13. The semiconductor device according to claim 12, in, The lower contact electrode is disposed under the second source / drain structure and connected to the second source / drain structure.

14. The semiconductor device according to claim 12, in, The semiconductor device also includes a second upper contact electrode disposed on and connected to the gate pattern.

15. The semiconductor device according to claim 12, in, The semiconductor device also includes a lower interconnect structure disposed below the lower pattern layer.

16. The semiconductor device according to claim 12, in, The semiconductor device further includes an upper interconnection structure disposed on the source / drain pattern, the gate pattern, or a combination thereof.

17. The semiconductor device according to claim 12, in, The semiconductor device further includes a lower insulating layer disposed below the lower pattern layer, and The lower contact electrode also penetrates the lower insulating layer.

18. A semiconductor device, the semiconductor device include: A first conductive type doped pattern layer, comprising a semiconductor material doped with first conductive type impurities; a source / drain pattern disposed on the first conductive type doped pattern layer and comprising a semiconductor material doped with a second conductive type impurity different from the first conductive type impurity; a channel pattern including a semiconductor pattern connected between the source / drain patterns and spaced apart from each other; A gate pattern is disposed on the first conductive type doped pattern layer between the source / drain patterns and surrounds the channel pattern; as well as The lower contact electrode is disposed below the source / drain pattern and connected to the source / drain pattern by penetrating the first conductive type doped pattern layer.

19. The semiconductor device according to claim 18, in, The source / drain pattern includes a first source / drain structure and a second source / drain structure spaced apart from each other, The semiconductor device further comprises a first upper contact electrode disposed on and connected to the first source / drain structure, and The lower contact electrode is arranged below the second source / drain structure and connected to the second source / drain structure.

20. The semiconductor device according to claim 18, in, The semiconductor device further includes a lower insulating layer disposed below the first conductive type doped pattern layer, and The lower contact electrode also penetrates the lower insulating layer.

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