Silicon-based substrate, preparation method thereof and silicon-based heterojunction battery

Abstract

The invention relates to the technical field of solar cells, in particular to a silicon-based substrate, a preparation method of the silicon-based substrate and a silicon-based heterojunction cell. The preparation method of the silicon-based substrate provided by the embodiment of the invention comprises the following steps: providing a silicon wafer which comprises a front surface and a back surface which are oppositely arranged, and performing texturing on the front surface and / or the back surface; coating the texturing surface of the silicon wafer with a phosphorus source, heating the phosphorus source at the grid line area by adopting infrared laser so as to form a phosphorosilicate glass protection layer on the silicon wafer at the grid line area, and then removing the residual phosphorus source; performing alkali polishing on the silicon wafer with the phosphorosilicate glass protective layer to polish a non-grid line area; after alkali polishing, the phosphorosilicate glass protection layer is removed; and after the phosphorosilicate glass protective layer is removed, performing secondary texturing on the silicon wafer. According to the embodiment of the invention, the suede capable of selectively increasing the grid line area can be formed, thereby improving the binding force between the grid line and the power generation device, and improving the stability of the assembly.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a silicon-based substrate and a preparation method thereof, and a silicon-based heterojunction cell. Background Art

[0002] Silicon-based heterojunction solar cells have the characteristics of low recombination and high opening voltage, and have become a research hotspot in the field of photovoltaic cells. Silicon-based heterojunction solar cells have an amorphous hydrogen passivation layer, which has poor tolerance to high temperatures. The general process temperature does not exceed 250°C. Therefore, the silver paste for silicon-based heterojunction solar cells needs to use low-temperature curing silver paste without a sintering process, so the bonding force between the grid line and the velvet surface is relatively poor.

[0003] In actual industrial production, silicon-based substrates are often designed to be pyramid velvet-shaped. The reflectivity of small pyramid velvet is easy to control, and it has better optical properties than large pyramid velvet. The large pyramid has a larger specific surface area and a stronger bonding force with the gate line.

[0004] Currently, the selective texturing method mainly uses a deposition mask method of silicon oxide or silicon nitride, but it has high energy consumption and long process time, which is not conducive to reducing mass production costs.

[0005] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0006] The embodiments of the present application provide a silicon-based substrate and a preparation method thereof and a silicon-based heterojunction battery to solve the problem of a long time required for selective texturing using a mask method.

[0007] A first aspect of an embodiment of the present application provides a method for preparing a silicon-based substrate, comprising the following operations:

[0008] Providing a silicon wafer, the silicon wafer comprising a front side and a back side arranged opposite to each other, and texturing the front side and / or the back side;

[0009] Applying a phosphorus source to the textured surface of the silicon wafer, heating the phosphorus source at the gate line area with a laser to form a phosphorus silicon glass protective layer on the silicon wafer at the gate line area, and then removing the residual phosphorus source;

[0010] Performing alkali polishing on the silicon wafer with the phosphorus silicon glass protective layer to polish the non-gate line area;

[0011] After the alkali polishing, removing the phosphosilicate glass protective layer;

[0012] After removing the phosphosilicate glass protective layer, the silicon wafer is subjected to secondary texturing.

[0013] The first aspect of the embodiment of the present application provides a method for preparing a silicon-based substrate, firstly applying a phosphorus source to the surface of a textured silicon wafer, further using a laser to selectively heat the gate line area to form a phosphorus-silicate glass protective layer, during alkali polishing, the presence of the phosphorus-silicate glass protective layer can prevent the alkali solution from corroding the velvet surface, and then a second texture is performed to form a velvet surface, which selectively increases the gate line area, can improve the bonding force between the gate line and the silicon-based substrate, and improve the stability of the component. Compared with the traditional deposition mask method, the preparation method of the embodiment of the present application does not require the setting of masks, development and other operations, and is faster and more efficient.

[0014] The second aspect of the embodiment of the present application provides a silicon-based substrate, which is prepared according to the first aspect of the embodiment of the present application. Thus, the surface of the gate line region is selectively increased, and an intrinsic amorphous silicon layer, an N-type microcrystalline silicon layer and an ITO layer are subsequently deposited on the front side of the silicon-based substrate, and an intrinsic amorphous silicon layer, a P-type microcrystalline silicon layer and an ITO layer are deposited on the back side of the silicon-based substrate to obtain a power generation device, which still maintains the selective increase of the surface of the gate line region, and can improve the bonding force between the gate line and the power generation device.

[0015] The third aspect of the embodiment of the present application provides a silicon-based heterojunction battery, comprising the silicon-based substrate of the second aspect of the embodiment of the present application. Thus, the bonding force between the gate line and the power generation device is improved, which is conducive to improving the stability of the component. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0017] Figure 1 is a flow chart of a method for preparing a silicon-based substrate provided in an embodiment;

[0018] Figure 2 is a schematic diagram of the structure of a silicon wafer provided in an embodiment;

[0019] Figure 3 is a schematic diagram of the structure of a phosphorus source for coating a silicon wafer provided in an embodiment;

[0020] Figure 4 is a schematic diagram of a structure in which a silicon wafer provided in an embodiment is covered with a phosphorus silicon glass protective layer;

[0021] Figure 5 is a schematic diagram of the structure of a polished silicon wafer covered with a phosphorus silicon glass protective layer provided in an embodiment;

[0022] Figure 6 is a schematic diagram of the structure of removing the phosphorus silicon glass protective layer after polishing the silicon wafer provided in the embodiment;

[0023] Figure 7 : is a schematic structural diagram of a silicon wafer secondary texturing process for removing a phosphorus-silicon glass protective layer provided in an embodiment;

[0024] Figure 8 It is a schematic diagram of the structure of a silicon-based heterojunction battery provided in an embodiment.

[0025] Description of reference numerals:

[0026] 1-silicon wafer; 2-phosphorus source layer; 3-phosphorus silicon glass protective layer; 4-gate line electrode; 5-power generation device. DETAILED DESCRIPTION

[0027] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0028] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. When the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0029] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0032] The embodiments of the present application provide a silicon-based substrate and a method for preparing the same, and a silicon-based heterojunction battery. See below for details.

[0033] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0034] In a first aspect, the present invention provides a method for preparing a silicon-based substrate. Figure 1 , the method for preparing a silicon-based substrate comprises the following operations:

[0035] S100, providing a silicon wafer, wherein the silicon wafer comprises a front side and a back side arranged opposite to each other, and texturing is performed on the front side and / or the back side. Figure 2 As shown, Figure 2 The front and back sides of the silicon wafer 1 are both textured. Figure 2 It can be seen that both the front and back sides are pyramid velvet, and the velvet is relatively uniform, with no distinction between grid lines and non-grid lines. The inventor found that the reflectivity of the small pyramid velvet is easy to control, and it has better optical properties than the large pyramid velvet, while the large pyramid has a larger specific surface area and a stronger bonding force with the grid lines. Based on this, selective velveting is proposed.

[0036] S200, applying a phosphorus source to the textured surface of the silicon wafer, heating the phosphorus source at the gate line region with a laser to form a phosphorus silicon glass protective layer on the silicon wafer at the gate line region, and then removing the remaining phosphorus source, thereby facilitating subsequent selective texture.

[0037] In some specific embodiments, the phosphorus source can be at least one of trimethylphosphine, triethyl phosphate, etc., and the phosphorus source is coated and then laser sintered to form a phosphorus silicate glass protective layer. Compared with the use of a phosphorus source for doping to form a phosphorus silicate glass protective layer, it has the advantage or characteristics of selectively masking the silicon wafer. Specifically, if a furnace tube doping or chain doping method is used, a heavily doped layer of 0.5μm-1.2μm will be generated under the phosphorus silicate glass. This heavily doped layer can only be removed by polishing or re-texturing, and polishing after the velvet is formed will damage the velvet. Laser can be used to quickly perform selective masking on the surface of the silicon wafer, which is more efficient and easy to implement. Further, the wavelength of the laser used is 900nm to 1600nm, for example, 900nm, 1000nm, 1300nm, 1600nm, etc. Specifically, a laser is used to heat the phosphorus source at the gate line area to form a phosphorus silicate glass protective layer on the silicon wafer at the gate line area. A light intensity of 20W / mm 2 ~200W / mm 2 , the illumination duration is 0.5s to 5s; for example, the illumination intensity can be 20W / mm 2 , 50W / mm 2 , 100W / mm 2 , 150W / mm 2 , 200W / mm 2etc.; the illumination time can be 0.5s, 1s, 3.5s, 5s, etc. Thus, the phosphorus source and the silicon wafer can be melted to form a phosphorus-silicon glass protective layer at the contact point, without damaging the silicon wafer deeper inside. Furthermore, the thickness of the phosphorus-silicon glass protective layer is 10nm to 100nm, for example, 10nm, 30nm, 50nm, 100nm, etc. Thus, it can protect the velvet surface and facilitate subsequent cleaning.

[0038] In some specific embodiments, removing the residual phosphorus source includes ultrasonic cleaning in water or a cleaning solution to remove the residual phosphorus source; the cleaning solution includes a mixture of ammonia water, hydrogen peroxide and water. Thus, the residual phosphorus source is cleaned away. As an optional technical solution of the present application, the cleaning solution is SC1 liquid, which is composed of ammonia water, hydrogen peroxide and water, and the volume ratio of ammonia water, hydrogen peroxide and water is 1:2:50. Thus, the cleaning is cleaner.

[0039] In some specific embodiments, a phosphorus source is applied to the textured surface of the silicon wafer to form a structure as shown in FIG. Figure 3 It can be seen that the textured surface of the silicon wafer 1 is covered with a phosphorus source layer 2. After the phosphorus source is coated, the phosphorus source at the gate line area is heated by laser to form a phosphorus silicon glass protective layer on the silicon wafer at the gate line area, and then the residual phosphorus source is removed. Figure 4 It can be seen that a phosphorus-silicate glass protective layer 3 is partially provided on the textured surface of the silicon wafer 1, and the corresponding part is the gate line area.

[0040] S300, alkali polishing is performed on the silicon wafer with the phosphosilicate glass protective layer to polish the non-gate line area. Thus, the area not covered by the phosphosilicate glass protective layer 3 is polished to achieve flatness, and the presence of the phosphosilicate glass protective layer prevents the alkali solution from corroding the velvet surface, so that the velvet surface is preserved.

[0041] In some specific embodiments, the silicon wafer with the phosphorus silicate glass protective layer is subjected to alkali polishing, comprising: using an alkali solution with a pH of 12 to 14, immersing the silicon wafer with the phosphorus silicate glass protective layer in the alkali solution, and placing it for 100s to 500s to complete the alkali polishing. For example, the pH may be 12, 13, 13.5, 14, etc.; the placement time may be 100s, 200s, 300s, 450s, 500s, etc. Thus, the anisotropy factor of the alkali solution etching at this concentration is low, and the (111), (100), and (011) crystal planes of the silicon crystal are etched simultaneously to form a relatively smooth surface. Preferably, a polishing agent may be added when the alkali solution is used for polishing. Thus, the velvet structure is retained in the area where the grid lines are printed, and the remaining areas are polished surfaces.

[0042] In some specific embodiments, the structure diagram of the silicon wafer with the phosphorus silicon glass protective layer after alkali polishing is as follows: Figure 5As shown, it can be seen that the velvet surface of the silicon wafer 1 covered by the phosphorus silicon glass protective layer 3 is retained, while the velvet surface of the silicon wafer 1 at other positions is a polished surface.

[0043] S400, after the alkali polishing, removing the phosphosilicate glass protective layer, thereby exposing the textured surface of the silicon wafer covered by the phosphosilicate glass protective layer, which is convenient for subsequent secondary texturing.

[0044] In some specific embodiments, an acid solution with a pH of 1 to 3 may be used to clean the silicon wafer so as to remove the phosphorus-silicate glass protective layer while not affecting other areas of the silicon wafer.

[0045] Furthermore, the acid solution includes at least one of hydrofluoric acid and hydrochloric acid.

[0046] S500, after removing the phosphorus-silicon glass protective layer, performing secondary texturing on the silicon wafer, so that the polishing area forms a primary texturing surface, and the gate line area forms a secondary texturing surface, so that the pyramid size of the gate line area is larger, and the adhesion of subsequent metal gate lines is better.

[0047] In some specific embodiments, see Figure 7 It can be seen that the secondary texturing surface of the silicon wafer 1 is significantly larger than the primary texturing surface. For example, the size of the pyramid base in the area outside the gate line is about 1.5μm to 2μm, while the size of the secondary texturing base can reach 6μm to 10μm. Thus, selective texturing is achieved.

[0048] The second aspect of the embodiment of the present application provides a silicon-based substrate, which is prepared according to the preparation method of the first aspect of the embodiment of the present application. Thus, under the condition of maintaining a low velvet reflectivity, the velvet surface in the grid line area is selectively increased, which can increase the bonding force between the grid line and the power generation device, thereby improving the stability of the photovoltaic module.

[0049] The third aspect of the embodiment of the present application provides a silicon-based heterojunction battery, comprising the silicon-based substrate of the second aspect of the embodiment of the present application, thereby increasing the bonding force between the gate line and the power generation device and improving the stability of the photovoltaic module.

[0050] In some specific embodiments, see Figure 8 , a plurality of functional layers are arranged on the silicon wafer 1, and a gate electrode 4 is arranged on the outer side of the functional layer, and the gate electrode 4 can be obtained by screen printing and curing. Therefore, the secondary textured surface is more conducive to the bonding of the gate line. Further, the silicon wafer 1 is an N-type silicon wafer, and the functional layer on the front side thereof may include an intrinsic amorphous silicon layer, an N-type amorphous silicon layer and a front tin-doped indium oxide (ITO), and the functional layer on the front side may include an intrinsic amorphous silicon layer, a P-type amorphous silicon layer and a back ITO. Thus, it is used as a photovoltaic heterojunction solar cell.

[0051] The following will conduct performance tests on the preparation method of the silicon-based heterojunction battery provided in the embodiments of the present application and related comparative examples.

[0052] [Example 1]

[0053] The specific preparation process of the preparation method of silicon-based heterojunction battery is as follows:

[0054] S100: Texturing is performed on both sides of the silicon wafer 1 to form pyramids of uniform size.

[0055] The velvet is made by alkaline liquid velvet method. During the velvet making, velvet additives are added. The size of the pyramid base is 4μm to 8μm. Figure 2 shown.

[0056] S200: coating a phosphorus source on the textured silicon wafer 1 to form a phosphorus source layer 2, such as Figure 3 The area where the grid lines are to be printed is continuously irradiated with a laser of wavelength 1064nm and the light intensity is 40W / mm 2 The time is 4s, and the phosphorus source in the irradiated area reacts with silicon to form a phosphorus-silicon glass protective layer 3, such as Figure 4 . Then, the silicon wafer is placed in SC1 solution and deionized water for ultrasonic cleaning to remove the phosphorus source;

[0057] S300: Place the silicon wafer 1 in NaOH with a pH of 12, add a polishing agent and polish it. Place it for 100 seconds and then take it out. Keep the velvet structure in the area where the gate lines are printed, and the rest of the area is polished. Figure 5 .

[0058] S400: using a mixture of hydrofluoric acid and hydrochloric acid with a pH of 3 to clean the silicon wafer 1 and remove the phosphorus silicon glass protective layer 3, such as Figure 5 .

[0059] S500: The silicon wafer 1 is subjected to secondary texturing, and the size of the pyramid base in the non-grid line area is about 1.5μm to 2μm, while the size of the pyramid base in the printed grid line area can reach 6μm to 10μm after the secondary texturing. Figure 7 shown.

[0060] In addition, the single-side thinning amount of the secondary texturing is about 4μm-6μm, while the diffusion depth of the heavily doped phosphorus area formed in S200 is less than 1μm, and the heavily doped phosphorus area is easy to be removed.

[0061] S600: a 15nm intrinsic amorphous silicon layer, a 20nm N-type microcrystalline silicon layer and a 100nm ITO layer are deposited on the front side of the silicon wafer 1, and a 10nm intrinsic amorphous silicon layer, a 15nm P-type microcrystalline silicon layer and a 120nm ITO layer are deposited on the back side of the silicon wafer 1 to obtain a power generation device 5; then, low-temperature silver paste is screen-printed on both sides, and after curing, a gate electrode 4 is obtained. Figure 8shown.

[0062] [Example 2]

[0063] The other operations are the same as those in Example 1, except that, S200: coating a phosphorus source on the textured silicon wafer 1 to form a phosphorus source layer 2, such as Figure 3 The area where the grid lines are to be printed is continuously irradiated with a laser of wavelength 1064nm and the light intensity is 100W / mm 2 The phosphorus source in the irradiated area reacts with silicon to form a phosphorus-silicon glass protective layer 3 for 2 seconds. Figure 4 The silicon wafer was then placed in SC1 solution and deionized water for ultrasonic cleaning to remove the phosphorus source.

[0064] [Example 3]

[0065] The other operations are the same as those in Example 1, except that, S200: coating a phosphorus source on the textured silicon wafer 1 to form a phosphorus source layer 2, such as Figure 3 The area where the grid lines are to be printed is continuously irradiated with a laser of 1064 nm in wavelength and a light intensity of 200 W / mm 2 The phosphorus source in the irradiated area reacts with silicon to form a phosphorus-silicon glass protective layer 3 for 0.8 s. Figure 4 The silicon wafer was then placed in SC1 solution and deionized water for ultrasonic cleaning to remove the phosphorus source.

[0066] [Example 4]

[0067] The other operations are the same as those in Example 1, except that, in S500, the silicon wafer 1 is subjected to secondary texturing to form a pyramid base having a size of about 1.5 μm to 2 μm in the non-gate line area, and the base of the pyramid can reach 4 μm to 8 μm after secondary texturing in the gate line area. Figure 7 shown.

[0068] [Comparative Example 1]

[0069] The rest is the same as that of Example 1, except that S200 to S500 are not included.

[0070]

Test example

[0071] The silicon-based heterojunction cells of Examples 1 to 4 and Comparative Example 1 were subjected to a gate line pull-off force test. The test conditions were: DK S03 slurry was used for printing, and the welding ribbon was Sn made by Suzhou Yubang New Materials Co., Ltd. 43 Pb 43 Bi 14 The circular solder strip and the solder flux are both PV201 produced by Vituo New Materials Co., Ltd. The soldering temperature is 290°C. The bonding strength between the power generation device and the gate electrode is obtained by a pull-off force tester. The results are shown in Table 1.

[0072] Table 1:

[0073]

[0074] It can be seen from Table 1 that the average pull-off force values ​​of multiple test points of Examples 1 to 4 are greater than that of Comparative Example 1; after multi-point testing, the qualified rates are different under different pull-off forces, for example, when the pull-off force of Example 1 is 0.8N, the qualified rate is 92%; under different pull-off forces, the qualified rates of Examples 1 to 4 are better than that of Comparative Example 1, indicating that the selective texturing of the preparation method of the present application can increase the bonding force between the power generation device and the gate line electrode.

[0075] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0076] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0077] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a silicon-based substrate, characterized in that: The following operations are included: Providing a silicon wafer, the silicon wafer comprising a front side and a back side arranged opposite to each other, and texturing the front side and / or the back side; Applying a phosphorus source to the textured surface of the silicon wafer, heating the phosphorus source at the gate line area with a laser to form a phosphorus silicon glass protective layer on the silicon wafer at the gate line area, and then removing the residual phosphorus source; Performing alkali polishing on the silicon wafer with the phosphorus silicon glass protective layer to polish the non-gate line area; After the alkali polishing, removing the phosphosilicate glass protective layer; After removing the phosphosilicate glass protective layer, the silicon wafer is subjected to secondary texturing.

2. The method for preparing a silicon-based substrate according to claim 1, characterized in that: The phosphorus source includes trimethyl phosphine and / or triethyl phosphate.

3. The method for preparing a silicon-based substrate according to claim 1, characterized in that: The wavelength of the laser is 900nm-1600nm.

4. The method for preparing a silicon-based substrate according to claim 3, characterized in that: The step of heating the phosphorus source at the gate line region by using laser comprises: The laser light intensity is 20W / mm 2 ~200W / mm 2 ; and / or The laser illumination duration is 0.5s to 5s.

5. The method for preparing a silicon-based substrate according to any one of claims 1 to 4, characterized in that: The removal of residual phosphorus source comprises: Ultrasonic cleaning in water or cleaning fluid to remove residual phosphorus sources; The cleaning solution includes a mixture of ammonia water, hydrogen peroxide and water.

6. The method for preparing a silicon-based substrate according to any one of claims 1 to 4, characterized in that: The silicon wafer with the phosphosilicate glass protective layer is subjected to alkali polishing, comprising: The silicon wafer with the phosphorus-silicon glass protective layer is immersed in an alkaline solution with a pH value of 12 to 14 and left for 100 to 500 seconds to complete alkaline polishing.

7. The method for preparing a silicon-based substrate according to any one of claims 1 to 4, characterized in that: The removing of the phosphosilicate glass protective layer comprises: The silicon wafer is cleaned with an acid solution having a pH value of 1 to 3.

8. The method for preparing a silicon-based substrate according to claim 7, characterized in that: The acid solution includes at least one of hydrofluoric acid and hydrochloric acid.

9. A silicon-based substrate, characterized in that: Prepared according to the preparation method according to any one of claims 1 to 8.

10. A silicon-based heterojunction battery, characterized in that: Comprising the silicon-based substrate as described in claim 9.

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