Voltage converter and mode switching circuit and chip thereof

Abstract

The invention discloses a voltage converter and a mode switching circuit and a chip thereof, and the mode switching circuit comprises a voltage clamping unit which is suitable for being connected with a load circuit of the voltage converter so as to generate a clamping current according to a first reference voltage and a feedback voltage outputted by the load circuit; a controllable switch unit and a compensation capacitor, the input end of the controllable switch unit is connected with the output end of the voltage clamping unit, and the output end of the controllable switch unit is connected with one end of the compensation capacitor, so that the clamping current is provided for the compensation capacitor according to a preset time interval, and the compensation capacitor is charged; and the frequency generation unit is connected with one end of the compensation capacitor so as to generate a frequency signal, and carries out frequency reduction control on the frequency signal according to the upper pole plate voltage of the compensation capacitor, so that the voltage converter is switched from a pulse width modulation mode to a pulse frequency modulation mode. According to the circuit, the equivalent average current is reduced, a compensation capacitor with a small capacitance value can be selected, and the size of the DC-DC converter is effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of power management circuits, and in particular to a voltage converter and a mode switching circuit and chip thereof. Background Art

[0002] DC-DC (Direct Current - Direct Current) converters usually have three modulation modes, namely PWM (Pulse Width Modulation), PFM (Pulse Frequency Modulation) and PSM (Pulse Skip Modulation). In order to make the DC-DC converter have higher efficiency in a wider load range, the PWM mode and PFM mode are seamlessly switched through the technology. The PWM module is used when the load is large, and the PFM mode is used under light load to improve the conversion efficiency, thereby achieving a smooth transition between the two modes to reduce the output voltage ripple when the mode is switched.

[0003] However, when switching between PWM mode and PFM mode, the loop characteristics change significantly. Under certain working conditions, the PWM mode and PFM mode switching technology requires the addition of a large capacitor to compensate the PFM loop, thereby avoiding the risk of loop oscillation. However, the capacitance of the large capacitor is usually tens of nanofarads, and the size is large, making it difficult to achieve on-chip integration. Therefore, the large capacitor occupies a large space, which increases the size of the DC-DC converter. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art to at least a certain extent. To this end, the first object of the present invention is to provide a mode switching circuit of a voltage converter, which reduces the equivalent average current by providing a clamping current to a compensation capacitor at a preset time interval, so that a compensation capacitor with a smaller capacitance can be selected, effectively reducing the volume of the capacitor, thereby reducing the volume of the DC-DC converter.

[0005] A second objective of the present invention is to provide a voltage converter.

[0006] The third objective of the present invention is to provide a chip.

[0007] To achieve the above-mentioned purpose, according to an embodiment of the first aspect of the present invention, a mode switching circuit of a voltage converter is proposed, comprising: a voltage clamping unit, the input end of the voltage clamping unit is suitable for connecting to a load circuit of the voltage converter, the voltage clamping unit is configured to generate a clamping current according to a first reference voltage and a feedback voltage output by the load circuit, so as to clamp the difference between the first reference voltage and the feedback voltage to a second reference voltage; a controllable switch unit and a compensation capacitor, the input end of the controllable switch unit is connected to the output end of the voltage clamping unit, the output end of the controllable switch unit is connected to one end of the compensation capacitor, and the other end of the compensation capacitor is grounded, the controllable switch unit is configured to provide the clamping current to the compensation capacitor at a preset time interval, so as to charge the compensation capacitor; a frequency generating unit, the input end of the frequency generating unit is connected to one end of the compensation capacitor, the frequency generating unit is configured to generate a frequency signal, and perform frequency reduction control on the frequency signal according to the upper plate voltage of the compensation capacitor, so as to switch the voltage converter from a pulse width modulation mode to a pulse frequency modulation mode.

[0008] According to an embodiment of the present invention, a mode switching circuit includes a voltage clamping unit, a controllable switch unit, a compensation capacitor and a frequency generating unit, wherein the input end of the voltage clamping unit is suitable for connecting to a load circuit of a voltage converter, the voltage clamping unit is configured to generate a clamping current according to a first reference voltage and a feedback voltage output by the load circuit, so as to clamp the difference between the first reference voltage and the feedback voltage at a second reference voltage, the input end of the controllable switch unit is connected to the output end of the voltage clamping unit, the output end of the controllable switch unit is connected to one end of the compensation capacitor, and the other end of the compensation capacitor is grounded, the controllable switch unit is configured to provide the clamping current to the compensation capacitor at a preset time interval, so as to charge the compensation capacitor, the input end of the frequency generating unit is connected to one end of the compensation capacitor, the frequency generating unit is configured to generate a frequency signal, and perform frequency reduction control on the frequency signal according to the upper plate voltage of the compensation capacitor, so as to switch the voltage converter from a pulse width modulation mode to a pulse frequency modulation mode. Therefore, when the clamping current is not generated, the upper plate voltage of the compensation capacitor is always 0, so the voltage converter operates in the pulse width modulation mode. When the load is small, the voltage clamping unit generates the clamping current, and the controllable switch unit provides the clamping current to the compensation capacitor at a preset time interval to charge the compensation capacitor, thereby reducing the equivalent average charging current of the compensation capacitor. Therefore, the compensation capacitor can use a capacitor with a smaller capacitance. After the compensation capacitor is charged, the upper plate voltage changes, so that the frequency generation unit performs frequency reduction control on the frequency signal, thereby realizing the switch from the pulse width modulation mode to the pulse frequency modulation mode. Therefore, loop compensation can be achieved using a small capacitor, which effectively reduces the volume of the capacitor, thereby reducing the volume of the DC-DC converter.

[0009] According to an embodiment of the present invention, the compensation capacitor is integrated inside the chip of the voltage converter.

[0010] According to one embodiment of the present invention, the frequency generating unit includes: a clock oscillator, which is configured to generate a frequency signal; a frequency control module, wherein a first input end of the frequency control module is connected to one end of the compensation capacitor, a second input end of the frequency control module is connected to the output end of the clock oscillator, and the frequency control module is configured to generate a delay signal according to the upper plate voltage and the frequency signal; a logic operation module, wherein a first input end of the logic operation module is connected to an input end of the frequency control module, a second input end of the logic operation module is connected to the output end of the clock oscillator, and the output end of the logic operation module is connected to the input end of the clock oscillator, and the logic operation module is configured to shield the frequency signal using the delay signal to reduce the frequency signal, and provide the reduced frequency signal to the clock oscillator so that the clock oscillator generates a frequency signal according to the reduced frequency signal.

[0011] According to one embodiment of the present invention, the frequency control module includes: a current generating submodule, the input end of the current generating submodule is connected to one end of the capacitor to generate a first current signal according to the upper plate voltage, wherein the first current signal is used to characterize the clamping current; a first current mirror, the first input end of the first current mirror is connected to the output end of the current generating submodule to mirror the first current signal to generate a second current signal; a second current mirror, the first output end of the second current mirror is suitable for connecting a preset bias current to mirror the preset bias current to generate a third current signal; a first resistor and a first switch tube, one end of the first resistor is respectively connected to the second input end of the first current mirror and the second output end of the second current mirror, and has a first node, and the other end of the first resistor is connected to the first switch tube. The first switch tube is connected to the drain of the first switch tube, and the source of the first switch tube is grounded; a first capacitor, one end of the first capacitor is respectively connected to the other end of the first resistor and the drain of the first switch tube, and the other end of the first capacitor is grounded; a first NOT gate, the input end of the first NOT gate is connected to the output end of the clock oscillator, and the output end of the first NOT gate is connected to the control end of the first switch tube; a second resistor, one end of the second resistor is connected to the third output end of the second current mirror and has a second node, and the other end of the second resistor is grounded; a delay signal generating submodule, the input end of the delay signal generating submodule is respectively connected to the first node and the second node, the output end of the delay signal generating submodule is connected to the logic operation module, and the delay signal generating submodule is configured to generate a delay signal according to the voltage of the first node and the voltage of the second node.

[0012] According to one embodiment of the present invention, when the voltage of the first node is greater than the voltage of the second node, the delay signal is at a low level; or when the voltage of the first node is less than or equal to the voltage of the second node, the delay signal is at a high level.

[0013] According to one embodiment of the present invention, the current generating submodule includes: a second switch tube, the source of the second switch tube is suitable for inputting a preset power supply, and the drain of the second switch tube is connected to the control end of the second switch tube; a third switch tube, the source of the third switch tube is suitable for inputting a preset power supply, the control end of the third switch tube is connected to the control end of the second switch tube, and the drain of the third switch tube is connected to the first input end of the first current mirror; a fourth switch tube, the drain of the fourth switch tube is connected to the drain of the second switch tube, and the control end of the fourth switch tube is connected to one end of the compensation capacitor; a third resistor, one end of the third resistor is connected to the source of the fourth switch tube, and the other end of the third resistor is grounded.

[0014] According to one embodiment of the present invention, the first current mirror includes: a fifth switch tube, the drain of the fifth switch tube is respectively connected to the output end of the current generating submodule and the control end of the fifth switch tube, and the source of the fifth switch tube is grounded; a sixth switch tube, the drain of the sixth switch tube is connected to the first node, the control end of the sixth switch tube is connected to the control end of the fifth switch tube, and the source of the sixth switch tube is grounded.

[0015] According to one embodiment of the present invention, the second current mirror includes: a seventh switch tube, the source of the seventh switch tube is suitable for inputting a preset power supply, the drain of the seventh switch tube is connected to the control end of the seventh switch tube and is suitable for connecting a preset bias current; an eighth switch tube, the source of the eighth switch tube is suitable for inputting a preset power supply, the control end of the eighth switch tube is connected to the control end of the seventh switch tube, and the drain of the eighth switch tube is connected to the first node; a ninth switch tube, the source of the ninth switch tube is suitable for inputting a preset power supply, the control end of the ninth switch tube is connected to the control end of the seventh switch tube, and the drain of the ninth switch tube is connected to the second node.

[0016] According to one embodiment of the present invention, the delay signal generating submodule includes: a tenth switch tube, the source of the tenth switch tube is suitable for inputting a preset power supply, the control end of the tenth switch tube is connected to the control end of the seventh switch tube, and the drain of the tenth switch tube has a third node; an eleventh switch tube, the source of the eleventh switch tube is connected to the third node, and the control end of the eleventh switch tube is connected to the first node; a twelfth switch tube, the source of the twelfth switch tube is connected to the third node, and the control end of the twelfth switch tube is connected to the second node; a thirteenth switch tube, the drain of the thirteenth switch tube is respectively connected to the drain of the eleventh switch tube and the control end of the thirteenth switch tube, and the eleventh switch tube is connected to the third node. The source of the third switch tube is grounded; the fourteenth switch tube, the drain of the fourteenth switch tube is connected to the drain of the twelfth switch tube, the control end of the fourteenth switch tube is connected to the control end of the thirteenth switch tube, and the source of the fourteenth switch tube is grounded; the fifteenth switch tube, the source of the fifteenth switch tube is suitable for inputting a preset power supply, the control end of the fifteenth switch tube is connected to the control end of the seventh switch tube, and the drain of the fifteenth switch tube is connected to the first input end of the logic operation module; the sixteenth switch tube, the drain of the sixteenth switch tube is connected to the drain of the fifteenth switch tube, the control end of the sixteenth switch tube is connected to the drain of the fourteenth switch tube, and the source of the sixteenth switch tube is grounded.

[0017] According to one embodiment of the present invention, the duration of the delay signal shielding the frequency signal is calculated according to the following formula: Wherein, C1 is the first capacitor, m is the current ratio of the first current mirror, k is the current ratio of the second current mirror, R1 is the first resistor, R2 is the second resistor, I bias is the preset bias current, I clamp' is the first current signal.

[0018] According to an embodiment of the present invention, the resistance value of the first resistor is greater than the resistance value of the second resistor.

[0019] According to one embodiment of the present invention, the logic operation module includes: a second NOT gate, the input end of the second NOT gate is connected to the output end of the frequency control module; an AND gate, the first input end of the AND gate is connected to the output end of the second NOT gate, the second input end of the AND gate is connected to the output end of the clock oscillator, and the output end of the AND gate is the output end of the logic operation module.

[0020] According to one embodiment of the present invention, the voltage clamping unit includes: an error amplifier, wherein the positive input terminal of the error amplifier is suitable for inputting a first reference voltage, the negative input terminal of the error amplifier is suitable for connecting a load circuit, and the error amplifier is configured to generate an error signal according to the difference between the first reference voltage and a feedback voltage; a clamping module, wherein the input terminal of the clamping module is connected to the output terminal of the error amplifier, and the clamping unit is configured to generate a clamping current when the error signal is less than a second reference voltage to clamp the error signal to the second reference voltage.

[0021] According to an embodiment of the present invention, the clamping current is positively correlated with the frequency reduction amplitude of the frequency signal.

[0022] To achieve the above objective, a voltage converter is provided according to a second aspect of the present invention, comprising a mode switching circuit according to any one of the above embodiments.

[0023] According to the voltage converter of the embodiment of the present invention, through the above-mentioned mode switching circuit, the clamping current is provided to the compensation capacitor at a preset time interval to reduce the equivalent average current. Therefore, a compensation capacitor with a smaller capacitance can be selected, which effectively reduces the volume of the capacitor, thereby reducing the volume of the DC-DC converter.

[0024] To achieve the above objective, a chip is provided according to a third aspect of the present invention, comprising the aforementioned voltage converter.

[0025] According to the chip of the embodiment of the present invention, the equivalent average current is reduced by providing the clamping current to the compensation capacitor at a preset time interval through the above-mentioned voltage converter. Therefore, a compensation capacitor with a smaller capacitance can be selected, which effectively reduces the volume of the capacitor, thereby reducing the volume of the DC-DC converter.

[0026] Additional aspects and advantages of the present invention will be given in part in the following description of the voltage converter and in part will be obvious from the following description or learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of the structure of a voltage converter in the related art;

[0028] Figure 2 is a schematic structural diagram of a voltage converter according to an embodiment of the present invention;

[0029] Figure 3 is a schematic structural diagram of a voltage converter according to another embodiment of the present invention;

[0030] Figure 4 is a structural schematic diagram of a frequency generating unit according to an embodiment of the present invention;

[0031] Figure 5 is a waveform diagram according to an embodiment of the present invention;

[0032] Figure 6 is a circuit diagram of a frequency control module according to an embodiment of the present invention;

[0033] Figure 7 is a system schematic diagram of a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0035] It should be noted that this application is made based on the inventor's understanding and research of the following issues:

[0036] Figure 1 FIG. 1 shows a schematic diagram of a voltage converter having a mode switching circuit in the related art. Figure 1 As shown, when the load is large, the feedback voltage output by the load circuit 400 is small, so the output voltage of the error amplifier 11 is high, the clamping module 12 does not generate a clamping current, and the frequency generating unit 30 generates a frequency signal with a fixed frequency; when the load is small, the feedback voltage output by the load circuit 400 is large, and the output voltage of the error amplifier 11 gradually decreases. When the output voltage of the error amplifier 11 decreases to a set value, the clamping module 12 starts to work and generates a clamping current to clamp the output voltage of the error amplifier 11 to the set value. The frequency generating unit 30 outputs a reduced frequency according to the clamping current, thereby realizing switching from PWM mode to PFM mode.

[0037] Because the clamping current may have pulse characteristics during operation, and the output voltage of the error amplifier 11 changes from a high impedance state to a low impedance state after clamping, the loop characteristics change significantly. Therefore, the mode switching circuit needs to add a compensation capacitor C with a larger capacitance to compensate the PFM loop, thereby avoiding the risk of loop oscillation. The capacitance of the compensation capacitor C is usually tens of nanofarads, and the size is large, making it difficult to achieve on-chip integration. Therefore, the large capacitance occupies a large space, resulting in an increase in the volume of the DC-DC converter.

[0038] Based on this, an embodiment of the present invention provides a voltage converter and a mode switching circuit and chip thereof, which reduces the equivalent average current by providing a clamping current to a compensation capacitor at a preset time interval. Therefore, a compensation capacitor with a smaller capacitance can be selected, which effectively reduces the volume of the capacitor, thereby reducing the volume of the DC-DC converter.

[0039] The voltage converter and its mode switching circuit and chip according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0040] Figure 2 is a schematic diagram of the structure of a voltage converter according to an embodiment of the present invention. Figure 2As shown, the mode switching circuit 100 includes a voltage clamping unit 10 , a controllable switch unit 20 , a compensation capacitor C and a frequency generating unit 30 .

[0041] The input end of the voltage clamping unit 10 is suitable for connecting to the load circuit 400 of the voltage converter, and the voltage clamping unit 10 is configured to generate a clamping current I according to the first reference voltage Vref1 and the feedback voltage output by the load circuit 400. clamp , so as to clamp the difference between the first reference voltage Vref1 and the feedback voltage to the second reference voltage; the input end of the controllable switch unit 20 is connected to the output end of the voltage clamp unit 10, the output end of the controllable switch unit 20 is connected to one end of the compensation capacitor C, the other end of the compensation capacitor C is grounded, and the controllable switch unit 20 is configured to clamp the current I according to a preset time interval clamp Provided to the compensation capacitor C to charge the compensation capacitor C; the input end of the frequency generating unit 30 is connected to one end of the compensation capacitor C, and the frequency generating unit 30 is configured to generate a frequency signal and perform frequency reduction control on the frequency signal according to the upper plate voltage Vb of the compensation capacitor C, so that the voltage converter switches from the pulse width modulation mode to the pulse frequency modulation mode.

[0042] Specifically, if Figure 2 As shown, the voltage converter includes a mode switching circuit 100, a comparator 20, a logic control circuit 300 and a load circuit 400. The input end of the voltage clamping unit 10 is connected to the load circuit 400. The load current of the load circuit 400 decreases, the load resistance increases, and the internal resistance of the voltage converter remains unchanged, so the feedback voltage gradually increases. Therefore, the difference between the first reference voltage Vref1 and the feedback voltage is small, and the voltage clamping unit 10 generates a clamping current I clamp , so as to clamp the difference between the first reference voltage Vref1 and the feedback voltage to the second reference voltage. The controllable switch unit 20 clamps the current I clamp Provided to the compensation capacitor C, therefore, the equivalent charging current I eff According to formula (1), we can get:

[0043]

[0044] Among them, t s is the opening time of the controllable switch unit 20, T cycle is the switching period of the controllable switch unit 20.

[0045] It should be noted that the switching period of the controllable switch unit 20 can be determined according to the clock of the voltage converter, or an independent or externally controlled clock can be used, and there is no specific limitation here.

[0046] Therefore, the equivalent capacitance of the compensation capacitor C is C eff It can be calculated according to formula (2):

[0047]

[0048] For example, assuming that the switching period T of the controllable switch unit 20 is cycle is 1us, and the turn-on time t of the controllable switch unit 20 is s If the capacitance of the compensation capacitor C in the related art is 20nF, then the capacitance of the equivalent capacitor is 20nF. According to formula (2), the capacitance of the compensation capacitor C can be calculated to be 200pF. Therefore, the selection of a small capacitor of 200pF can achieve the compensation effect of a large capacitor of 20nF in the related art.

[0049] The voltage clamping unit 10 does not generate a clamping current I clamp In the case of, the upper plate voltage Vb of the compensation capacitor C is 0, the frequency generating unit 30 does not adjust the frequency signal, so the frequency generating unit 30 outputs a frequency signal with a fixed frequency; when the voltage clamping unit 10 generates a clamping current I clamp In the case where the upper plate voltage Vb of the compensation capacitor C is not 0, the frequency generating unit 30 performs frequency reduction control on the frequency signal to achieve switching between the PWM mode and the PFM mode.

[0050] In an optional implementation, the controllable switch unit 20 includes a switch S, one end of which is connected to the output end of the voltage clamping unit 10 , and the other end of which is respectively connected to one end of the compensation capacitor C and the input end of the frequency generating unit 30 .

[0051] Furthermore, in some embodiments, the compensation capacitor C is integrated inside the chip of the voltage converter.

[0052] It is understandable that, because the equivalent charging current of the compensation capacitor C is reduced, the compensation capacitor C can be selected as a small on-chip capacitor. Therefore, the compensation capacitor C can be integrated inside the chip of the voltage converter, thereby further reducing the volume of the voltage converter.

[0053] In some embodiments, the clamping current I clamp It is positively correlated with the frequency reduction amplitude of the frequency signal.

[0054] Specifically, as the load current gradually decreases, the feedback voltage gradually increases, so the difference between the first reference voltage Vref1 and the feedback voltage also gradually decreases. In order to fix the difference between the first reference voltage Vref1 and the feedback voltage at the second reference voltage, the clamping current I clamp As the frequency increases, the frequency reduction amplitude of the frequency signal also increases, and the frequency of the frequency signal output by the frequency generating unit 30 becomes lower.

[0055] In some embodiments, Figure 3 As shown, the voltage clamping unit 10 includes: an error amplifier 11 and a clamping module 12, wherein the positive input terminal of the error amplifier 11 is suitable for inputting a first reference voltage Vref1, and the negative input terminal of the error amplifier 11 is suitable for connecting to a load circuit 400, and the error amplifier 11 is configured to generate an error signal Vc according to a difference between the first reference voltage Vref1 and a feedback voltage; the input terminal of the clamping module 12 is connected to the output terminal of the error amplifier 11, and the clamping unit is configured to generate a clamping current I when the error signal Vc is less than a second reference voltage. clamp , so as to clamp the error signal Vc at the second reference voltage.

[0056] Specifically, the feedback voltage is fed back to the negative input terminal of the error amplifier 11. When the feedback voltage gradually increases, the error signal Vc gradually decreases. When the error signal Vc drops below the second reference voltage, the clamping module 12 generates a clamping current I clamp , so as to pull up the error signal Vc to the second reference voltage, and a feedback loop is formed between the error amplifier 11 and the clamping module 12 to prevent the error signal Vc from continuing to decrease.

[0057] In an optional embodiment, if Figure 2 and Figure 3 As shown, the output terminal of the error amplifier 11 is also connected to the positive input terminal of the comparator 200 to provide the error signal Vc to the comparator 200. The negative input terminal of the comparator 200 is suitable for inputting a preset triangular wave signal. The comparator 200 generates a comparison signal according to the difference between the first reference voltage Vref1 and the feedback voltage and the preset triangular wave signal, and provides the comparison signal to the logic control circuit 300. The first input terminal of the logic control circuit 300 is connected to the output terminal of the comparator 200, and the second input terminal of the logic control circuit 300 is connected to the output terminal of the frequency generation unit 30. The logic control circuit 300 generates a control signal according to the comparison signal and the frequency signal output by the frequency generation unit 30, and provides the control signal to the load circuit 400.

[0058] In the above embodiment, when the load is large, the voltage clamping unit will not generate a clamping current, and the frequency generating unit outputs a frequency signal of a fixed frequency. When the load is small, the voltage clamping unit generates a clamping current, and the controllable switch unit provides the clamping current to the compensation capacitor at a preset time interval to charge the compensation capacitor, thereby reducing the equivalent charging current of the compensation capacitor. Therefore, the compensation capacitor can be a capacitor with a smaller capacitance. After the compensation capacitor is charged, the upper plate voltage changes, so that the frequency generating unit performs frequency reduction control on the frequency signal, thereby realizing the switch from the pulse width modulation mode to the pulse frequency modulation mode. Therefore, the use of a small capacitor can ensure the stability of the system loop during mode switching, effectively reducing the volume of the capacitor, thereby reducing the volume of the voltage converter. Furthermore, the compensation capacitor can be an on-chip capacitor, so that the compensation capacitor can be integrated inside the voltage converter, thereby further reducing the volume of the voltage converter.

[0059] In some embodiments, Figure 4 As shown, the frequency generating unit 30 includes: a clock oscillator 31, a frequency control module 32 and a logic operation module 33, wherein the clock oscillator 31 is configured to generate a frequency signal; a first input end of the frequency control module 32 is connected to one end of the compensation capacitor C, a second input end of the frequency control module 32 is connected to the output end of the clock oscillator 31, and the frequency control module 32 is configured to generate a delay signal according to the upper plate voltage Vb and the frequency signal; a first input end of the logic operation module 33 is connected to the input end of the frequency control module 32, a second input end of the logic operation module 33 is connected to the output end of the clock oscillator 31, and the output end of the logic operation module 33 is connected to the input end of the clock oscillator 31, and the logic operation module 33 is configured to shield the frequency signal with the delay signal to reduce the frequency signal, and provide the reduced frequency signal to the clock oscillator 31, so that the clock oscillator 31 generates a frequency signal according to the reduced frequency signal.

[0060] Specifically, the output end of the clock oscillator 31 and the logic operation module 33 are connected to generate a frequency signal according to the frequency signal output by the logic operation module 33. The clock oscillator 31 can dynamically adjust the output frequency of the clock oscillator 31 through closed-loop control to adapt to different needs. The frequency control module 32 generates a delay signal according to the upper plate voltage Vb of the compensation capacitor C and the frequency signal. The delay signal is used to adjust the frequency of the clock oscillator 31 to achieve the required frequency change. The logic operation module 33 uses the delay signal to shield the high-level duration of the frequency signal to delay the rising edge of the frequency signal, thereby extending the period of the frequency signal and achieving frequency reduction of the frequency signal.

[0061] It should be noted that the clock oscillator 31 can be any clock generating circuit that can generate a fixed frequency clock.

[0062] In some embodiments, Figure 5 As shown, the frequency control module 32 includes: a current generating submodule 321, a first current mirror 322, a second current mirror 323, a first resistor R1, a first switch tube M1, a first capacitor C1, a first NOT gate 324, a second resistor R2 and a delay signal generating submodule 325, wherein the input end of the current generating submodule 321 is connected to one end of the capacitor to generate a first current signal I according to the upper plate voltage Vb clamp’ , where the first current signal I clamp’ Used to characterize the clamping current I clamp The first input terminal of the first current mirror 322 is connected to the output terminal of the current generating submodule 321 to generate the first current signal I clamp’ The first output terminal of the second current mirror 323 is suitable for connecting the preset bias current I bias , to preset the bias current I bias The first resistor R1 is connected to the second input terminal of the first current mirror 322 and the second output terminal of the second current mirror 323, and has a first node J1. The other end of the first resistor R1 is connected to the drain of the first switch tube M1, and the source of the first switch tube M1 is grounded. The first capacitor C1 is connected to the other end of the first resistor R1 and the drain of the first switch tube M1, and the other end of the first capacitor C1 is grounded. The input end of the first NOT gate 324 is connected to the output end of the clock oscillator 31, and the output end of the first NOT gate 324 is connected to the control end of the first switch tube M1. The second resistor R2 is connected to the third output end of the second current mirror 323, and has a second node J2. The other end of the second resistor R2 is grounded. The input end of the delay signal generation submodule 325 is connected to the first node J1 and the second node J2, respectively. The output end of the delay signal generation submodule 325 is connected to the logic operation module 33. The delay signal generation submodule 325 is configured to generate a delay signal according to the voltage of the first node J1 and the voltage of the second node J2.

[0063] Specifically, the frequency control module 32 includes two working states, namely, a working state when the frequency signal is at a low level and a working state when the frequency signal is at a high level.

[0064] When the frequency signal is at a low level, the electrical signal output by the first NOT gate 324 is at a high level, the first switch tube M1 is turned on, and the first capacitor C1 is short-circuited. If the voltage converter operates in the PWM mode, the clamping module 12 does not generate the clamping current I clamp , so the current generating submodule 321 is not turned on, and the first current signal I clamp’=0, therefore, the second current signal is also 0. The second current mirror 323 provides a third current signal to the first resistor R1 and the second resistor R2 respectively. If the voltage converter operates in the PFM mode, the clamping module 12 generates a clamping current I clamp , so the current generating submodule 321 is turned on to generate the first current signal I clamp’ , clamping current I clamp The larger the first current signal I clamp’ Then the first current mirror 322 is turned on to generate a second current signal. Therefore, the third current signal provided by the second current mirror 323 to the first resistor R1 includes the second current signal flowing into the first current mirror 322. Therefore, the voltage V1 of the first node J1 is as shown in formula (3), and the voltage V2 of the second node J2 is as shown in formula (4).

[0065] V1=(k·I bias -mI clamp' )R1 (3)

[0066] V2=k·I bias ·R2 (4)

[0067] Wherein, k is the current ratio of the second current mirror 323 , and m is the current ratio of the first current mirror 322 .

[0068] When the frequency signal is at a high level, the electrical signal output by the first NOT gate 324 is at a low level, the first switch tube M1 is turned off, and the first capacitor C1 starts to charge. The voltage of the second node J2 remains unchanged, and the voltage of the first node J1 gradually increases as the first capacitor C1 is charged, thereby changing the relationship between the voltage of the first node J1 and the voltage of the second node J2. Therefore, when the clamping current I clamp During the generation, the voltage of the first node J1 and the voltage of the second node J2 will change, and the delay signal generation submodule 325 can generate a delay signal according to the voltage of the first node J1 and the voltage of the second node J2.

[0069] Furthermore, in some embodiments, the resistance of the first resistor R1 is greater than the resistance of the second resistor R2.

[0070] Specifically, as shown in formula (3) and formula (4), when the frequency signal is at a low level and the voltage converter is in the PWM mode, because the second current signal is 0, the voltage of the first node J1 is greater than the voltage of the second node J2; when the frequency signal is at a low level and the voltage converter is in the PFM mode, because the third current signal provided by the second current mirror 323 to the first resistor R1 includes the second current signal flowing into the first current mirror 322, the voltage of the first node J1 is less than the voltage of the second node J2; when the frequency signal is at a high level, the voltage of the first node J1 is less than the voltage of the second node J2, and as the first capacitor C1 is charged, the voltage of the first node J1 gradually increases and then becomes greater than the voltage of the second node J2.

[0071] In some embodiments, Figure 5 As shown, when the voltage of the first node J1 is greater than the voltage of the second node J2, the delay signal is at a low level; or when the voltage of the first node J1 is less than or equal to the voltage of the second node J2, the delay signal is at a high level.

[0072] Specifically, if Figure 5 As shown, when the error signal Vc output by the error amplifier 11 is greater than the second reference voltage, the voltage converter is in PWM mode, and the clamping module 12 does not generate the clamping current I clamp , that is, the clamping current I clamp is 0, therefore, the first current signal I clamp’ is 0, and the second current signal is also 0. Therefore, when the frequency signal output by the clock oscillator 31 is at a low level, the voltage of the first node J1 is always greater than the voltage of the second node J2, and the delay signal is at a low level. When the frequency signal output by the clock oscillator 31 is at a high level, the voltage of the first node J1 is also greater than the voltage of the second node J2, and the delay signal is at a low level. Therefore, when the voltage converter is in PWM mode, the delay signal always remains at a low level. When the error signal Vc output by the error amplifier 11 is less than or equal to the second reference voltage, the clamp module 12 generates a clamp current I clamp Therefore, the first current signal I clamp’ is greater than 0, and the second current signal is also greater than 0, so when the frequency signal output by the clock oscillator 31 is at a low level, the voltage of the first node J1 is less than the voltage of the second node J2, and the delay signal is at a high level. When the frequency signal output by the oscillator is at a high level, the voltage of the first node J1 is first less than or equal to the voltage of the second node J2. At this time, the delay signal is at a high level. When the voltage of the first node J1 is greater than the voltage of the second node J2, the delay signal changes from a high level to a low level.

[0073] In some embodiments, the duration of the delay signal shielding the frequency signal is calculated according to the following formula (5):

[0074]

[0075] Wherein, C1 is the first capacitor, m is the current ratio of the first current mirror 322, k is the current ratio of the second current mirror 323, R1 is the first resistor, R2 is the second resistor, I bias is the preset bias current, I clamp' is the first current signal.

[0076] Specifically, if Figure 5 As shown, when the frequency signal is at a high level, the high level width of the delay signal is the duration of the delay signal shielding the frequency signal. The relationship between the high level duration of the delay signal and the charge accumulated on the first capacitor C1 is shown in formula (6):

[0077] (k·I bias -m·I clamp' )t delay =C1(V1-V2) (6)

[0078] Substituting formula (3) and formula (4) into formula (6), the high level duration of the delayed signal can be calculated, that is, the duration of the delayed signal shielding the frequency signal.

[0079] Therefore, when the voltage converter is in PWM mode, the delay signal always maintains a low level. If the frequency signal period generated by the oscillator is T, the frequency signal period output by the logic operation module 33 is also T. When the voltage converter is in PFM mode, the delay signal delays the rising edge of the frequency signal by t. delay If the frequency signal period generated by the oscillator is T, then the frequency signal period output by the logic operation module 33 is T+t delay , so the frequency of the frequency signal output by the logic operation module 33 decreases.

[0080] In some embodiments, Figure 6 As shown, the current generating submodule 321 includes: a second switch tube M2, a third switch tube M3, a fourth switch tube M4 and a third resistor R3, wherein the source of the second switch tube M2 is suitable for inputting a preset power supply, and the drain of the second switch tube M2 is connected to the control end of the second switch tube M2; the third switch tube M3, the source of the third switch tube M3 is suitable for inputting a preset power supply, the control end of the third switch tube M3 is connected to the control end of the second switch tube M2, and the drain of the third switch tube M3 is connected to the first input end of the first current mirror 322; the fourth switch tube M4, the drain of the fourth switch tube M4 is connected to the drain of the second switch tube M2, and the control end of the fourth switch tube M4 is connected to one end of the compensation capacitor C; one end of the third resistor R3 is connected to the source of the fourth switch tube M4, and the other end of the third resistor R3 is grounded.

[0081] Specifically, when the clamping current I clamp When the upper plate voltage Vb is 0, the fourth switch tube M4 is in the off state, so the first current signal I clamp’ is 0; when the clamping current I clamp is greater than 0, the upper plate voltage Vb is greater than 0, the fourth switch tube M4 is turned on, the second switch tube M2 and the third switch tube M3 are also turned on, and the third switch tube M3 inputs the first current signal I to the first current mirror 322. clamp’ Therefore, the second current signal input by the first current mirror 322 is greater than zero.

[0082] In some embodiments, Figure 6 As shown, the first current mirror 322 includes: a fifth switch tube M5 and a sixth switch tube M6, wherein the drain of the fifth switch tube M5 is respectively connected to the output end of the current generating submodule 321 and the control end of the fifth switch tube M5, and the source of the fifth switch tube M5 is grounded; the drain of the sixth switch tube M6 is connected to the first node J1, the control end of the sixth switch tube M6 is connected to the control end of the fifth switch tube M5, and the source of the sixth switch tube M6 is grounded.

[0083] Specifically, when the first current signal I clamp’ When the first current signal I clamp’ When the current ratio of the fifth switch tube M5 to the sixth switch tube M6 is m, the second current signal is m divided by the first current signal I clamp’ The product of .

[0084] In some embodiments, Figure 6 As shown, the second current mirror 323 includes: a seventh switch tube M7, an eighth switch tube M8 and a ninth switch tube M9, wherein the source of the seventh switch tube M7 is suitable for inputting a preset power supply, and the drain of the seventh switch tube M7 is connected to the control end of the seventh switch tube M7 and is suitable for connecting a preset bias current I bias The source of the eighth switch tube M8 is suitable for inputting a preset power supply, the control end of the eighth switch tube M8 is connected to the control end of the seventh switch tube M7, and the drain of the eighth switch tube M8 is connected to the first node J1; the source of the ninth switch tube M9 is suitable for inputting a preset power supply, the control end of the ninth switch tube M9 is connected to the control end of the seventh switch tube M7, and the drain of the ninth switch tube M9 is connected to the second node J2.

[0085] Specifically, when the seventh switch tube M7 is turned on, the eighth switch tube M8 and the ninth switch tube M9 are turned on. Since the current ratio of the seventh switch tube M7 to the eighth switch tube M8 and the ninth switch tube M9 is k, the third current signal is k and the preset bias current I bias The eighth switch tube M8 provides a third current signal to the first resistor R1, and the ninth switch tube M9 provides a current signal to the second resistor R2. When the second current signal is 0, the third current signal provided by the eighth switch tube M8 to the first resistor R1 all flows into the first resistor R1; when the second current signal is greater than 0, the eighth switch tube M8 provides current to the first resistor R1 and the first current mirror 322 at the same time, so part of the third current signal flows into the first current mirror 322, and the other part flows into the first resistor R1.

[0086] In some embodiments, Figure 6 As shown, the delay signal generating submodule 325 includes: a tenth switch tube M10, an eleventh switch tube M11, a twelfth switch tube M12, a thirteenth switch tube M13, a fourteenth switch tube M14, a fifteenth switch tube M15 and a sixteenth switch tube M16, wherein the source of the tenth switch tube M10 is suitable for inputting a preset power supply, the control end of the tenth switch tube M10 is connected to the control end of the seventh switch tube M7, and the drain of the tenth switch tube M10 has a third node J3; the source of the eleventh switch tube M11 is connected to the third node J3, and the control end of the eleventh switch tube M11 is connected to the first node J1; the source of the twelfth switch tube M12 is connected to the third node J3, and the control end of the twelfth switch tube M12 is connected to the second node J2; the drain of the thirteenth switch tube M13 is connected to the eleventh node J3, and the control end of the twelfth switch tube M12 is connected to the second node J2; The drain of the switch tube M11 is connected to the control end of the thirteenth switch tube M13, and the source of the thirteenth switch tube M13 is grounded; the drain of the fourteenth switch tube M14 is connected to the drain of the twelfth switch tube M12, the control end of the fourteenth switch tube M14 is connected to the control end of the thirteenth switch tube M13, and the source of the fourteenth switch tube M14 is grounded; the source of the fifteenth switch tube M15 is suitable for inputting a preset power supply, the control end of the fifteenth switch tube M15 is connected to the control end of the seventh switch tube M7, and the drain of the fifteenth switch tube M15 is connected to the first input end of the logic operation module 33; the drain of the sixteenth switch tube M16 is connected to the drain of the fifteenth switch tube M15, the control end of the sixteenth switch tube M16 is connected to the drain of the fourteenth switch tube M14, and the source of the sixteenth switch tube M16 is grounded.

[0087] It can be understood that the tenth switch tube M10 and the fifteenth switch tube M15 respectively form a current mirror with the seventh switch tube M7, so when the seventh switch tube M7 is turned on, the tenth switch tube M10 and the fifteenth switch tube M15 are turned on respectively. When the voltage of the first node J1 is greater than the voltage of the second node J2, the eleventh switch tube M11 and the twelfth switch tube M12 are turned off, so the thirteenth switch tube M13, the fourteenth switch tube M14 and the sixteenth switch tube M16 are all in the off state, so the delay signal is a low level; when the voltage of the first node J1 is less than or equal to the voltage of the second node J2, the eleventh switch tube M11 and the twelfth switch tube M12 are turned on, so the thirteenth switch tube M13, the fourteenth switch tube M14 and the sixteenth switch tube M16 are all in the on state, so the delay signal is a high level.

[0088] In some embodiments, Figure 4 As shown, the logic operation module 33 includes: a second NOT gate 331 and an AND gate 332, wherein the input end of the second NOT gate 331 is connected to the output end of the frequency control module 32; the first input end of the AND gate 332 is connected to the output end of the second NOT gate 331, the second input end of the AND gate 332 is connected to the output end of the clock oscillator 31, and the output end of the AND gate 332 is the output end of the logic operation module 33.

[0089] Specifically, if Figure 5 As shown, when the voltage converter is in PWM mode, the delay signal is low level, the signal output by the second NOT gate 331 is a high level signal, and the electrical signal output by the AND gate 332 is the same as the frequency signal output by the clock oscillator 31. Therefore, when the voltage converter is in PWM mode, the frequency generating unit 30 outputs the frequency signal; when the voltage converter is in PFM mode, if the delay signal is high level, the electrical signal output by the second NOT gate 331 is low level. Therefore, when the voltage converter is in PFM mode, if the frequency signal is high level and the delay signal is low level, the signal output by the AND gate 332 is a high level signal, thereby realizing frequency reduction control of the frequency signal.

[0090] In summary, according to an embodiment of the present invention, the mode switching circuit includes a voltage clamping unit, a controllable switch unit, a compensation capacitor and a frequency generating unit, wherein the input end of the voltage clamping unit is suitable for connecting to the load circuit of the voltage converter, the voltage clamping unit is configured to generate a clamping current according to the first reference voltage and the feedback voltage output by the load circuit, so as to clamp the difference between the first reference voltage and the feedback voltage to the second reference voltage, the input end of the controllable switch unit is connected to the output end of the voltage clamping unit, the output end of the controllable switch unit is connected to one end of the compensation capacitor, and the other end of the compensation capacitor is grounded, the controllable switch unit is configured to provide the clamping current to the compensation capacitor at a preset time interval to charge the compensation capacitor, the input end of the frequency generating unit is connected to one end of the compensation capacitor, the frequency generating unit is configured to generate a frequency signal, and perform frequency reduction control on the frequency signal according to the upper plate voltage of the compensation capacitor, so that the voltage converter switches from the pulse width modulation mode to the pulse frequency modulation mode. Therefore, when the clamping current is not generated, the upper plate voltage of the compensation capacitor is always 0, so the voltage converter operates in the pulse width modulation mode. When the load is small, the voltage clamping unit generates the clamping current, and the controllable switch unit provides the clamping current to the compensation capacitor at a preset time interval to charge the compensation capacitor, thereby reducing the equivalent average charging current of the compensation capacitor. Therefore, the compensation capacitor can use a capacitor with a smaller capacitance. After the compensation capacitor is charged, the upper plate voltage changes, so that the frequency generation unit performs frequency reduction control on the frequency signal, thereby realizing the switch from the pulse width modulation mode to the pulse frequency modulation mode. Therefore, loop compensation can be achieved using a small capacitor, which effectively reduces the volume of the capacitor, thereby reducing the volume of the DC-DC converter.

[0091] Corresponding to the above embodiment, an embodiment of the present invention further provides a voltage converter. Figure 2 As shown, the voltage converter includes the mode switching circuit 100 of any of the above embodiments.

[0092] According to the voltage converter of the embodiment of the present invention, through the above-mentioned mode switching circuit, the clamping current is provided to the compensation capacitor at a preset time interval to reduce the equivalent average current. Therefore, a compensation capacitor with a smaller capacitance can be selected, which effectively reduces the volume of the capacitor, thereby reducing the volume of the DC-DC converter.

[0093] To achieve the above-mentioned object, a chip is provided according to a third aspect of the present invention. Figure 7 As shown, the chip 2000 includes the aforementioned voltage converter 1000 .

[0094] According to the chip of the embodiment of the present invention, the equivalent average current is reduced by providing the clamping current to the compensation capacitor at a preset time interval through the above-mentioned voltage converter. Therefore, a compensation capacitor with a smaller capacitance can be selected, which effectively reduces the volume of the capacitor, thereby reducing the volume of the DC-DC converter.

[0095] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0096] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0097] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0098] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0099] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0100] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A mode switching circuit of a voltage converter, characterized in that: include: a voltage clamping unit, wherein an input terminal of the voltage clamping unit is suitable for connecting to a load circuit of the voltage converter, and the voltage clamping unit is configured to generate a clamping current according to a first reference voltage and a feedback voltage output by the load circuit, so as to clamp a difference between the first reference voltage and the feedback voltage to a second reference voltage; A controllable switch unit and a compensation capacitor, wherein the input end of the controllable switch unit is connected to the output end of the voltage clamp unit, the output end of the controllable switch unit is connected to one end of the compensation capacitor, the other end of the compensation capacitor is grounded, and the controllable switch unit is configured to provide the clamp current to the compensation capacitor at a preset time interval to charge the compensation capacitor; A frequency generating unit, wherein the input end of the frequency generating unit is connected to one end of the compensation capacitor, and the frequency generating unit is configured to generate a frequency signal and perform frequency reduction control on the frequency signal according to the upper plate voltage of the compensation capacitor so that the voltage converter switches from a pulse width modulation mode to a pulse frequency modulation mode.

2. The mode switching circuit according to claim 1, characterized in that: The compensation capacitor is integrated inside the chip of the voltage converter.

3. The mode switching circuit according to claim 1, characterized in that: The frequency generating unit comprises: a clock oscillator configured to generate the frequency signal; A frequency control module, wherein a first input terminal of the frequency control module is connected to one end of the compensation capacitor, a second input terminal of the frequency control module is connected to an output terminal of the clock oscillator, and the frequency control module is configured to generate a delay signal according to the upper plate voltage and the frequency signal; A logic operation module, wherein a first input end of the logic operation module is connected to an input end of the frequency control module, a second input end of the logic operation module is connected to an output end of the clock oscillator, and an output end of the logic operation module is connected to an input end of the clock oscillator, and the logic operation module is configured to shield the frequency signal using the delay signal to reduce the frequency signal, and provide the reduced frequency signal to the clock oscillator so that the clock oscillator generates the frequency signal according to the reduced frequency signal.

4. The mode switching circuit according to claim 3, characterized in that: The frequency control module comprises: a current generating submodule, wherein an input end of the current generating submodule is connected to one end of the capacitor to generate a first current signal according to the upper plate voltage, wherein the first current signal is used to characterize the clamping current; a first current mirror, wherein a first input terminal of the first current mirror is connected to an output terminal of the current generating submodule to mirror the first current signal to generate a second current signal; a second current mirror, wherein a first output terminal of the second current mirror is suitable for connecting a preset bias current to mirror the preset bias current to generate a third current signal; A first resistor and a first switch tube, wherein one end of the first resistor is respectively connected to the second input end of the first current mirror and the second output end of the second current mirror and has a first node, the other end of the first resistor is connected to the drain of the first switch tube, and the source of the first switch tube is grounded; A first capacitor, one end of which is connected to the other end of the first resistor and the drain of the first switch tube respectively, and the other end of the first capacitor is grounded; A first NOT gate, wherein an input end of the first NOT gate is connected to an output end of the clock oscillator, and an output end of the first NOT gate is connected to a control end of the first switch tube; a second resistor, one end of the second resistor being connected to the third output end of the second current mirror and having a second node, and the other end of the second resistor being grounded; A delay signal generating submodule, wherein the input end of the delay signal generating submodule is respectively connected to the first node and the second node, the output end of the delay signal generating submodule is connected to the logic operation module, and the delay signal generating submodule is configured to generate the delay signal according to the voltage of the first node and the voltage of the second node.

5. The mode switching circuit according to claim 4, characterized in that: The second current mirror comprises: a seventh switch tube, wherein a source of the seventh switch tube is suitable for inputting a preset power supply, and a drain of the seventh switch tube is connected to a control end of the seventh switch tube and is suitable for connecting the preset bias current; an eighth switch tube, wherein a source of the eighth switch tube is suitable for inputting the preset power supply, a control end of the eighth switch tube is connected to the control end of the seventh switch tube, and a drain of the eighth switch tube is connected to the first node; A ninth switch tube, wherein the source of the ninth switch tube is suitable for inputting the preset power supply, the control end of the ninth switch tube is connected to the control end of the seventh switch tube, and the drain of the ninth switch tube is connected to the second node.

6. The mode switching circuit according to claim 5, characterized in that: The delay signal generating submodule comprises: a tenth switch tube, wherein a source of the tenth switch tube is suitable for inputting the preset power supply, a control end of the tenth switch tube is connected to a control end of the seventh switch tube, and a drain of the tenth switch tube has a third node; an eleventh switch tube, wherein a source of the eleventh switch tube is connected to the third node, and a control terminal of the eleventh switch tube is connected to the first node; a twelfth switch tube, wherein a source of the twelfth switch tube is connected to the third node, and a control terminal of the twelfth switch tube is connected to the second node; a thirteenth switch tube, wherein the drain of the thirteenth switch tube is respectively connected to the drain of the eleventh switch tube and the control end of the thirteenth switch tube, and the source of the thirteenth switch tube is grounded; a fourteenth switch tube, wherein the drain of the fourteenth switch tube is connected to the drain of the twelfth switch tube, the control end of the fourteenth switch tube is connected to the control end of the thirteenth switch tube, and the source of the fourteenth switch tube is grounded; a fifteenth switch tube, wherein the source of the fifteenth switch tube is suitable for inputting the preset power supply, the control end of the fifteenth switch tube is connected to the control end of the seventh switch tube, and the drain of the fifteenth switch tube is connected to the first input end of the logic operation module; A sixteenth switch tube, wherein the drain of the sixteenth switch tube is connected to the drain of the fifteenth switch tube, the control end of the sixteenth switch tube is connected to the drain of the fourteenth switch tube, and the source of the sixteenth switch tube is grounded.

7. The mode switching circuit according to any one of claims 4 to 6, characterized in that: The duration of the delay signal shielding the frequency signal is calculated according to the following formula: Wherein, C1 is the first capacitor, m is the current ratio of the first current mirror, k is the current ratio of the second current mirror, R1 is the first resistor, R2 is the second resistor, I bias is the preset bias current, I clamp' is the first current signal.

8. The mode switching circuit according to claim 3, characterized in that: The logic operation module comprises: A second NOT gate, wherein an input end of the second NOT gate is connected to an output end of the frequency control module; An AND gate, wherein a first input terminal of the AND gate is connected to an output terminal of the second NOT gate, a second input terminal of the AND gate is connected to an output terminal of the clock oscillator, and an output terminal of the AND gate is an output terminal of the logic operation module.

9. A voltage converter, characterized in that: The method comprises a mode switching circuit according to any one of claims 1 to 8.

10. A chip, characterized in that: Comprising a voltage converter according to claim 9.

Images