Heterojunction cell, preparation method, photovoltaic module and photovoltaic system

Abstract

The embodiment of the invention provides a heterojunction cell, a preparation method, a photovoltaic module and a photovoltaic system. The heterojunction cell includes: a silicon substrate layer; the electron transmission layer is located on the back face of the silicon substrate layer, the electron transmission layer is made of an organic conductive material, and the energy band of the organic conductive material is matched with the energy band of the silicon substrate layer; wherein the organic conductive material comprises carbazole phosphonic acid. According to the embodiment of the invention, the electron transmission layer is made of the organic conductive material, and the organic conductive material has excellent conductivity, so that the conductivity of the electron transmission layer is greatly improved. And on the other hand, the energy band of the organic conductive material is matched with the energy band of the silicon substrate layer, so that the transmission potential barrier of the electron transmission layer and the silicon substrate layer can be reduced, electrons can reach the electron transmission layer from the silicon substrate layer more easily, the series resistance of the cell is reduced, and the overall photoelectric conversion efficiency of the cell is further improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a heterojunction cell, a preparation method, a photovoltaic module and a photovoltaic system. Background Art

[0002] Silicon-based heterojunction (HJT) cells based on the principle of selective passivation contact have the advantages of higher cell conversion efficiency, lower temperature coefficient and no photoinduced degradation effect.

[0003] At present, heterojunction batteries usually use transition metal oxides as hole transport layers. However, transition metal oxides have low conductivity, and using transition metal oxides in heterojunction batteries will increase the overall resistivity of the battery, thereby affecting the overall performance of the battery.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0005] The embodiments of the present application provide a heterojunction battery, a preparation method, a photovoltaic module and a photovoltaic system to solve or alleviate one or more of the technical problems mentioned above.

[0006] According to a first aspect of an embodiment of the present application, a heterojunction battery is provided, comprising:

[0007] Silicon base layer;

[0008] The electron transport layer is located on the back of the silicon substrate layer and is made of an organic conductive material. The energy band of the organic conductive material matches the energy band of the silicon substrate layer. The organic conductive material includes carbazole phosphonic acid.

[0009] Optionally, the organic conductive material includes carbazolephosphonic acid.

[0010] Optionally, it further includes a first amorphous silicon layer; the first amorphous silicon layer is arranged between the silicon base layer and the electron transport layer, and the first amorphous silicon layer is intrinsic hydrogenated amorphous silicon.

[0011] Optionally, the back side of the silicon base layer is a polished surface.

[0012] Optionally, the first amorphous silicon layer is deposited on the back side of the silicon base layer by a PECVD process;

[0013] Wherein, the thickness ratio of the first amorphous silicon layer to the electron transport layer is 0.12-0.6.

[0014] Optionally, a first conductive layer is further included, and the first conductive layer is stacked on a side of the electron transport layer away from the silicon base layer.

[0015] Optionally, it also includes a second amorphous silicon layer, a hole transport layer and a second conductive layer; the second amorphous silicon layer, the hole transport layer and the second conductive layer are stacked in sequence on the front side of the silicon base layer; wherein the hole transport layer is made of one or more materials selected from molybdenum oxide, nickel oxide, tungsten oxide, titanium oxide and copper oxide.

[0016] Optionally, the second amorphous silicon layer is intrinsic hydrogenated amorphous silicon.

[0017] Optionally, a thickness ratio of the second amorphous silicon layer to the hole transport layer is 0.3-3.

[0018] A second aspect of an embodiment of the present application provides a method for preparing a heterojunction battery, comprising:

[0019] A silicon substrate layer having a velvet surface on the front side and a polished surface on the back side is obtained;

[0020] Depositing a first amorphous silicon layer on the back side of the silicon base layer;

[0021] An electron transport layer is spin-coated on the back of the first amorphous silicon layer. The spin-coated material is an organic conductive material whose energy band matches that of the material of the silicon substrate layer. The organic conductive material includes carbazole phosphonic acid.

[0022] According to a third aspect of the embodiments of the present application, a photovoltaic assembly is provided, comprising at least one battery string, wherein the battery string comprises at least two photovoltaic cells as described above.

[0023] According to a fourth aspect of the embodiments of the present application, a photovoltaic system is provided, comprising the photovoltaic assembly as described above.

[0024] The above technical solution adopted in the embodiment of the present application may have the following advantages:

[0025] On the one hand, the organic conductive material used in the electron transport layer itself has excellent electrical conductivity, which can greatly improve the conductivity of the electron transport layer itself. On the other hand, the energy band of the organic conductive material matches the energy band of the silicon substrate layer, which can reduce the transmission barrier between the electron transport layer and the silicon substrate layer, making it easier for electrons to reach the electron transport layer from the silicon substrate layer, reducing the series resistance of the battery, and thus improving the overall photoelectric conversion efficiency of the battery. This can reduce the impact of the high resistivity of the transition metal oxide in the hole transport layer, thereby improving the photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0027] Figure 1 is a schematic diagram of the structure of a heterojunction battery provided in an embodiment of the present application;

[0028] Figure 2 It is a flow chart of the method for preparing a heterojunction battery provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0031] In this application, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] In the embodiments of the present application, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products or apparatuses.

[0033] The following provides an explanation of the terms used in this application.

[0034] Heterojunction cell: A solar cell composed of two or more different semiconductor materials, which converts light energy into electrical energy by forming a PN junction at their junction. Heterojunction cells include crystalline silicon / amorphous silicon heterojunction solar cells and organic / inorganic heterojunction solar cells.

[0035] Dipole effect: The electric dipole generated by the uneven distribution of electron density inside a molecule or material can interact with the external electric field and affect the photoelectric properties and electron transport properties of the material. In optoelectronic devices such as solar cells, the dipole effect can be used to regulate the extraction and transmission of electrons, thereby improving the efficiency and performance of the device.

[0036] Schottky barrier: refers to the potential barrier formed in the contact area between semiconductor and metal. The existence of Schottky barrier will hinder the movement of electrons from semiconductor to metal and affect the injection and transmission of electrons to a certain extent.

[0037] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0038] Figure 1 The structural diagram of a heterojunction battery according to an embodiment of the present application is schematically shown.

[0039] like Figure 1 As shown, the heterojunction cell may include: a silicon substrate layer 101 and an electron transport layer 102 .

[0040] The silicon base layer 101 may be a P-type silicon substrate or an N-type silicon substrate.

[0041] In one example, the silicon base layer 101 uses an N-type silicon substrate, such as N-type single crystal silicon. The thickness of the silicon base layer 101 may be 60 μm to 180 μm; for example, the thickness may be 150 μm.

[0042] In an embodiment of the present application, the electron transport layer 102 is located on the back side of the silicon base layer 101. The back side of the silicon base layer 101 refers to the side of the silicon base layer 101 that faces away from the sunlight. It is understood that the front side of the silicon base layer 101 refers to the side of the silicon base layer 101 that faces the sunlight. The front side of the silicon base layer 101 faces the sunlight to absorb light energy. When sunlight shines on the front side of the silicon base layer 101, photons are absorbed by the silicon base layer 101 and stimulate the generation of photogenerated electrons and holes. Under the action of the electron transport layer 102, the photogenerated electrons move from the silicon base layer 101 to the electron transport layer 102.

[0043] In the embodiment of the present application, the electron transport layer 102 is made of an organic conductive material, and the energy band of the organic conductive material matches the energy band of the silicon base layer 101 .

[0044] Band matching means that the band structures of two materials can be well aligned or matched at the contact interface, so that electrons can be transmitted freely between the two materials without much hindrance, thereby reducing the transmission barrier between the materials.

[0045] In the embodiment of the present application, the electron transport layer 102 uses an organic material that matches the energy band of the silicon base layer 101. On the one hand, the organic conductive material used in the electron transport layer 102 itself has excellent electrical conductivity, which greatly improves the conductivity of the electron transport layer 102 itself. On the other hand, the energy band of the organic conductive material matches the energy band of the silicon base layer 101, which can reduce the transmission barrier between the electron transport layer 102 and the silicon base layer 101, making it easier for electrons to reach the electron transport layer 102 from the silicon base layer 101, reducing the series resistance of the battery, and thus improving the overall photoelectric conversion efficiency of the battery. This can reduce the impact of the high resistivity of the transition metal oxide in the hole transport layer 106, thereby improving the photoelectric conversion efficiency of the battery.

[0046] In one embodiment, the organic conductive material used in the electron transport layer 102 may include carbazolephosphonic acid.

[0047] In the embodiment of the present application, carbazole phosphonic acid itself has good electrical conductivity, so electrons can be quickly transported inside it, thereby increasing the conductivity of the electron transport layer 102 itself. Secondly, carbazole phosphonic acid can form a dipole effect at the interface, and the formation of the dipole effect can reduce the Schottky barrier at the contact interface between the electron transport layer 102 and other layers, thereby reducing the series resistance of the device and improving the photoelectric conversion efficiency of the battery.

[0048] like Figure 1 As shown, the heterojunction cell may further include: a first amorphous silicon layer 103 .

[0049] In the embodiment of the present application, the first amorphous silicon layer 103 is disposed between the silicon base layer 101 and the electron transport layer 102 .

[0050] Since there may be lattice defects in the silicon crystal and the silicon base layer 101 is easily affected by external factors, defects may occur on the surface of the silicon base layer 101. External factors include the processing of the silicon base layer 101, such as cutting, polishing, corrosion and other processes may cause mechanical scratches and chemical damage on the surface, resulting in surface defects of the silicon base layer 101. The surface with these defects will capture photogenerated carriers, resulting in recombination losses and reducing the open circuit voltage of the device.

[0051] Therefore, the first amorphous silicon layer 103 can be provided between the silicon base layer 101 and the electron transport layer 102 as a passivation layer of the silicon base layer 101 , thereby reducing the defect density at the interface of the silicon base layer 101 and improving the open circuit voltage of the device.

[0052] In one example, the first amorphous silicon layer 103 is intrinsic hydrogenated amorphous silicon.

[0053] Intrinsic hydrogenated amorphous silicon refers to an amorphous silicon material, and in the present example, it is used as the material of the first amorphous silicon layer 103 to passivate the interface defects of the silicon base layer 101. Since the hydrogen atoms in the intrinsic hydrogenated amorphous silicon have a repairing effect and can form a stable hydride layer at the interface, it can be used as a passivation material.

[0054] In the embodiment of the present application, intrinsic hydrogenated amorphous silicon is used as the first amorphous silicon layer 103, and the first amorphous silicon layer 103 is disposed between the silicon base layer 101 and the electron transport layer 102. On the one hand, the first amorphous silicon layer 103 can be used as a passivation layer of the silicon base layer 101, passivating the surface defects of the silicon base layer 101 and improving the open circuit voltage of the device. On the other hand, the anchoring group of carbazole phosphonic acid in the electron transport layer 102 can be well bonded with the intrinsic hydrogenated amorphous silicon, and the carbazole phosphonic acid plays a role similar to a coupling agent. The intrinsic hydrogenated amorphous silicon cooperates with the carbazole phosphonic acid to achieve a good connection between the first amorphous silicon layer 103 and the electron transport layer 102.

[0055] The back side of the silicon base layer 101 is a polished surface. Specifically, the back side of the silicon base layer 101 can be alkali-washed to make the back side of the silicon base layer 101 a polished surface.

[0056] In the embodiment of the present application, the back side of the silicon base layer 101 is a polished surface, and after polishing, the flatness and cleanliness of the back side of the silicon base layer 101 can be improved, so it is conducive to the deposition of intrinsic hydrogenated amorphous silicon, and it is easier to form a first amorphous silicon layer 103 with a uniform surface, thereby improving the passivation effect. On this basis, the electron transport layer 102 deposited on the first amorphous silicon layer 103 can also be more uniform, which improves the filling factor of the electron transport layer 102, thereby forming a more continuous and dense electron transport layer 102 film. Such a thin film structure helps to reduce holes and defects in the electron transport layer 102, thereby reducing the defect state density at the interface of the electron transport layer 102, further improving the open circuit voltage of the battery, and reducing the impact caused by the high resistivity of the hole transport layer 106 using transition metal oxides. Secondly, the back polished structure can effectively reflect the light passing through the silicon base layer 101 back into the silicon base layer 101 again, increase internal reflection, and improve the utilization rate of light, thereby improving the photoelectric conversion efficiency.

[0057] In an optional embodiment, the first amorphous silicon layer 103 is deposited on the back side of the silicon base layer 101 by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process. Specifically, the thickness ratio of the first amorphous silicon layer 103 to the electron transport layer 102 is 0.12 to 0.6. Exemplarily, the thickness ratio of the first amorphous silicon layer 103 to the electron transport layer 102 can be 0.12, 0.2, 0.3, 0.5 or 0.6.

[0058] PECVD is a process technology used to deposit thin films on the surface of substrates. It uses the energy of plasma to promote chemical reactions, thereby achieving thin film deposition at a lower temperature.

[0059] In one example, the thickness of the first amorphous silicon layer 103 may be 3 nm, the thickness of the electron transport layer 102 may be 25 nm, and the ratio of the thickness of the first amorphous silicon layer 103 to the thickness of the electron transport layer 102 is 0.12.

[0060] In this embodiment, by limiting the thickness ratio of the first amorphous silicon layer 103 and the electron transport layer 102 within a suitable range, the interface quality between the first amorphous silicon layer 103 and the electron transport layer 102 can be optimized, and the transport efficiency of electrons between the electron transport layer 102 and the first amorphous silicon layer 103 can be improved, thereby improving the current output of the battery.

[0061] like Figure 1As shown, the heterojunction cell may further include a first conductive layer 104. The first conductive layer 104 is stacked on the side of the electron transport layer 102 that is away from the silicon substrate layer 101. The first conductive layer 104 is the outermost stacked layer on the side facing away from the sunlight in the heterojunction cell. The first conductive layer 104 is used to collect and conduct photogenerated electrons, and the electrode 108 is used to longitudinally collect photogenerated holes and transmit them to the main grid.

[0062] In one example, the first conductive layer 104 may also be made of metal such as aluminum, copper, or silver.

[0063] In one embodiment, the heterojunction cell may further include a second amorphous silicon layer 105, a hole transport layer 106, and a second conductive layer 107. Figure 1 As shown, the second amorphous silicon layer 105 , the hole transport layer 106 and the second conductive layer 107 are sequentially stacked on the front surface of the silicon base layer 101 .

[0064] The second amorphous silicon layer 105 has a similar function to the first amorphous silicon layer 103 . The second amorphous silicon layer 105 and the first amorphous silicon layer 103 are amorphous silicon layers covering the front and back sides of the silicon base layer 101 , respectively, to passivate defects on the surface of the silicon base layer 101 .

[0065] In one example, the second amorphous silicon layer 105 is intrinsic hydrogenated amorphous silicon. Intrinsic hydrogenated amorphous silicon can effectively passivate defects on the surface of the silicon base layer 101, reduce recombination losses of carriers, and improve efficiency and stability of the battery.

[0066] The hole transport layer 106 can effectively extract holes from electron-hole pairs and prevent electrons and holes from recombining inside the device, thereby reducing the photoelectric conversion efficiency.

[0067] In one example, the hole transport layer 106 may include a transition metal oxide, which may be one or more of molybdenum oxide, nickel oxide, tungsten oxide, titanium oxide, and copper oxide.

[0068] The conductivity of the transition metal oxide used in the hole transport layer 106 is low, so the overall resistivity of the heterojunction battery is high, which affects the battery efficiency. Therefore, by improving the conductivity of the electron transport layer 102, the impact caused by the high resistivity of the transition metal oxide in the hole transport layer 106 can be reduced, the series resistance of the battery is reduced, and the photoelectric conversion efficiency of the battery is improved.

[0069] In an optional embodiment, the thickness ratio of the second amorphous silicon layer 105 to the hole transport layer 106 is 0.3 to 3. For example, the thickness ratio of the second amorphous silicon layer 105 to the hole transport layer 106 may be 0.3, 0.5, 1, 1.5, 2, 2.5 or 3.

[0070] In one example, the thickness of the second amorphous silicon layer 105 is 3 nm, the thickness of the hole transport layer 106 is 3 nm, and the ratio of the thickness of the second amorphous silicon layer 105 to the thickness of the hole transport layer 106 is 1.

[0071] In this embodiment, by limiting the thickness ratio of the second amorphous silicon layer 105 and the hole transport layer 106, the interface quality between the second amorphous silicon layer 105 and the hole transport layer 106 is improved, the charge separation and transfer efficiency between the hole transport layer 106 and the second amorphous silicon layer 105 is improved, the charge recombination is reduced, and the photoelectric conversion efficiency is improved.

[0072] See also Figure 1 , the heterojunction battery may further include an electrode 108 .

[0073] The second conductive layer 107 is used to collect photogenerated holes and transfer the holes to the electrode 108 .

[0074] In one example, the material of the second conductive layer 107 may include one of indium cerium oxide, indium tungsten oxide, indium tin oxide, zinc oxide, and indium zinc oxide.

[0075] The electrode 108 is located on a side of the second conductive layer 107 away from the silicon substrate layer 101 and is electrically connected to the main grid. The electrode 108 can be used to collect the photocurrent generated by the heterojunction cell, and transmit the collected photocurrent to the main grid, and then transmit it to the external device through the main grid. The external device can be an electrical device or a storage device.

[0076] The material of the electrode 108 may include silver, gold, etc. In other embodiments, the electrode 108 may also be a structure of silver wrapped copper.

[0077] The embodiment of the present application also provides a method for preparing a heterojunction battery, which is used to prepare the heterojunction battery of the above embodiment.

[0078] like Figure 2 As shown, the preparation method comprises:

[0079] Step S200: preparing a silicon base layer, wherein the front side of the silicon base layer is a velvet surface and the back side is a polished surface.

[0080] The silicon base layer with a velvet surface on the front side and a polished surface on the back side can be obtained by pre-treating the original silicon base layer.

[0081] Preprocessing includes:

[0082] Step 1: Clean and texture the original silicon base layer to obtain a silicon base layer with textured surfaces on both sides;

[0083] Step 2: depositing mask materials on both sides of the silicon base layer obtained in step 1;

[0084] Step 3: Remove the mask on the front side of the silicon base layer obtained in step 2 by using a chemical solution, remove the mask on the back side of the silicon base layer obtained in step 2 by using a chain cleaning machine, and perform alkali polishing on the back side of the silicon base layer obtained in step 2, so as to obtain a silicon base layer with a velvet surface on the front side and a polished surface on the back side.

[0085] In one example, the texturing solution may include potassium hydroxide.

[0086] In one example, the deposited mask material may be silicon nitride or silicon oxide.

[0087] In one example, the chemical solution may include hydrofluoric acid.

[0088] like Figure 2 As shown, the preparation method further includes: Step S202: depositing a first amorphous silicon layer on the back side of the silicon base layer.

[0089] In one example, a first amorphous silicon layer can be deposited on the back side of a silicon base layer using a PECVD plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition) device, with an RF (Radio Frequency) power supply having a power of 1000W to 5000W. The first amorphous silicon layer having a thickness of 2nm to 5nm can be deposited under a pressure of 40Pa to 400Pa and a temperature of 100°C to 200°C.

[0090] like Figure 2 As shown, the preparation method further includes: step S204: spin coating an electron transport layer on the back side of the first amorphous silicon layer.

[0091] In one example, the spin coating rotation speed may be 2500 rpm to 3500 rpm, and the spin coating time may be 60 s to 90 s.

[0092] In one example, after spin coating an electron transport layer on the back of the first amorphous silicon layer, a high temperature curing process may be performed, wherein the temperature of the high temperature curing process may be 100° C. to 130° C., and the time of the high temperature curing process may be 5 min to 10 min.

[0093] In one example, the electron transport layer may be cleaned and dried after being cured at high temperature, wherein the cleaning liquid may be isopropanol and the drying time may be 2 to 3 minutes.

[0094] In one example, in the process of forming the electron transport layer, the material used for spin coating is an organic conductive material whose energy band matches that of the material of the silicon base layer.

[0095] Band matching means that the band structures of two materials can be well aligned or matched at the contact interface, so that electrons can be transmitted freely between the two materials without much hindrance, thereby reducing the transmission barrier between the materials.

[0096] In the embodiment of the present application, the electron transport layer adopts an organic conductive material that matches the energy band of the silicon base layer. On the one hand, the organic conductive material used in the electron transport layer itself has excellent electrical conductivity, which greatly improves the conductivity of the electron transport layer itself. On the other hand, the energy band of the organic conductive material matches the energy band of the silicon base layer, which can reduce the transmission barrier between the electron transport layer and the silicon base layer, making it easier for electrons to reach the electron transport layer from the silicon base layer, reducing the series resistance of the battery, and thus improving the overall photoelectric conversion efficiency of the battery. This can reduce the impact of the high resistivity of the transition metal oxide in the hole transport layer, thereby improving the photoelectric conversion efficiency of the battery.

[0097] The embodiment of the present application may also provide a photovoltaic assembly (not shown), including at least one battery string, the battery string including at least two photovoltaic cells as described above, and adjacent photovoltaic cells may be connected together by series welding.

[0098] The embodiment of the present application can provide a photovoltaic system, including the photovoltaic components in any of the above embodiments. The advantages of the above photovoltaic components are also possessed by the photovoltaic system, which will not be repeated here. The above photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be used in all fields where solar energy is required for power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components may form multiple photovoltaic arrays. The photovoltaic array is connected to a junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0099] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0100] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0101] In the present invention, when it comes to numerical intervals (i.e., numerical ranges), unless otherwise specified, the distribution of optional numerical values ​​within the numerical interval is deemed to be continuous and includes the two numerical endpoints of the numerical interval (i.e., the minimum value and the maximum value), and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to integers within the numerical interval, including the two endpoint integers of the numerical range, and each integer between the two endpoints, is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be combined. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0102] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0103] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A heterojunction battery, characterized in that: include: Silicon base layer; An electron transport layer, the electron transport layer is located on the back of the silicon base layer, the electron transport layer is made of an organic conductive material, and the energy band of the organic conductive material matches the energy band of the silicon base layer; wherein the organic conductive material includes carbazole phosphonic acid.

2. The heterojunction battery according to claim 1, characterized in that: It also includes a first amorphous silicon layer; the first amorphous silicon layer is arranged between the silicon base layer and the electron transport layer, and the first amorphous silicon layer is intrinsic hydrogenated amorphous silicon.

3. The heterojunction battery according to claim 2, characterized in that: The back side of the silicon base layer is a polished surface.

4. The heterojunction battery according to claim 2, characterized in that: The first amorphous silicon layer is deposited on the back side of the silicon base layer by a PECVD process; Wherein, the ratio of the thickness of the first amorphous silicon layer to the thickness of the electron transport layer is 0.12-0.

6.

5. The heterojunction battery according to any one of claims 1 to 4, characterized in that: It also includes a first conductive layer, which is stacked on a side of the electron transport layer away from the silicon base layer.

6. The heterojunction battery according to any one of claims 1 to 4, characterized in that: Also includes a second amorphous silicon layer, a hole transport layer, and a second conductive layer; The second amorphous silicon layer, the hole transport layer and the second conductive layer are sequentially stacked on the front surface of the silicon base layer.

7. The heterojunction battery according to claim 6, characterized in that: The second amorphous silicon layer is intrinsic hydrogenated amorphous silicon.

8. The heterojunction battery according to claim 7, characterized in that: The ratio of the thickness of the second amorphous silicon layer to the thickness of the hole transport layer is 0.3-3.

9. A method for preparing a heterojunction battery, characterized in that: include: A silicon substrate layer having a velvet surface on the front side and a polished surface on the back side is obtained; Depositing a first amorphous silicon layer on the back side of the silicon base layer; An electron transport layer is spin-coated on the back of the first amorphous silicon layer, and the spin-coated material is an organic conductive material whose energy band matches that of the material of the silicon base layer; wherein the organic conductive material includes carbazolephosphonic acid.

10. A photovoltaic module, characterized in that: include: At least one battery string, the battery string comprising at least two heterojunction batteries according to any one of claims 1 to 8.

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