Phase measuring system

Abstract

The invention relates to the technical field of chip design, in particular to a phase measuring system which comprises a clock source, a first signal receiving end, a second signal receiving end, a state machine FSM, a counter cnt and a calculation module. According to the method, corresponding clock signals are sampled through a first register in a first signal receiving end and a second register in a second receiving end respectively to obtain a first level signal and a second level signal; through mutual cooperation of a state machine and a counter, counting is started when the first level signal is effective, counting is ended when the second level signal is effective, and an effective count value is obtained; and the phase difference is calculated through the calculation module. The clock signals in the chip are directly accessed through the receiving end, the phase difference of the clock signals in the chip is measured through mutual cooperation of the state machine, the counter and the calculation module, the measurement precision is high, the expansion capacity is high, the occupied area is small, and statistical data of measurement results can be provided.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a system for measuring phase. Background Art

[0002] In hardware simulation platform systems, multiple global clock signals are usually generated by one or more phase-locked loops (PLLs) and distributed to different FPGAs. These global clock signals are critical to the overall synchronization of the system, especially in complex multi-FPGA systems. However, due to the variability and scalability of the system, different clock signals may experience different delays when reaching each FPGA. This delay uncertainty increases the difficulty of timing analysis, especially in the scenario of synchronous clock source output. In order to achieve more accurate timing analysis, the clock signals output by these synchronous clock sources must be studied and processed in depth. Specifically, the phase difference between clock signals directly affects the timing margin of the system and the reliability of data transmission. If the phase difference information cannot be accurately obtained and processed, it may cause unpredictable timing problems during system operation, which in turn affects the overall performance of the simulation platform.

[0003] The current technology for obtaining phase difference is to measure it through an oscilloscope. The defects of measuring phase difference with an oscilloscope include:

[0004] First, oscilloscope measurement is usually a manual process, and each measurement requires human intervention, which increases the complexity of the operation.

[0005] Second, the oscilloscope can only measure the pin position of the chip at most. These signals have passed through the chip package pins and may be affected by factors such as packaging materials, pin layout, and pin coupling, resulting in low measurement accuracy.

[0006] Third, the ports that the oscilloscope can measure are limited and cannot be expanded. Summary of the invention

[0007] In response to the third technical problem, the technical solution adopted by the present invention is: a system for measuring phase, the system comprising: a clock source for generating a sampling clock signal refclk. At least one unit group for measuring the effective count value between two clock signals inside the chip, the unit group comprising a first signal receiving end, a second signal receiving end, a state machine FSM and a counter cnt; wherein the first signal receiving end comprises a first register FF1 and a first level detection module ED1; the data input end of the FF1 is connected to the sampled first clock signal clk0, and the clock input end of the FF1 is connected to the refclk; the ED1 is used to detect the level change logic output by the data output end of the FF1 to obtain a first level signal. The second signal receiving end comprises a second register FF2 and a second level detection module ED2; the data input end of the FF2 is connected to the sampled second clock signal clk1, and the clock input end of the FF2 is connected to the refclk; the ED2 is used to detect the level change logic output by the data output end of the FF2 to obtain a second level signal. The state machine FSM is connected to the ED1 and ED2 respectively. When the first level signal is valid, the state machine is triggered to transfer to the first state; when the second level signal is valid, the state machine is triggered to transfer to the second state. The counter cnt is connected to the FSM. When the state machine transfers to the first state, the cnt is triggered to start counting; when the state machine transfers to the second state, the cnt is triggered to end counting to obtain a valid count value C. diff The calculation module is connected to the cnt and calculates the diff , refclk clock period p s , the clock period p0 of clk0 and the clock period p1 of clk1 are used to calculate the phase difference Shift between clk1 and clk0.

[0008] The present invention has at least the following beneficial effects:

[0009] The present invention provides a system for measuring phase, which directly connects the first signal receiving end and the second signal receiving end to the clock signal inside the chip and samples them respectively, and measures the phase difference of the clock signal inside the chip through the cooperation of the state machine, the counter and the calculation module, with high measurement accuracy; and the system for measuring phase can include more than one group of units to measure the phase difference at the same time, and has strong expansion capability; no special measurement tools are required. In addition, the system occupies a small hardware area, and because the state machine can measure repeatedly in a loop, statistical data such as the average and variance of the measurement results can be obtained as a reference for evaluating the quality of the clock signal and the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram of a system for measuring phase provided by an embodiment of the present invention;

[0012] Figure 2 A schematic diagram of the timing of sampling and counting provided by an embodiment of the present invention;

[0013] Figure 3 A flow chart of a method for measuring a phase difference between clock signals provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0015] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0016] In order to solve the technical problem of low measurement accuracy and reliance on manual operation caused by independent tools such as oscilloscopes, the present invention proposes embodiment 1.

[0017] Embodiment 1

[0018] See also Figure 3 The present invention also provides a method for measuring the phase difference between clock signals, the method comprising:

[0019] S100, obtaining a sampling clock signal refclk.

[0020] Furthermore, the clock source is used to generate a sampling clock signal refclk. The clock source is used to provide clock signals for various components in the system, for example, registers, state machines, counters and calculation modules in the first receiving end and the second receiving end.

[0021] S200 , synchronously sampling two clock signals with different phases but the same frequency or a multiple frequency relationship through refclk to generate a first level signal and a second level signal respectively.

[0022] In one implementation, a direct sampling method may be used: using two independent registers, and using refclk to sample the levels of the two clock signals respectively. Therefore, S200 further includes:

[0023] S210, obtaining the first register FF1 and the second register FF2.

[0024] S220 , obtaining the two clock signals: a first clock signal clk0 and a second clock signal clk1 .

[0025] S230, the clock input terminal of FF1 is connected to the refclk, the data input terminal of FF1 is connected to the first clock signal clk0, and the signal output by the data output terminal of FF1 is a first level signal.

[0026] S240, the clock input terminal of FF2 is connected to the refclk, the data input terminal of FF2 is connected to the second clock signal clk1, and the signal output by the data output terminal of FF2 is a second level signal.

[0027] In another implementation, a dual trigger link may also be used, and S200 further includes:

[0028] S201 , obtaining a first trigger FFP1 , a second trigger FFP2 , a third trigger FFP3 , and a fourth trigger FFP4 .

[0029] S202 , obtaining the two clock signals: a first clock signal clk0 and a second clock signal clk1 .

[0030] S203, the data input end of FFP1 is connected to the first clock signal clk0, the data output end of FFP1 is connected to the data input end of FFP2, the clock input ends of FFP1 and FFP2 are respectively connected to the refclk, and the signal output by the data output end of FFP2 is the first clock signal.

[0031] Among them, in the dual triggers (FFP1 and FFP2) used to collect clk0, FFP1 is used to capture the input signal, and FFP2 is used to eliminate the hysteresis to ensure the stability of the output signal.

[0032] S204, the data input terminal of FFP3 is connected to the second clock signal clk1, the data output terminal of FFP3 is connected to the data input terminal of FFP4, the clock input terminals of FFP3 and FFP4 are respectively connected to refclk, and the signal output by the data output terminal of FFP4 is the second clock signal.

[0033] Through the dual trigger chain, a set of dual trigger chains (two serially connected D flip-flops) is used for each input signal, which can ensure the stability of the signal when sampling at the edge of the reference clock.

[0034] Other hardware circuits or software algorithms for realizing the function of "synchronously sampling two clock signals with different phases but the same frequency or a multiple frequency relationship through refclk to generate a first level signal and a second level signal respectively" all fall within the protection scope of the present invention.

[0035] S300, when the first level signal is valid, start counting; when the second level signal is valid, end counting, and obtain a valid count value C diff .

[0036] In one embodiment, counting is achieved by cooperating with a counter through a first level detection module and a second level detection module. The first level detection module is used to identify the effective edge of the first level signal. When the effective edge arrives, the counter is triggered to start counting. The second level detection module is used to identify the effective edge of the second level signal. When the effective edge arrives, the counter is triggered to end counting to obtain an effective count value C. diff It should be noted that the first level detection module and the second level detection module are implemented as combinational logic circuits.

[0037] In one implementation, the driving clock of the counter is the refclk.

[0038] In another implementation, it can also be implemented directly by a combinational logic circuit, and S300 further includes:

[0039] S301, obtaining a combinational logic circuit and a counter;

[0040] S302, the combinational logic circuit comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is connected to the first level signal, the second input terminal is connected to the second level signal, and the output terminal is connected to the start / stop input terminal of the counter; the combinational logic circuit is used for, when the first level signal is valid, the combinational logic circuit outputs a start signal to the counter, the counter starts counting, and the count value increases with the clock signal; when the second level signal is valid, the combinational logic circuit outputs a stop signal to the counter, the counter stops counting and outputs a valid count value C diff .

[0041] Others are used to realize "when the first level signal is valid, start counting; when the second level signal is valid, end counting, and obtain the valid count value C diff " hardware circuits or software algorithms that have the function of " fall within the protection scope of the present invention.

[0042] S400, according to C diff , refclk clock period p s, the phase difference Shift between the two clock signals is calculated from the clock periods p0 of the two clock signals.

[0043] In one embodiment, the C diff 、p s The relationship between p0 and Shift satisfies: Shift=C diff ×△t;△t=±(p s -p b )=±(p s -N×p0)=±(p s -M×N×p1), where N is an integer greater than 0.

[0044] In one embodiment, the lowest frequency of clk0 and clk1 is an integer multiple of the base frequency, the frequency of the sampling clock refclk is slightly lower or slightly higher than the base frequency, and the period p of refclk is s and the period of the fundamental frequency p b Satisfy p b =p s ±△t, and p b =N×p0=M×N×p1, where M and N are both integers greater than 0.

[0045] Embodiment 2 of the present invention provides a method for measuring the phase difference between clock signals, which synchronously samples two clock signals with different phases but the same frequency or a multiple frequency relationship through refclk, generates a first level signal and a second level signal respectively, and calculates the phase difference Shift between the first level signal and the second level signal through the effective count value between the effective edges. Compared with the method of measuring the phase difference through an oscilloscope in the prior art, this system can easily and accurately obtain the phase difference.

[0046] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0047] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0048] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0049] The method provided in the first embodiment does not rely on manual operation and the measured signal is a clock signal inside the chip, and its measurement accuracy is high. However, measuring the clock signal inside the chip requires the support of hardware circuits. In order to make the chip area occupied by the hardware circuit smaller and to further expand the number of measured signals and obtain statistical data, the present invention provides a second embodiment.

[0050] Embodiment 2

[0051] See also Figure 1 , which shows a system for measuring phase, the system includes: a clock source, at least one unit group and a calculation module, each unit group includes a first signal receiving end, a second signal receiving end, a state machine FSM and a counter cnt. Each unit group is used to measure the effective count value between two clock signals inside the chip. The number of unit groups can be expanded according to the number of clock signals to be measured, and the expansion capability is strong.

[0052] Furthermore, the clock source is used to generate a sampling clock signal refclk. The clock source is used to provide clock signals for various components in the system, such as registers, state machines, counters and calculation modules in the first receiving end and the second receiving end.

[0053] Furthermore, the first signal receiving end includes a first register FF1 and a first level detection module ED1; the data input end of the FF1 is connected to the sampled first clock signal clk0, and the clock input end of the FF1 is connected to the refclk; the ED1 is used to detect the level change logic output by the data output end of the FF1 to obtain a first level signal.

[0054] Among them, the register is a sampling register or a data register, which is used to capture or save instantaneous data samples. The register includes a clock input terminal, a data input terminal and a data output terminal. The data input terminal is connected to clk0, and the clock input terminal is connected to refclk. When the valid edge of refclk comes, the register copies the data of the data input port to its internal storage unit and outputs this new value to the data output port; otherwise, the register keeps its internal state unchanged, that is, the data of the output port remains unchanged. Other registers or register equivalent circuits used for sampling also fall within the protection scope of the present invention.

[0055] Among them, the level detection module is used to identify the change of the signal level. The change of the level is usually an effective edge, and the effective edge can be a rising edge or a falling edge. The implementation of the level detection module can be a level detection module composed of a combinational logic circuit, or a level detection module composed of a trigger and other sequential logic components. Other types of level detection modules all fall within the protection scope of the present invention.

[0056] Among them, the first clock signal and the second clock signal are two objects of the measured phase difference, and both are clock signals inside the chip. In order to obtain the phase difference between the first clock signal and the second clock signal, the first signal receiving end and the second signal receiving end are driven respectively by the sampling clock signal refclk, the first clock signal is connected to the data input end of FF1 as a data signal for sampling, and the second clock signal is connected to the data input end of FF2 as a data signal for use, and the first clock signal and the second clock signal are sampled respectively by refclk. By directly sampling the clock signal inside the chip, the noise and interference in the signal transmission of the independent measurement tool are avoided, and the measurement accuracy is higher.

[0057] Furthermore, the second signal receiving end includes a second register FF2 and a second level detection module ED2; the data input end of the FF2 is connected to the sampled second clock signal clk1, and the clock input end of the FF2 is connected to the refclk; the ED2 is used to detect the level change logic output by the data output end of FF2 to obtain a second level signal.

[0058] Similarly, the structure and function of the second signal receiving end are the same as those of the first signal receiving end, and will not be described in detail.

[0059] Furthermore, the state machine FSM is connected to the ED1 and ED2 respectively, and when the first level signal is valid, the state machine is triggered to transfer to the first state; when the second level signal is valid, the state machine is triggered to transfer to the second state.

[0060] In one embodiment, the state machine includes at least three states: an idle state, a first state, and a second state. When the state machine is in the idle state, if the first level signal is valid, the state machine transfers from the idle state to the first state; when the state machine is in the first state, if the second level signal is valid, the state machine transfers from the first state to the second state. When the state machine transfers to the second state, the counter completes the current counting work.

[0061] In another embodiment, the control signal of the state machine may also include a specified signal fed back by a counter. For example, when the state machine is transferred from the first state to the second state, the counter is triggered to end counting, and the counter feeds back a specified signal to the state machine after the counting ends; after the state machine receives the specified signal, it transfers from the second state to the idle state. Optionally, the specified signal may be an interrupt signal. Other methods for realizing state transfer of the state machine when the first level signal is valid and the second level signal is valid fall within the protection scope of the present invention.

[0062] The purpose of counting is achieved by the cooperation between the state machine and the counter, which not only simplifies the complex control logic, but also avoids false triggering and has higher counting accuracy because the counting ends when the state machine transfers from the first state to the second state, rather than simply when the second level signal is valid. And because the state of the state machine is cyclic, it can count cyclically and measure repeatedly, thereby obtaining statistical data such as average and variance as a reference for evaluating the quality of the clock signal and the stability of the system.

[0063] State machine circuits implemented by hardware logic fall within the protection scope of the present invention. Alternatively, state machines implemented by software also fall within the protection scope of the present invention.

[0064] Further, the counter cnt is connected to the FSM. When the state machine is transferred to the first state, the cnt is triggered to start counting; when the state machine is transferred to the second state, the cnt is triggered to end counting, and the effective count value C is obtained. diff The complex control logic is simplified and the purpose of accurate counting is achieved through the cooperation between the state machine and the counter, so that the phase difference finally obtained is more accurate.

[0065] In one embodiment, the counter is a D flip-flop or a JK flip-flop. Other types of flip-flops or logic circuits for implementing the counter function also fall within the protection scope of the present invention. Modules that implement the counting function through software also fall within the protection scope of the present invention.

[0066] In one implementation, the driving clock of the cnt is the refclk.

[0067] It should be noted that the time length of the effective count value is the sampling asynchrony caused by the phase difference between the first clock signal and the second clock signal.

[0068] Further, the calculation module is connected to the cnt, according to the C diff , refclk clock period p s , the clock period p0 of clk0 and the clock period p1 of clk1 are calculated to obtain the phase difference between clk1 and clk0.

[0069] In one implementation, p0=M×p1, where M is an integer greater than or equal to 1. That is, p0 and p1 have the same frequency or an integer multiple of the frequency.

[0070] In one embodiment, the lowest frequency of clk0 and clk1 is an integer multiple of the base frequency, the frequency of the sampling clock refclk is slightly lower or slightly higher than the base frequency, and the period p of refclk is s and the period of the fundamental frequency pb Satisfy p b =p s ±△t, and p b =N×p0=M×N×p1, where M and N are both integers greater than 0.

[0071] In one implementation, when the driving clock of cnt is the refclk, the C diff 、p s 、p b The relationship between the phase difference Shift satisfies:

[0072] Shift=C diff ×△t;△t=±(p s -p b )=±(p s -N×p0)=±(p s -M×N×p1)

[0073] p s and p b The difference between them determines the accuracy of the measurement result. Since the clock signal periods of the sampled first clock signal clk0 and the second clock signal clk1 are both p b The clock period of the sampling clock signal refclk is an integer multiple of p s The difference between the sampling clock and the base frequency period, △t, needs to be much smaller than p0, p1, and p b , and p b =p s ±△t, so in each sampling cycle, the edge of refclk and the edges of the sampled first clock signal and the second clock signal will increase the time difference of △t. By accumulating them, the sampling result can observe the rising edge of the sampled first clock signal and the second clock signal in a period of time, and the falling edge in another period of time. Therefore, the phase difference can be calculated by Shift.

[0074] The system can detect the phase difference between multiple pairs of clock signals at the same time. The sampling clock signals connected to the clock input ends of the two signal receiving ends for detecting the phase difference between each pair of clock signals are the same. The actual circuit of the system provided in the second embodiment of the present invention is relatively simple, and the measurement of multiple groups of clock signals can be realized on the same FPGA chip.

[0075] As an example, for ease of understanding, take measuring the phase difference between two sampled clocks as an example, see Figure 2 , Figure 2The first clock signal clk0 and the second clock signal clk1 sampled in the example are both 10 MHz, and the sampling clock refclk is configured to 9.999 MHz by the configurable clock source. That is, the clock period p0 of clk0 is 100 ns, and the clock period p of refclk is s =100.01ns, so the difference between the clock period of clk0 and the clock period of refclk is 10ps. By adjusting the delay of the clock source, refclk obtains the rising edge samples of clk0 and clk1 at different times, corresponding to sample0 and sample1. A counter cnt driven by refclk is used to obtain the difference C between the two rising edges. diff The final measurement result is Shift = C diff ×△t. Figure 2 In the example, sample0 and sample1 occur when cnt is the 5th and 8th count values ​​respectively. diff =3. △t=10ps, therefore, the phase difference Shift between clk1 and clk0 is 30ps.

[0076] The present invention provides a system for measuring phase, which directly connects the first signal receiving end and the second signal receiving end to the clock signal inside the chip and samples them respectively, and measures the phase difference of the clock signal inside the chip through the cooperation of the state machine, the counter and the calculation module, with high measurement accuracy; and the system for measuring phase can include more than one group of units to measure the phase difference at the same time, and has strong expansion capability; no special measurement tools are required. In addition, the system occupies a small hardware area, and because the state machine can measure repeatedly in a loop, statistical data such as the average and variance of the measurement results can be obtained as a reference for evaluating the quality of the clock signal and the stability of the system.

[0077] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0078] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A system for measuring phase, characterized in that: The system comprises: A clock source, used to generate a sampling clock signal refclk; At least one unit group for measuring the effective count value between two clock signals inside the chip, the unit group comprising a first signal receiving end, a second signal receiving end, a state machine FSM and a counter cnt; The first signal receiving end includes a first register FF1 and a first level detection module ED1; the data input end of the FF1 is connected to the sampled first clock signal clk0, and the clock input end of the FF1 is connected to the refclk; the ED1 is used to detect the level change logic output by the data output end of the FF1 to obtain a first level signal; The second signal receiving end includes a second register FF2 and a second level detection module ED2; the data input end of the FF2 is connected to the sampled second clock signal clk1, and the clock input end of the FF2 is connected to the refclk; the ED2 is used to detect the level change logic output by the data output end of the FF2 to obtain a second level signal; The state machine FSM is connected to the ED1 and ED2 respectively, and when the first level signal is valid, the state machine is triggered to transfer to the first state; when the second level signal is valid, the state machine is triggered to transfer to the second state; The counter cnt is connected to the FSM. When the state machine is transferred to the first state, the cnt is triggered to start counting; when the state machine is transferred to the second state, the cnt is triggered to end counting, and a valid count value C is obtained. diff ; A calculation module is connected to the cnt and calculates the diff , refclk clock period p s , the clock period p0 of clk0 and the clock period p1 of clk1 are used to calculate the phase difference Shift between clk1 and clk0.

2. The system according to claim 1, characterized in that The state machine includes at least three states: an idle state, a first state, and a second state; when the state machine is in the idle state, if the first level signal is valid, the state machine transfers from the idle state to the first state; When the state machine is in the first state, if the second level signal is valid, the state machine transfers from the first state to the second state.

3. The system according to claim 2, characterized in that The sampling clock signal input to the clock input terminal of the first signal receiving terminal and the clock input terminal of the second signal receiving terminal in each component is the same.

4. The system according to claim 1, characterized in that The driving clock of the cnt is the refclk.

5. The system according to claim 1, characterized in that The C diff 、p s , the relationship between p0 and Shift satisfies: Shift=C diff ×△t;△t=±(p s -N×p0)=±(p s -M×N×p1), where N is an integer greater than 0.

6. The system according to claim 1, characterized in that The lowest frequency of clk0 and clk1 is an integer multiple of the base frequency, and the period of refclk is p s and the period of the fundamental frequency p b Satisfaction: p b =p s ±△t, and p b =N×p0=M×N×p1, where M and N are both integers greater than 0.

7. The system according to claim 1, characterized in that The counter is a D flip-flop or a JK flip-flop.

8. The system according to claim 1, characterized in that The register is a sampling register or a data register.

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