Low dropout regulator without off-chip capacitor and with high power supply rejection ratio

Abstract

The invention discloses a low-dropout linear regulator without an off-chip capacitor and with a high power supply rejection ratio. The invention is suitable for an integrated circuit technology, and provides an off-chip capacitor-free low dropout linear regulator (LDO) with a high power supply rejection ratio and a related power supply rejection ratio (PSRR) improving circuit thereof. According to the LDO, a special structure composed of an error amplifier at the input end and a PMOS source follower is adopted, the PMOS source follower is introduced behind the error amplifier to serve as a buffer stage, the stability of a feedback control loop is enhanced, and current conversion is conducted through two identical cascode current mirrors. In addition, the circuit is combined with a PSRR enhancement circuit and a compensation capacitor circuit, ripple waves on a power supply are effectively restrained, and single-end output is provided. Due to the unique design of the circuit structure, the LDO has the advantages that push-pull output is achieved, and higher output voltage swing is provided; 2, a simulation result shows that the power supply rejection at medium-high frequency is improved by about 13dB compared with a traditional LDO without an off-chip capacitor, and the LDO has higher robustness and lower power consumption;

Description

Technical Field

[0001] The present invention relates to a system for regulating electric or magnetic variables, and in particular to a low voltage drop linear regulator with high power supply rejection ratio and no off-chip capacitor. Background Art

[0002] Low Dropout Regulator (LDO). Low Dropout Regulator (LDO) is a power management component widely used in electronic devices to provide a stable output voltage despite possible fluctuations in the input voltage. LDOs are often used in noise-sensitive analog circuits, battery-powered devices, and other applications that require a stable power supply. In many applications, the power supply rejection ratio (PSRR) is a key parameter for measuring LDO performance. A high PSRR means that the LDO can effectively suppress noise and fluctuations in the input voltage, thereby providing a purer output voltage. However, improving the PSRR usually requires adding external off-chip capacitors to the LDO circuit to better filter out high-frequency noise.

[0003] Although off-chip capacitors can improve the PSRR of LDOs, they also bring some significant disadvantages. First, off-chip capacitors increase the size and cost of the circuit, making LDOs difficult to use in volume-constrained or cost-sensitive applications. Second, the presence of off-chip capacitors increases the complexity of circuit design and may affect the stability and response speed of the LDO. In order to overcome these problems, in recent years, some technical solutions have been dedicated to designing LDOs without off-chip capacitors while ensuring high PSRR. This type of LDO usually achieves high PSRR by optimizing the internal circuit structure, utilizing on-chip capacitors and efficient feedback control mechanisms. However, these solutions still face some challenges, such as PSRR performance in high frequency bands and how to further improve PSRR without increasing power consumption. In the mid-to-high frequency bands, the PSRR of the LDO is mainly limited by two factors: the g of the power tube. ds The transconductance between the gate and the source is g m Therefore, developing a low-dropout linear regulator that does not require external capacitors and has a high power supply rejection ratio can not only simplify circuit design, reduce cost and volume, but also provide higher power quality to meet various application scenarios with high requirements for power stability and purity. Summary of the invention

[0004] The main purpose of the present invention is to provide a high power supply voltage rejection ratio LDO without external capacitor and a related PSRR improvement circuit to solve the problem that the power supply rejection ratio of the above-mentioned LDO is relatively poor at medium and high frequencies.

[0005] To achieve the above object, the present invention proposes a high power supply voltage rejection ratio and no external capacitor LDO. A PMOS source follower is placed after the error amplifier of the LDO as a buffer stage. The buffer stage is used to buffer the output of the error amplifier in a feedback control loop. At the same time, a related PSRR enhancement circuit and a compensation capacitor circuit are connected to the source end of the PMOS to form a corresponding feedforward path, and the compensation path completes the suppression of the ripple on the power supply.

[0006] The specific structure of the LDO without external capacitor and its PSRR improvement circuit described in the present invention is: the inverting input end of the error amplifier is connected to the reference voltage, the output end of the error amplifier is connected to the gate of the PMOS buffer; the source end of the PMOS buffer is connected to the power tube M p The gate of the PMOS buffer is connected to the drain terminal; the source of the PMOS buffer is connected to the corresponding PSRR improvement circuit and the output terminal of the NCC compensation capacitor (CN) circuit; the PSRR improvement circuit is composed of M1, M2, R4, C4 and an ideal current source, wherein R4 and C4 form a low-pass filter, and the gate of M1 is connected to the power supply ripple after passing through the filter; the power tube M p The source of the power tube is connected to the power ripple, the drain of the power tube is connected in series with the RC output stage and then grounded, and the drain voltage of the power tube is the output voltage; the compensation capacitor circuit is composed of M5-M8, R6, C3 and an ideal current source, M5 and I1 form a source follower, and the remaining MOS tubes and resistors form a common-mode amplifier. The gate of M5 is connected to one side of the capacitor and is also connected to the power tube M p The gate, capacitor C3 and the above-mentioned source follower and in-phase amplifier are equivalent to the Vg end to form a compensation capacitor path to complete the compensation of the parasitic capacitance of the power tube.

[0007] The principle of the PSRR enhancement structure proposed in the present invention is derived as follows:

[0008] Power supply noise analysis of the circuit:

[0009] For the given circuit, since I2 is assumed to be an ideal current source, no small signal current flows into the current source because its output impedance is infinite. Therefore, the small signal voltage at node V1 is approximately equal to the power supply ripple and is represented as vdd. The noise figure includes the low and high frequencies of the power supply noise and is expressed as:

[0010] υdd=υdd,lpf+υdd,hpf (1)

[0011] Where υdd,lpf and υdd,hpf are high-frequency and low-frequency noises respectively, and the small-signal voltage at node V1 reaches V2 after passing through a low-pass filter with a low cutoff frequency composed of resistor R4 and capacitor C3. Therefore, the small-signal gate-source voltage of M2 can be derived as:

[0012] |υ gs2 |=υdd-υdd, lph=υdd, hpf (2)

[0013] The output node VG of the feed-forward path is connected to the gate of the power transistor MP. The small signal voltage of the gate of MP can be expressed as:

[0014]

[0015] Where gm1 and gm3 are the transconductances of PMOS transistors M1 and M3, and CP is the parasitic capacitance at the gate of MP. This equation shows that as long as C P +C N = 0, the small signal voltage VG can be insensitive to frequency changes. The purpose is to make V G = vdd, hpf, thus helping to improve the PSRR of the LDO. This can be achieved by adjusting the term gm1 / gm3 to be close to 1. Therefore, the small signal gate-source voltage of the power transistor MP is equal to zero at high frequencies, which effectively reduces the leakage current of MP.

[0016] The proposed capacitance compensation circuit structure principle is derived as follows:

[0017] Capacitor C3 and the above-mentioned source follower and in-phase amplifier are equivalent to the Vg terminal to form a negative capacitance circuit. The capacitance value is given by formula 5:

[0018] C N =(1-g m7 ×R6)×C3 (5)

[0019] Among them, g m7 is the transconductance value of transistor M7, and the negative capacitance circuit cannot obtain an accurate capacitance value. By analyzing equation 4, we can get P +C N = 0, the gate voltage of the power tube Mp will be insensitive to frequency. It can eliminate part of the capacitance at the output node of the feedforward path at a low cost over a wide frequency range.

[0020] The power supply rejection ratio simulation curve of the low voltage drop linear regulator with high power supply rejection ratio without external capacitors proposed by the present invention is shown in FIG. Figure 4 The power supply rejection ratio simulation curve of the low voltage drop linear regulator with off-chip capacitor of general structure is shown in Figure 5, both use the same current, input and load capacitance, comparing Figure 4 as well as Figure 5 It can be seen that at 1MHz, the LDO proposed by the present invention has a power supply rejection ratio of about 22dB under different load conditions. Figure 4 It can be seen that the power supply rejection ratio of the LDO proposed by the present invention is about 35dB under different loads at 1MHz, which is improved by about 13dB compared with the conventional LDO without external capacitors. Therefore, compared with the traditional solution using an additional summing circuit, the present invention has stronger robustness and relatively simple circuits, saving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0022] Figure 1 The invention provides an LDO without external capacitor and a related PSRR improvement circuit;

[0023] Figure 2 It is a common LDO circuit;

[0024] Figure 3 Detailed circuit for NCC structure;

[0025] Figure 4 for Figure 1 The power supply voltage rejection ratio simulation results of the present invention under different load conditions are shown in;

[0026] Figure 5 for Figure 2 The simulation results of the power supply voltage rejection ratio of an ordinary LDO without external capacitors under different load conditions;

[0027] Figure 6 for Figure 1 The stability simulation results of the present invention are given;

[0028] Figure 7 is a circuit diagram of an embodiment; DETAILED DESCRIPTION

[0029] [Example 1]

[0030] The circuit of the embodiment is as follows Figure 7 The power supply voltage is 3.3V, the input reference voltage is 1.2V, and the circuit is AC simulated by inputting a sinusoidal signal with an amplitude of 1 to the power supply input voltage, and the gain (20dB) and phase curves at the output are plotted.

[0031] [Comparative Example 2]

[0032] The circuit of the comparative example is Figure 7The power supply voltage is 3.3V, the input reference voltage is 1.2V, and the circuit is AC simulated by inputting a sinusoidal signal with an amplitude of 1 to the power supply input voltage, and the gain (20dB) and phase curves at the output are plotted.

Claims

1. A low dropout linear regulator (LDO) with high power supply voltage rejection ratio without external capacitor, characterized in that: A PMOS source follower is placed in front of the gate of the power tube as a buffer. The buffer is used to control the gate voltage of the power tube Mp in the feedback loop and form a feedforward path between the power supply ripple and the input. The source of the PMOS buffer is connected to the corresponding PSRR improvement circuit and the output end of the NCC compensation capacitor circuit; the positive end of the error amplifier is connected to the feedback voltage (Vfb), and the reverse input end of the error amplifier is connected to the reference voltage (Vref); the PSRR improvement circuit is composed of M1, M2, R4, C4 and an ideal current source, wherein R4 and C4 form a low-pass filter, and the gate of M1 is connected to the power supply ripple after passing through the filter; the power tube M p The source of the power tube is connected to the power ripple, the drain of the power tube is connected in series with the RC output stage and then grounded, and the drain voltage of the power tube is the output voltage; the compensation capacitor circuit is composed of M5-M8, R6, C3 and an ideal current source, M5 and I1 form a source follower, and the remaining MOS tubes and resistors form a common-mode amplifier. The gate of M5 is connected to one side of the capacitor and is also connected to the power tube M p of the gate.

2. The buffer and the M1 and M2 transistors of the PSRR improving circuit as claimed in claim 1 are all PMOS tubes.

3. The gm values ​​of M1 and M3 in the PSRR improving circuit as claimed in claim 1 must be equal in order to obtain a good high frequency power supply rejection ratio.

4. R6 in the NCC compensation capacitor circuit as described in claim 1 can achieve the same effect by biasing the active load through an NMOS tube.

5. The ideal current source in the PSRR improvement circuit and the NCC compensation capacitor circuit as described in claim 1 can be replaced by a load formed by a MOS tube to achieve the same effect.

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