Heterogeneous multi-core chip control method, device, equipment and system

Abstract

The invention discloses a control method, device, equipment and system for a heterogeneous multi-core chip, and relates to the technical field of chips, the control method for the heterogeneous multi-core chip is applied to a main core of a first core, and the method comprises the following steps: when an external wake-up request is received, sending a first power-on control instruction to a second core in the heterogeneous multi-core chip, the second core executes a starting program according to the first power-on control instruction; and when the first power-on control instruction is sent to the second core, generating a second power-on control instruction according to a parallel starting strategy, and respectively sending the second power-on control instruction to a plurality of sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes a starting program according to the second power-on control instruction. By means of the mode, rapid starting, high stability and high reliability of the heterogeneous multi-core chip are achieved, and the comprehensive requirements of the heterogeneous multi-core chip for energy efficiency, safety and real-time performance under variable working conditions are met.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to control methods, devices, equipment and systems for heterogeneous multi-core chips. Background Art

[0002] As the complexity of in-vehicle electronic systems increases, the requirements for energy efficiency management, functional safety and real-time performance of heterogeneous multi-core chips are also increasing. The S32G heterogeneous multi-core chip system has become a key component of in-vehicle electronic systems due to its multi-core parallel processing capabilities, low-latency response and high reliability. However, existing power-on and power-off control strategies often cannot meet the comprehensive requirements of these systems for energy efficiency, safety and real-time performance under variable working conditions. Summary of the invention

[0003] The main purpose of this application is to provide a control method, device, equipment and system for heterogeneous multi-core chips, aiming to solve the technical problem that existing power-on and power-off control strategies often cannot meet the comprehensive requirements of energy efficiency, safety and real-time performance of heterogeneous multi-core chip systems under variable working conditions.

[0004] To achieve the above objectives, the present application proposes a control method for a heterogeneous multi-core chip, the control method for a heterogeneous multi-core chip comprising:

[0005] Upon receiving an external wake-up request, sending a first power-on control instruction to a second core in the heterogeneous multi-core chip, so that the second core executes a startup program according to the first power-on control instruction;

[0006] When the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to the parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes the startup program according to the second power-on control instruction.

[0007] In one embodiment, when receiving an external wake-up request, sending a first power-on control instruction to a second core in a heterogeneous multi-core chip includes:

[0008] When receiving an external wake-up request, obtain the system initialization status;

[0009] When the system initialization state is the completion state and the control authority transmitted by the third core of the heterogeneous multi-core chip is received, a first power-on control instruction is sent to the second core in the heterogeneous multi-core chip. The control authority is transmitted after the third core completes the loading of the user firmware through the target firmware when the third core obtains the system integrity confirmation result by executing the target firmware.

[0010] In one embodiment, the control method of the heterogeneous multi-core chip further includes:

[0011] When there is no target wake-up source, sending a first sleep control instruction to a second core in the heterogeneous multi-core chip according to an inter-core communication mechanism, so that the second core executes a sleep program according to the first sleep control instruction and feeds back sleep confirmation information;

[0012] When the sleep confirmation information fed back by the second core is received and the preset sleep duration is reached, a second sleep control instruction is sent to the multiple sub-cores in the second core of the heterogeneous multi-core chip respectively, so that each sub-core executes a sleep program according to the second sleep control instruction and feeds back status confirmation information;

[0013] When the status confirmation information fed back by each sub-core is received, the target sleep program is executed.

[0014] In one embodiment, the method further comprises:

[0015] Upon receiving the status confirmation information fed back by each sub-core, shutting down the target system service;

[0016] When it is detected that the target system service is shut down, the core state information is saved to the target storage location;

[0017] When it is detected that the core state information is saved completely, a target sleep program is executed.

[0018] In one embodiment, the control method of the heterogeneous multi-core chip is applied to multiple sub-cores in a first core, and the control method of the heterogeneous multi-core chip includes:

[0019] When a second power-on control instruction sent by the main core of the first core is received, an interrupt service routine is triggered according to the second power-on control instruction, and a startup program is executed.

[0020] In one embodiment, the method further comprises:

[0021] When receiving the second sleep control instruction sent by the main core of the first core, saving the target task state;

[0022] When it is detected that the target task state is saved, the target processing mechanism is closed;

[0023] When it is detected that the shutdown of the target processing mechanism is completed, a sleep program is executed and status confirmation information is fed back to the main core of the first core.

[0024] In one embodiment, the control method of the heterogeneous multi-core chip is applied to the second core, and the control method of the heterogeneous multi-core chip includes:

[0025] When receiving the first sleep control instruction sent by the main core of the first core, sleep confirmation information is fed back to the main core of the first core, and when detecting that the key data is saved completely, a sleep program is executed.

[0026] In addition, to achieve the above-mentioned purpose, the present application also proposes a control device for a heterogeneous multi-core chip, and the control device for a heterogeneous multi-core chip includes:

[0027] A processing module, configured to, upon receiving an external wake-up request, start the operating system and send a first power-on control instruction to a second core in the heterogeneous multi-core chip, so that the second core executes a startup program according to the first power-on control instruction;

[0028] A control module is used to generate a second power-on control instruction according to a parallel startup strategy when the first power-on control instruction is sent to the second core, and to send the second power-on control instruction to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes a startup program according to the second power-on control instruction.

[0029] In addition, to achieve the above-mentioned objectives, the present application also proposes a control device for a heterogeneous multi-core chip, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the control method for a heterogeneous multi-core chip as described above.

[0030] In addition, to achieve the above-mentioned purpose, the present application also proposes a control system for a heterogeneous multi-core chip, characterized in that the control system of the heterogeneous multi-core chip includes a main core of the first core as described in any one of claims 1 to 4 above, multiple sub-cores in the first core as described in any one of claims 5 to 6, and the second core as described in claim 7 above.

[0031] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the control method of the heterogeneous multi-core chip as described above.

[0032] This application sends a first power-on control instruction to the second core in a heterogeneous multi-core chip when receiving an external wake-up request, so that the second core executes a startup program according to the first power-on control instruction; when the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to a parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes a startup program according to the second power-on control instruction. In the above manner, fast startup, high stability and high reliability of heterogeneous multi-core chips are achieved, and the comprehensive requirements of energy efficiency, safety and real-time performance of heterogeneous multi-core chips under variable working conditions are met. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0034] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0035] Figure 1 A flow chart of a control method for a heterogeneous multi-core chip applied to a main core of a first core provided in the present application in Embodiment 1;

[0036] Figure 2 A schematic diagram of the architecture of an S32G heterogeneous multi-core chip system provided in Embodiment 1 of the control method for a heterogeneous multi-core chip of the present application;

[0037] Figure 3 A schematic diagram of a specific startup process of core A after the main core sends an instruction to start core A, provided in Embodiment 1 of the control method for a heterogeneous multi-core chip of the present application;

[0038] Figure 4 A schematic diagram of a power management state machine flow chart of core A provided in Embodiment 1 of the control method for heterogeneous multi-core chip of the present application;

[0039] Figure 5 A flow chart of a control method for a heterogeneous multi-core chip of multiple sub-cores of a first core provided in the second embodiment of the present application;

[0040] Figure 6 A flowchart diagram of a control method embodiment 3 of a heterogeneous multi-core chip applied to a second core of the present application is provided;

[0041] Figure 7This is a schematic diagram of the module structure of the control device of the heterogeneous multi-core chip according to the embodiment of the present application;

[0042] Figure 8 Schematic diagram of the device structure of the hardware operating environment involved in the control method of the heterogeneous multi-core chip in the embodiment of the present application.

[0043] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0045] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0046] The main solution of the embodiment of the present application is: when an external wake-up request is received, a first power-on control instruction is sent to the second core in the heterogeneous multi-core chip, so that the second core executes the startup program according to the first power-on control instruction; when the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to the parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes the startup program according to the second power-on control instruction.

[0047] As the complexity of in-vehicle electronic systems increases, the requirements for energy efficiency management, functional safety and real-time performance of heterogeneous multi-core chips are also increasing. The S32G heterogeneous multi-core chip system has become a key component of in-vehicle electronic systems due to its multi-core parallel processing capabilities, low-latency response and high reliability. However, existing power-on and power-off control strategies often cannot meet the comprehensive requirements of these systems for energy efficiency, safety and real-time performance under variable working conditions.

[0048] This application sends a first power-on control instruction to the second core in a heterogeneous multi-core chip when receiving an external wake-up request, so that the second core executes a startup program according to the first power-on control instruction; when the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to a parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes a startup program according to the second power-on control instruction. In the above manner, fast startup, high stability and high reliability of heterogeneous multi-core chips are achieved, and the comprehensive requirements of energy efficiency, safety and real-time performance of heterogeneous multi-core chips under variable working conditions are met.

[0049] It should be noted that the execution subject of this embodiment may be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or a control device of a heterogeneous multi-core chip capable of realizing the above functions, etc. The following takes the control device of a heterogeneous multi-core chip as an example of the execution subject to illustrate this embodiment and the following embodiments.

[0050] Based on this, an embodiment of the present application provides a control method for a heterogeneous multi-core chip, wherein the control method for a heterogeneous multi-core chip is applied to a main core of a first core, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the control method of a heterogeneous multi-core chip of the present application.

[0051] In this embodiment, the control method of the heterogeneous multi-core chip includes steps S10 to S20:

[0052] Step S10, when receiving an external wake-up request, sending a first power-on control instruction to a second core in the heterogeneous multi-core chip, so that the second core executes a startup program according to the first power-on control instruction;

[0053] It should be noted that the architecture diagram of the S32G heterogeneous multi-core chip system in this embodiment is as follows: Figure 2 As shown, the S32G heterogeneous multi-core chip system includes an A core and an M core, wherein the M core also includes core 0 (Core0), core 1 (Core1), core 2 (Core2) and core 3 (Core3), and this embodiment uses core 0 of the M core as the execution body.

[0054] It can be understood that the external wake-up request refers to a request signal for externally controlling the vehicle to wake up from a low power consumption mode to a normal working state, and the first power-on control instruction refers to an instruction for controlling the second core (core A) to switch to a power-on state.

[0055] In the specific implementation, when the M core of S32G receives a request signal from the external control vehicle to wake up from low power mode to normal working state, the operating system (OS) will initialize the startup on the core 0 of the M core (hereinafter referred to as the main core). In the initial operation stage, the main core is responsible for issuing a startup instruction to the A core to ensure that the A core (the second core) can respond in time and start its startup procedure.

[0056] In a feasible implementation, step S10 may include steps A11 to A12:

[0057] Step A11, upon receiving an external wake-up request, obtaining a system initialization state;

[0058] It can be understood that the system initialization state includes a completed state and an uncompleted state.

[0059] In a specific implementation, when the main core of the M core receives a request signal from an external control vehicle to wake up from a low-power mode to a normal working state, the S32G chip undergoes a hardware reset process to restore the system to its initial state, thereby determining the initialization state of the system.

[0060] Step A12, when the system initialization state is completed and the control authority transmitted by the third core of the heterogeneous multi-core chip is received, a first power-on control instruction is sent to the second core in the heterogeneous multi-core chip, and the control authority is transmitted after the third core completes the loading of the user firmware through the target firmware when the third core obtains the system integrity confirmation result by executing the target firmware.

[0061] It can be understood that the third core refers to a processor core (HSE_H core) located in the HSE_H subsystem, and the target firmware refers to firmware written by a user.

[0062] In the specific implementation, after the hardware reset is completed, the integrity of the system is checked. Once the system integrity is confirmed, the BootROM firmware will load the firmware or operating system written by the user into the memory and prepare to pass it to the main processor core for execution. After the user firmware is loaded, the HSE_H core will pass the control to the main processor core. The main processor core will start to execute the user firmware and take over the control of the system. The main core sends an instruction to control the second core (core A) to switch to the power-on state to the second core.

[0063] Step S20, when the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to the parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes the startup program according to the second power-on control instruction.

[0064] It can be understood that the parallel startup strategy refers to a strategy of parallel controlling the A core and the M cores so that they can enter the working state almost at the same time. The second power-on control instruction refers to an instruction for controlling the M cores (core 1, core 2 and core 3) to switch to the power-on state. The multiple sub-cores refer to core 1, core 2 and core 3 in the M core.

[0065] In the specific implementation, after completing the sending of the A core startup instruction, the main core continues to execute the parallel startup strategy and starts the remaining cores in the M core (core 1, core 2, core 3) in sequence. This strategy ensures that the A core and the M core can enter the working state almost at the same time, significantly shortening the overall system startup time. At the same time, through parallel startup, the system can establish a communication link between the cores in the fastest time to cope with the processing needs of various real-time events and improve the system response efficiency.

[0066] In a feasible implementation manner, the control method of the heterogeneous multi-core chip is applied to core 0 of M cores, and the method further includes steps S11 to S13:

[0067] Step S11, when there is no target wake-up source, sending a first sleep control instruction to a second core in the heterogeneous multi-core chip according to an inter-core communication mechanism, so that the second core executes a sleep program according to the first sleep control instruction and feeds back sleep confirmation information;

[0068] It can be understood that the target wake-up source includes external wake-up source (such as external interrupt, signal trigger, etc.) and internal wake-up source (such as timer, task scheduling, etc.), the inter-core communication mechanism refers to a pre-set mechanism for communication between cores, the first sleep control instruction refers to the instruction to control the second core (core A) to switch to sleep state, and the sleep confirmation information refers to the information indicating that core A has received the shutdown instruction.

[0069] In the specific implementation, the main core performs a comprehensive check to determine that there are no external wake-up sources (such as external interrupts, signal triggers, etc.) and internal wake-up sources (such as timers, task scheduling, etc.) to maintain the system wake-up state. Once it is confirmed that there are no such wake-up sources, the main core will issue a command to shut down the A core through the inter-core communication mechanism.

[0070] Step S12, when the sleep confirmation information fed back by the second core is received and the preset sleep duration is reached, sending a second sleep control instruction to the multiple sub-cores in the second core of the heterogeneous multi-core chip respectively, so that each sub-core executes a sleep program according to the second sleep control instruction and feeds back status confirmation information;

[0071] It can be understood that the preset sleep duration refers to the pre-set sleep waiting time, the second sleep control instruction refers to the instruction for controlling each core of the M core (core 1, core 2 and core 3) to switch to the sleep state, and the status confirmation information refers to the information indicating that each core of the M core (core 1, core 2 and core 3) has successfully entered the safe shutdown state.

[0072] In the specific implementation, the main core will use time reservation to ensure that core A has enough time to complete all shutdown operations. Once the main core detects that core A has been completely shut down, the main core sends a shutdown command to core 1, core 2, and core 3 through the system control interface. After completing the shutdown sequence, each sub-core will send a status confirmation signal to the main core, indicating that it has successfully entered the safe shutdown state.

[0073] Step S13: upon receiving the status confirmation information fed back by each sub-core, executing the target sleep program.

[0074] It can be understood that the target sleep program refers to a program that controls the main core to sleep.

[0075] In the specific implementation, after each sub-core completes the shutdown sequence, it will send a status confirmation signal to the main core, indicating that it has successfully entered the safe shutdown state. The main core will continue to monitor the shutdown status of cores 1, 2, and 3 to ensure that each core has completed the shutdown process as expected. After confirming that all sub-cores have been safely shut down, the main core will perform its own shutdown operation.

[0076] In this embodiment, when there is no target wake-up source, the first sleep control instruction is sent to the second core in the heterogeneous multi-core chip according to the inter-core communication mechanism, so that the second core executes the sleep program according to the first sleep control instruction and feeds back sleep confirmation information; when the sleep confirmation information fed back by the second core is received and the preset sleep duration is reached, the second sleep control instruction is sent to multiple sub-cores in the second core of the heterogeneous multi-core chip respectively, so that each sub-core executes the sleep program according to the second sleep control instruction and feeds back status confirmation information; when the status confirmation information fed back by each sub-core is received, the target sleep program is executed. In the above manner, the operating status of the core is intelligently monitored and dynamically adjusted, and the system optimizes energy consumption and improves energy efficiency.

[0077] In a feasible implementation manner, the control method of the heterogeneous multi-core chip is applied to core 0 of M cores, and the method further includes steps S21 to S23:

[0078] Step S21, when receiving the status confirmation information fed back by each sub-core, shutting down the target system service;

[0079] It is understandable that the target system service refers to all remaining system services. After confirming that all sub-cores have been safely shut down, the main core will perform its own shutdown operation, that is, shut down all remaining system services and tasks.

[0080] Step S22, when it is detected that the target system service is shut down, saving the core status information to the target storage location;

[0081] It can be understood that the core state information refers to the state information of the main core, and the target storage location refers to the location of the non-volatile storage.

[0082] In a specific implementation, when it is detected that all remaining system services have been shut down, the state information of the main core is saved to a non-volatile storage location.

[0083] Step S23, when it is detected that the core state information is saved completely, executing the target sleep program.

[0084] It is understandable that when it is detected that the state information of the main core has been saved, the operating frequency of the main core is actively reduced to the minimum to enter a low power consumption state, that is, a program for controlling the main core to enter a sleep state is executed.

[0085] In this implementation, when receiving the state confirmation information fed back by each sub-core, the target system service is shut down; when detecting that the shutdown of the target system service is completed, the core state information is saved to the target storage location; when detecting that the saving of the core state information is completed, the target hibernation program is executed. In this way, the continuity of key tasks and the integrity of data are ensured.

[0086] It should be noted that this embodiment improves system response speed and energy efficiency management through efficient parallel startup strategy and orderly sleep process. The specific implementation steps are described as follows: S1. When the S32G M core receives an external wake-up request, the operating system (OS) will initialize the startup on the core 0 of the M core (hereinafter referred to as the main core). In the initial operation stage, the main core is responsible for issuing a startup instruction to the A core to ensure that the A core can respond in time and start its startup program;

[0087] Further, step S1 specifically includes: first, the S32G chip undergoes a hardware reset process to restore the system to an initial state. After the hardware reset is completed, the HSE_H core (the processor core located in the HSE_H subsystem) becomes the only available processor core. The HSE_H core is mainly responsible for security-related functions, including executing firmware from the HSE_H ROM module. The HSE_H core starts to execute the BootROM firmware from the HSE_HROM module. The BootROM firmware is a read-only code pre-installed in the chip, which is responsible for initializing the hardware, checking the system integrity, and preparing to load the firmware or operating system written by the user. The BootROM firmware will perform a series of security policy checks to ensure that the software loaded into the system has not been tampered with and is authenticated. These checks may include verifying the digital signature of the firmware or operating system, checking the checksum, etc. Once the system integrity is confirmed, the BootROM firmware will load the firmware or operating system written by the user into the memory and prepare to pass it to the main processor core for execution. After the user firmware is loaded, the HSE_H core will pass control to the main processor core. The main processor core will start executing the user firmware and take over control of the system. After the BootROM phase is completed, uboot will boot the subsequent kernel. The main core starts to execute the main code of the operating system, including the startup of the A core. After the main core sends the startup A core instruction, the specific startup process of the A core is as follows: Figure 3 shown.

[0088] S2. After sending the start-up instruction of core A, the main core continues to execute the parallel start-up strategy and starts the remaining cores in core M (core 1, core 2, core 3) in sequence. This strategy ensures that the cores of core A and core M can enter the working state almost at the same time, significantly shortening the overall system startup time. At the same time, through parallel startup, the system can establish the communication link between the cores in the fastest time to cope with the processing requirements of various real-time events and improve the system response efficiency;

[0089] Furthermore, step S2 specifically includes: after completing the basic initialization, the main core (core 0) executes a detailed software configuration process, which not only includes setting up an efficient communication mechanism between cores (such as shared memory, message queues, etc.), but also involves customizing the operating environment configuration for each core, such as clock frequency, power management strategy, etc., to ensure that each core runs in the optimal state.

[0090] The main core triggers the internal interrupt service routine by sending an interrupt signal of a specific format to the core to be started, thereby realizing non-active wake-up and code execution startup. This mechanism effectively reduces the energy consumption and delay during the system startup process. In a multi-core processor system, especially for the four cores of the M-core architecture, the present invention introduces a synchronization mechanism based on mutex locks to ensure mutual exclusion and consistency in key links such as shared resource access and task scheduling, avoid data conflicts and deadlocks, and improve system stability.

[0091] During the development process, rigorous multi-core boot reliability and stability testing was implemented, including but not limited to performance testing in multiple configuration environments, fault injection testing, and active scanning and immediate repair of security vulnerabilities, to ensure that the system performs well under various operating conditions.

[0092] Regarding the security-sensitive operations involved in the process of the main core starting other cores, the present invention follows a set of strict security protocols and operating procedures, including but not limited to data encryption transmission, access permission control and security auditing, to fully ensure system security.

[0093] S3. Before the system enters the sleep phase, the main core will first issue a command to shut down the A core, and then enter a short waiting period to ensure that the A core has successfully received the shutdown command and completed its shutdown process. This sleep management strategy ensures the system's ability to wake up quickly in a low-power state and reduces potential damage to the A core caused by improper sleep operation;

[0094] Further, step S3 specifically includes: A core power management state machine schematic diagram is as follows Figure 4As shown in Table 1, before the system enters the sleep phase, in order to ensure the low power consumption of the system and reduce potential damage, the system implements a set of sophisticated sleep management strategies. First, the main core will conduct a comprehensive check to determine that there are no external wake-up sources (such as external interrupts, signal triggers, etc.) and internal wake-up sources (such as timers, task scheduling, etc.) to maintain the system wake-up state. Once it is confirmed that there are no such wake-up sources, the main core will issue an instruction to shut down the A core through the inter-core communication mechanism. The state machine of the A core is shown in Table 1. After receiving the shutdown instruction from the main core, the A core will immediately send a confirmation message to the main core, indicating that the shutdown instruction has been received, and start to execute the operation of shutting down all its running applications and processes. In this process, the A core will ensure that all key data is properly saved so that it can be restored to the correct state when it is woken up later. At the same time, the main core will use time reservation to ensure that the A core has enough time to complete all shutdown operations, including the shutdown of applications and processes, the preservation of key data, etc. Once the main core detects that the A core has been completely shut down and the system is in a stable state, the main core will start to execute its own shutdown procedure.

[0095] Table 1:

[0096]

[0097] S4. After ensuring that core A has been safely shut down, the main core continues to execute the shutdown operation of the remaining cores (core 1, core 2, and core 3) in core M. After these cores have successfully entered the sleep state, the main core will execute its own shutdown action to complete the sleep process of the entire system. This process not only ensures the orderly sleep of the system, but also further improves the energy efficiency of the system through refined management strategies.

[0098] Further, step S4 specifically includes: first, the main core completes all ongoing tasks or saves them to non-volatile storage. Ensure data synchronization of all cores to prevent data loss. The main core sends a shutdown command to core 1, core 2 and core 3 through the system control interface. After receiving the shutdown command, core 1, core 2 and core 3 will perform the following operations respectively: stop the currently executed task and ensure that all task states are properly saved; turn off the interrupt and event handling mechanism running locally; gradually reduce the operating frequency of the processor until it stops. After completing the shutdown sequence, each sub-core will send a status confirmation signal to the main core, indicating that it has successfully entered the safe shutdown state. The main core will continue to monitor the shutdown status of cores 1, 2 and 3 to ensure that each core has completed the shutdown process as expected. After confirming that all sub-cores have been safely shut down, the main core will perform its own shutdown operations, including but not limited to: shutting down all remaining system services and tasks; saving the status information of the main core to non-volatile storage; actively reducing its own operating frequency to the minimum and entering a low power consumption state. Ultimately, the master core will ensure that the power of the entire S32G chip system is properly managed and all necessary hardware components enter a low-power or shutdown state, completing the shutdown process of the entire system.

[0099] This embodiment sends a first power-on control instruction to the second core in the heterogeneous multi-core chip when receiving an external wake-up request, so that the second core executes the startup program according to the first power-on control instruction; when the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to the parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes the startup program according to the second power-on control instruction. In the above manner, the fast startup, high stability and high reliability of the heterogeneous multi-core chip are achieved, and the comprehensive requirements of the heterogeneous multi-core chip for energy efficiency, safety and real-time performance under variable working conditions are met.

[0100] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 5 The control method of the heterogeneous multi-core chip is applied to multiple sub-cores in a first core, and the method includes step S101:

[0101] Step S101, when receiving a second power-on control instruction sent by a main core of the first core, triggering an interrupt service routine according to the second power-on control instruction, and executing a startup program.

[0102] It can be understood that the interrupt service routine refers to a pre-written code for processing interrupt events, and this embodiment uses core 1, core 2 and core 3 of the M core as the execution body.

[0103] In a specific implementation, the main core sends an interrupt signal of a specific format to the core to be started, triggering its internal interrupt service routine, thereby achieving non-active wake-up and code execution startup.

[0104] In a feasible implementation, step S101 may include steps A1011 to A1013:

[0105] Step A1011, upon receiving the second sleep control instruction sent by the main core of the first core, saving the target task state;

[0106] It can be understood that the target task state refers to the tasks currently executed by core 1, core 2, and core 3 of the M cores.

[0107] In a specific implementation, when receiving the sleep instruction, core 1, core 2 and core 3 of the M cores respectively save the currently executed tasks.

[0108] Step A1012, when it is detected that the target task state is saved, the target processing mechanism is closed;

[0109] It can be understood that the target processing mechanism refers to the interrupt and event processing mechanism.

[0110] In a specific implementation, when it is detected that the tasks currently executed by core 1, core 2, and core 3 of the M cores are all saved and completed, the interrupt and event processing mechanism of the local operation is closed.

[0111] Step A1013, when it is detected that the shutdown of the target processing mechanism is completed, a sleep program is executed and status confirmation information is fed back to the main core of the first core.

[0112] It is understandable that when it is detected that the interrupt and event handling mechanism is shut down, the operating frequency of the processor is gradually reduced until it stops, and information indicating that it has successfully entered the safe shutdown state is fed back to the core 0 of the M cores.

[0113] This embodiment triggers an interrupt service routine according to the second power-on control instruction and executes a startup program when receiving the second power-on control instruction sent by the main core of the first core. The parallel startup mechanism realizes the synchronous and rapid startup of the A core and the M core, significantly shortens the system startup time, and improves the system response speed.

[0114] Based on the first embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 6 , the control method of the heterogeneous multi-core chip is applied to the second core, and the method includes step S201:

[0115] Step S201 , when receiving a first sleep control instruction sent by a main core of a first core, feeding back sleep confirmation information to the main core of the first core, and executing a sleep program when detecting that the key data is saved completely.

[0116] It can be understood that the key data refers to the key operating data in the A core, and the present embodiment takes the A core as the execution subject.

[0117] In the specific implementation, after receiving the shutdown command from the main core, the A core will immediately send a confirmation message to the main core, indicating that the shutdown command has been received, and start to execute the operation of shutting down all its running applications and processes. During this process, the A core will ensure that all key data is properly saved so that it can be restored to the correct state when it is woken up later.

[0118] This embodiment feeds back sleep confirmation information to the main core of the first core upon receiving the first power-on control instruction sent by the main core of the first core, and executes the sleep program upon detecting that the key data has been saved. In this way, the reliability of the system is improved, and the continuity of key tasks and the integrity of data are ensured.

[0119] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the control method of the heterogeneous multi-core chip of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0120] This application also provides a control device for a heterogeneous multi-core chip. Figure 7 The control device of the heterogeneous multi-core chip is applied to the main core of the first core, and the device includes:

[0121] The processing module 10 is used to start the operating system and send a first power-on control instruction to the second core in the heterogeneous multi-core chip when receiving an external wake-up request, so that the second core executes a startup program according to the first power-on control instruction;

[0122] The control module 20 is used to generate a second power-on control instruction according to a parallel startup strategy when the first power-on control instruction is sent to the second core, and to send the second power-on control instruction to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes a startup program according to the second power-on control instruction.

[0123] Optionally, the processing module 10 is further used for:

[0124] When receiving an external wake-up request, obtain the system initialization status;

[0125] When the system initialization state is the completion state and the control authority transmitted by the third core of the heterogeneous multi-core chip is received, a first power-on control instruction is sent to the second core in the heterogeneous multi-core chip. The control authority is transmitted after the third core completes the loading of the user firmware through the target firmware when the third core obtains the system integrity confirmation result by executing the target firmware.

[0126] Optionally, the processing module 10 is further used for:

[0127] When there is no target wake-up source, sending a first sleep control instruction to a second core in the heterogeneous multi-core chip according to an inter-core communication mechanism, so that the second core executes a sleep program according to the first sleep control instruction and feeds back sleep confirmation information;

[0128] When the sleep confirmation information fed back by the second core is received and the preset sleep duration is reached, a second sleep control instruction is sent to the multiple sub-cores in the second core of the heterogeneous multi-core chip respectively, so that each sub-core executes a sleep program according to the second sleep control instruction and feeds back status confirmation information;

[0129] When the status confirmation information fed back by each sub-core is received, the target sleep program is executed.

[0130] Optionally, the processing module 10 is further used for:

[0131] Upon receiving the status confirmation information fed back by each sub-core, shutting down the target system service;

[0132] When it is detected that the target system service is shut down, the core state information is saved to the target storage location;

[0133] When it is detected that the core state information is saved completely, a target sleep program is executed.

[0134] The present application also provides a control device for a heterogeneous multi-core chip, the control device for the heterogeneous multi-core chip is applied to multiple sub-cores in a first core, and the device includes:

[0135] The startup module 101 is used to trigger an interrupt service routine according to a second power-on control instruction and execute a startup program when receiving a second power-on control instruction sent by a main core of the first core.

[0136] Optionally, the startup module 10 is further used to:

[0137] When it is detected that the target task state is saved, closing the target processing mechanism;

[0138] When it is detected that the shutdown of the target processing mechanism is completed, a sleep program is executed and status confirmation information is fed back to the main core of the first core.

[0139] The present application also provides a control device for a heterogeneous multi-core chip, wherein the control device for the heterogeneous multi-core chip is applied to a second core, and the device includes:

[0140] The sleep module 102 is used to feed back sleep confirmation information to the main core of the first core when receiving the first sleep control instruction sent by the main core of the first core, and execute the sleep program when detecting that the key data is saved.

[0141] The control device of the heterogeneous multi-core chip provided by the present application adopts the control method of the heterogeneous multi-core chip in the above-mentioned embodiment, which can solve the technical problem that the existing power-on and power-off control strategy often cannot meet the comprehensive requirements of energy efficiency, safety and real-time performance of the heterogeneous multi-core chip system under variable working conditions. Compared with the prior art, the beneficial effects of the control device of the heterogeneous multi-core chip provided by the present application are the same as the beneficial effects of the control method of the heterogeneous multi-core chip provided by the above-mentioned embodiment, and the other technical features in the control device of the heterogeneous multi-core chip are the same as the features disclosed in the above-mentioned embodiment method, which will not be repeated here.

[0142] The present application provides a control device for a heterogeneous multi-core chip, the control device for a heterogeneous multi-core chip comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the control method for the heterogeneous multi-core chip in the above-mentioned embodiment 1.

[0143] Reference below Figure 8 , which shows a schematic diagram of the structure of a control device for a heterogeneous multi-core chip suitable for implementing an embodiment of the present application. The control device for the heterogeneous multi-core chip in the embodiment of the present application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The control device of the heterogeneous multi-core chip shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0144] like Figure 8As shown, the control device of the heterogeneous multi-core chip may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. Various programs and data required for the operation of the control device of the heterogeneous multi-core chip are also stored in RAM1004. The processing device 1001, ROM1002 and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1003 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009. The communication device 1009 may allow the control device of the heterogeneous multi-core chip to communicate wirelessly or wired with other devices to exchange data. Although the figure shows a control device of a heterogeneous multi-core chip with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have alternatively.

[0145] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0146] The control device of the heterogeneous multi-core chip provided by the present application adopts the control method of the heterogeneous multi-core chip in the above embodiment, which can solve the technical problem that the existing power-on and power-off control strategy often cannot meet the comprehensive requirements of energy efficiency, safety and real-time performance of the heterogeneous multi-core chip system under variable working conditions. Compared with the prior art, the beneficial effects of the control device of the heterogeneous multi-core chip provided by the present application are the same as the beneficial effects of the control method of the heterogeneous multi-core chip provided by the above embodiment, and the other technical features in the control device of the heterogeneous multi-core chip are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0147] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0148] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0149] In addition, to achieve the above objectives, the present invention also proposes a control system for a heterogeneous multi-core chip, wherein the control system for the heterogeneous multi-core chip includes the main core of the first core described above, multiple sub-cores in the first core, and a second core.

[0150] Since the control system of the heterogeneous multi-core chip adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0151] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the control method of the heterogeneous multi-core chip in the above-mentioned embodiment.

[0152] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0153] The computer-readable storage medium may be included in the control device of the heterogeneous multi-core chip; or may exist independently without being assembled into the control device of the heterogeneous multi-core chip.

[0154] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the control device of the heterogeneous multi-core chip, the control device of the heterogeneous multi-core chip: when receiving an external wake-up request, sends a first power-on control instruction to the second core in the heterogeneous multi-core chip, so that the second core executes the startup program according to the first power-on control instruction; when the first power-on control instruction is sent to the second core, generates a second power-on control instruction according to a parallel startup strategy, and sends the second power-on control instruction to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes the startup program according to the second power-on control instruction.

[0155] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0156] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0157] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0158] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the control method of the above-mentioned heterogeneous multi-core chip, and can solve the technical problem that the existing power-on and power-off control strategies often cannot meet the comprehensive requirements of energy efficiency, safety, and real-time performance of the heterogeneous multi-core chip system under variable working conditions. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the control method of the heterogeneous multi-core chip provided by the above-mentioned embodiment, and will not be repeated here.

[0159] The present application also provides a computer program product, including a computer program, which implements the steps of the control method of the heterogeneous multi-core chip as described above when executed by a processor.

[0160] The computer program product provided by the present application can solve the technical problem that the existing power-on and power-off control strategies often cannot meet the comprehensive requirements of energy efficiency, safety and real-time performance of heterogeneous multi-core chip systems under variable working conditions. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the control method of the heterogeneous multi-core chip provided by the above-mentioned embodiment, which will not be repeated here.

[0161] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A control method for a heterogeneous multi-core chip, It is characterized in that The control method of the heterogeneous multi-core chip is applied to the main core of the first core, and the method includes: Upon receiving an external wake-up request, sending a first power-on control instruction to a second core in the heterogeneous multi-core chip, so that the second core executes a startup program according to the first power-on control instruction; When the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to the parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes the startup program according to the second power-on control instruction.

2. The method according to claim 1, It is characterized in that The method of sending a first power-on control instruction to a second core in the heterogeneous multi-core chip upon receiving an external wake-up request includes: When receiving an external wake-up request, obtain the system initialization status; When the system initialization state is the completion state and the control authority transmitted by the third core of the heterogeneous multi-core chip is received, a first power-on control instruction is sent to the second core in the heterogeneous multi-core chip. The control authority is transmitted after the third core completes the loading of the user firmware through the target firmware when the third core obtains the system integrity confirmation result by executing the target firmware.

3. The method according to claim 1, It is characterized in that The control method of the heterogeneous multi-core chip further comprises: When there is no target wake-up source, sending a first sleep control instruction to a second core in the heterogeneous multi-core chip according to an inter-core communication mechanism, so that the second core executes a sleep program according to the first sleep control instruction and feeds back sleep confirmation information; When the sleep confirmation information fed back by the second core is received and the preset sleep duration is reached, a second sleep control instruction is sent to the multiple sub-cores in the second core of the heterogeneous multi-core chip respectively, so that each sub-core executes a sleep program according to the second sleep control instruction and feeds back status confirmation information; When the status confirmation information fed back by each sub-core is received, the target sleep program is executed.

4. The method according to claim 1, It is characterized in that The method further comprises: Upon receiving the status confirmation information fed back by each sub-core, shutting down the target system service; When it is detected that the target system service is shut down, the core state information is saved to the target storage location; When it is detected that the core state information is saved completely, a target sleep program is executed.

5. A control method for a heterogeneous multi-core chip, It is characterized in that The control method of the heterogeneous multi-core chip is applied to multiple sub-cores in a first core, and the control method of the heterogeneous multi-core chip includes: When a second power-on control instruction sent by the main core of the first core is received, an interrupt service routine is triggered according to the second power-on control instruction, and a startup program is executed.

6. The method according to claim 5, It is characterized in that The method further comprises: When receiving the second sleep control instruction sent by the main core of the first core, saving the target task state; When it is detected that the target task state is saved, the target processing mechanism is closed; When it is detected that the shutdown of the target processing mechanism is completed, a sleep program is executed and status confirmation information is fed back to the main core of the first core.

7. A control method for a heterogeneous multi-core chip, It is characterized in that The control method of the heterogeneous multi-core chip is applied to the second core, and the control method of the heterogeneous multi-core chip includes: When receiving the first sleep control instruction sent by the main core of the first core, sleep confirmation information is fed back to the main core of the first core, and when detecting that the key data is saved completely, a sleep program is executed.

8. A control device for a heterogeneous multi-core chip, It is characterized in that The device comprises: A processing module, configured to, upon receiving an external wake-up request, start the operating system and send a first power-on control instruction to a second core in the heterogeneous multi-core chip, so that the second core executes a startup program according to the first power-on control instruction; A control module is used to generate a second power-on control instruction according to a parallel startup strategy when the first power-on control instruction is sent to the second core, and to send the second power-on control instruction to multiple sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes a startup program according to the second power-on control instruction.

9. A control device for a heterogeneous multi-core chip, It is characterized in that The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the control method for a heterogeneous multi-core chip applied to a main core of a first core as described in any one of claims 1 to 4, or the control method for a heterogeneous multi-core chip applied to multiple sub-cores in the first core as described in claim 5 or 6, or the control method for a heterogeneous multi-core chip as described in claim 7.

10. A control system for heterogeneous multi-core chips. It is characterized in that The control system of the heterogeneous multi-core chip comprises the main core of the first core as described in any one of claims 1 to 4 above, a plurality of sub-cores in the first core as described in any one of claims 5 to 6, and the second core as described in claim 7 above.

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