Method and system for efficiently switching FPGA loading logic versions

Abstract

The invention provides a method and a system for efficiently switching FPGA (Field Programmable Gate Array) loading logic versions. The method comprises the following steps of: writing a configuration field and a plurality of logic configuration file versions into a flash; and the FPGA reads the configuration field from the flash to obtain the address of the default loading version, completes loading of the default loading version, can store and modify the configuration field, modifies the jump address in the configuration field into the flash address of the ith version needing to be switched and loaded, then erases the configuration field in the flash, rewrites the modified configuration field into the flash, and completes loading of the default loading version. And updating and storing the modified configuration field in the flash. And after finishing rewriting the configuration field of the flash, the FPGA is powered off and restarted to read the configuration field in the flash again, reads the jump address and loads the modified version, and after the loading is finished, the function switching of the FPGA is realized. According to the method, flexible switching among multiple FPGA logic configuration file versions can be realized, the operation is simple and efficient, the operation risk is obviously reduced compared with the whole flash erasing, and the method is suitable for the complex scene of FPGA equipment function switching.

Description

Technical Field

[0001] The present invention relates to the field of FPGA equipment technology, and in particular to a method for efficiently switching FPGA loading logic versions. Background Art

[0002] When the FPGA device is powered on, it will load the program stored in the flash into the FPGA. After the program is loaded, the FPGA device can be used normally. Figure 1 The connection relationship between FPGA and flash is shown. The program loaded from flash determines the functions of the FPGA device. In the current usage scenario, an FPGA version is usually stored in flash. When the device is powered on, the FPGA reads and loads the program from flash and then works.

[0003] On this basis, the prior art proposes a more optimized loading solution, that is, storing two FPGA configuration files in the flash: version A and version B. When the device is powered on, version A is loaded. If version A fails to load, version B is loaded. This optimized design increases the stability of the FPGA program loading process from the flash. However, this solution only has the function of version A under normal loading conditions. When version A fails to load, it has the function of version B, that is, this solution does not have the certainty of loading versions.

[0004] When the function of the FPGA device needs to be replaced, the program in the flash can only be updated. For example, the current flash stores version A. After the FPGA is powered on, it will have the function of version A after loading from the flash. If the FPGA device needs to have the function of version B at this time, it is necessary to erase version A in the flash, and then rewrite version B. When it is powered on next time, the FPGA will load version B from the flash, so that the FPGA device has the function of version B.

[0005] The above replacement scheme has poor flexibility. If the function of the FPGA device needs to be replaced, the flash content needs to be erased and rewritten, which takes a long time. In addition, if an unexpected situation occurs during the erasing or writing process, such as power failure, the FPGA device will not work. Summary of the invention

[0006] In view of the technical problems and defects in the prior art, according to a first aspect of the present invention, a method for efficiently switching FPGA loading logic versions is proposed, comprising the following steps:

[0007] Writing a configuration field and m logic configuration file versions that can be loaded into the FPGA into the flash, and configuring one of the multiple logic configuration file versions as a default loading version, wherein the flash address of the default loading version is written into the jump address in the configuration field, and m is a positive integer greater than or equal to 2;

[0008] After power-on, the FPGA reads the configuration field from the flash and loads the default loading version configured in the configuration field, and after the loading is completed, the FPGA is enabled to implement the FPGA function corresponding to the default loading version;

[0009] In response to the FPGA function switching and the need to load the i-th version of the plurality of logic configuration file versions, the FPGA reads the configuration field in the flash and stores it in the memory;

[0010] FPGA erases the configuration fields stored in the flash;

[0011] The FPGA reads the configuration field in the memory, modifies the jump address therein to the address of the i-th version, and then rewrites the modified configuration field into the flash, so that the flash updates and stores the modified configuration field, where i≤m;

[0012] The FPGA is powered off and restarted, and after powering on again, the modified configuration field is read from the flash, the jump address is read and the i-th version is loaded, and after the loading is completed, the FPGA is enabled to implement the FPGA function corresponding to the i-th version, thereby realizing the function switching of the FPGA.

[0013] According to a second aspect of the present invention, a system for efficiently switching FPGA loading logic versions is provided, comprising:

[0014] flash, which is connected to the FPGA and used to store a configuration field and m logic configuration file versions that can be loaded into the FPGA, one of the multiple logic configuration file versions is configured as a default loading version, and a flash address of the default loading version is written into a jump address in the configuration field, wherein m is a positive integer greater than or equal to 2;

[0015] The FPGA is configured to read the configuration field from the flash to obtain the address of the default loaded version, complete the loading of the default loaded version, and store and modify the configuration field, modify the jump address therein to the flash address of the i-th logical configuration file version to be switched and loaded, and then erase the configuration field in the flash and rewrite the modified configuration field into the flash, so that the modified configuration field is updated and stored in the flash;

[0016] Among them, after the FPGA completes rewriting the modified configuration field in the flash, it reads the configuration field in the flash again by powering off and restarting, reads the jump address and loads the i-th version. After the loading is completed, the FPGA can implement the FPGA function corresponding to the i-th version, thereby realizing the function switching of the FPGA.

[0017] The system and method for efficiently switching FPGA loading logic versions proposed by the present invention can write multiple versions in the flash, and can realize flexible switching between multiple FPGA logic configuration file versions. The operation is simple and efficient, and the operation risk is significantly reduced compared to erasing the entire flash. It can be applied to complex scenarios of FPGA device function switching.

[0018] Compared with the prior art, the system and method for efficiently switching FPGA loading logic versions of the present invention have the following significant advantages:

[0019] 1. Provide fast switching and recovery capabilities: Allow FPGA to quickly switch between different logic configuration files. By pre-storing multiple configuration versions in the flash, the FPGA can select different configurations by modifying the jump address in the configuration field when needed. This can quickly switch the FPGA function, which is suitable for applications that require fast response to external changes or fault recovery;

[0020] 2. Enhance the flexibility of FPGA devices: By storing multiple configuration files, users can select different logic configurations according to different application requirements, and the maintenance and update process is simple. To update the logic version loaded by FPGA, the configuration field in the flash can be modified through FPGA and the flash can be erased and rewritten, making the maintenance and upgrade process faster and more efficient. At the same time, the part that is erased and rewritten to the flash is limited to the configuration file. The operation process is simple, fast and safe, which improves the reliability and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are not intended to be drawn to scale. In the accompanying drawings, each identical or nearly identical component shown in each figure may be represented by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings.

[0022] Figure 1 It is a schematic diagram of the connection between FPGA and flash according to an embodiment of the present invention.

[0023] Figure 2 The flowchart of the method for efficiently switching FPGA loading logic version according to an embodiment of the present invention.

[0024] Figure 3 It is a schematic diagram of configuration fields written in flash and multiple logical configuration file versions according to an embodiment of the present invention.

[0025] Figure 4 It is a schematic diagram of configuration fields written in flash and three logical configuration file versions according to an embodiment of the present invention.

[0026] Figure 5 is based on Figure 4 Embodiment, schematic diagram of configuration fields when the default loading version is configured as B.

[0027] Figure 6 is based on Figure 4 In the embodiment, the FPGA is a schematic diagram of modifying the jump address field in the configuration field to the address of version C. DETAILED DESCRIPTION

[0028] In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.

[0029] {Example 1}

[0030] Combination Figure 1 , 2 As shown in FIG. 3 , the method for efficiently switching FPGA loading logic versions according to an example of the present invention includes the following steps:

[0031] Writing a configuration field and m logic configuration file versions that can be loaded into the FPGA into the flash, and configuring one of the multiple logic configuration file versions as a default loading version, wherein the flash address of the default loading version is written into the jump address in the configuration field, and m is a positive integer greater than or equal to 2;

[0032] After power-on, the FPGA reads the configuration field from the flash and loads the default loading version configured in the configuration field, and after the loading is completed, the FPGA is enabled to implement the FPGA function corresponding to the default loading version;

[0033] In response to the FPGA function switching and the need to load the i-th version of the plurality of logic configuration file versions, the FPGA reads the configuration field in the flash and stores it in the memory;

[0034] FPGA erases the configuration fields stored in the flash;

[0035] The FPGA reads the configuration field in the memory, modifies the jump address therein to the address of the i-th version, and then rewrites the modified configuration field into the flash, so that the flash updates and stores the modified configuration field, where i≤m;

[0036] The FPGA is powered off and restarted, and after powering on again, the modified configuration field is read from the flash, the jump address is read and the i-th version is loaded, and after the loading is completed, the FPGA is enabled to implement the FPGA function corresponding to the i-th version, thereby realizing the function switching of the FPGA.

[0037] Combination Figure 3 As shown, as an optional implementation, the aforementioned configuration field includes a synchronization header, a loading time register address, a loading time value, a jump address register address and a jump address, and the jump address is configured to write the flash address corresponding to the storage of the logic configuration file version.

[0038] Combination Figure 3 As shown, as an optional implementation, each of the m logic configuration file versions is independently stored in the flash, and the first line address and the end mark of each logic configuration file version stored in the flash are recorded.

[0039] As an optional implementation, after power-on, the FPGA reads the configuration field from the flash and loads the default loading version configured in the configuration field, including the following process:

[0040] Step 1.1, read the contents in the flash starting from flash address 0, and when the synchronization header in the configuration field is detected, start reading the load time register address, and after obtaining the address, fill in the load time value field in the corresponding register address;

[0041] Step 1.2, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the address, fill in the jump address in the corresponding register address, that is, the flash address of the default loaded version;

[0042] Step 1.3: Jump to the flash address of the default loaded version, start loading the default loaded version from the first row address, and until the end mark of the default loaded version is detected, the version loading is completed.

[0043] As an optional implementation, the FPGA is powered off and restarted, and after powering on again, the modified configuration field is read from the flash, the jump address is read, and the i-th version is loaded, including the following process:

[0044] Step 2.1, power off and restart the FPGA;

[0045] Step 2.2, after powering on again, the FPGA starts reading the contents in the flash from flash address 0. When the synchronization header in the configuration field after the update storage modification is detected, it starts reading the load time register address. After obtaining the address, fill in the load time value field in the corresponding register address;

[0046] Step 2.3, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the i-th version, fill in the jump address field in the corresponding register address with the address of the i-th version;

[0047] Step 2.4: Jump to the flash address of the ith version, start loading the version from the first line address of the ith version, until the end mark of the ith version is detected, and the ith version is loaded.

[0048] {Example 2}

[0049] Combination Figure 1 , 2 3. According to an embodiment of the present invention, a system for efficiently switching FPGA loading logic versions is also provided, including flash and FPGA.

[0050] The flash is configured to be connected to the FPGA and is used to store configuration fields and m logic configuration file versions that can be loaded into the FPGA, one of the multiple logic configuration file versions is configured as a default loading version, and the flash address of the default loading version is written into the jump address in the configuration field, where m is a positive integer greater than or equal to 2.

[0051] The FPGA is configured to read the configuration field from the flash to obtain the address of the default loaded version, complete the loading of the default loaded version, and store and modify the configuration field, modify the jump address therein to the flash address of the i-th logical configuration file version that needs to be switched to load, and then erase the configuration field in the flash and rewrite the modified configuration field into the flash, so that the modified configuration field is updated and stored in the flash.

[0052] Among them, after the aforementioned FPGA completes rewriting the modified configuration field in the flash, it reads the configuration field in the flash again by powering off and restarting, reads the jump address and loads the i-th version. After the loading is completed, the FPGA can implement the FPGA function corresponding to the i-th version, thereby realizing the function switching of the FPGA.

[0053] As an optional implementation, Figure 3As shown, the aforementioned configuration field includes a synchronization header, a loading time register address, a loading time value, a jump address register address, and a jump address, and the jump address is configured to be used to write the flash address corresponding to the storage of the logic configuration file version.

[0054] like Figure 3 As shown, each of the m logic configuration file versions is independently stored in the flash, and the first line address and the end mark of each logic configuration file version stored in the flash are recorded.

[0055] As an optional implementation, the FPGA is configured to complete the operation of reading the configuration field from the flash to obtain the address of the default loaded version therein and completing the loading of the default loaded version in the following manner:

[0056] Step 1.1, read the contents in the flash starting from flash address 0, and when the synchronization header in the configuration field is detected, start reading the load time register address, and after obtaining the address, fill in the load time value field in the corresponding register address;

[0057] Step 1.2, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the address, fill in the jump address in the corresponding register address, that is, the flash address of the default loaded version;

[0058] Step 1.3: Jump to the flash address of the default loaded version, start loading the default loaded version from the first row address, and until the end mark of the default loaded version is detected, the version loading is completed.

[0059] As an optional implementation, the FPGA is configured to complete the operation of reading the configuration field in the flash again by powering off and restarting, reading the jump address and loading the i-th version in the following manner:

[0060] Step 2.1, power off and restart the FPGA;

[0061] Step 2.2, after powering on again, the FPGA starts reading the contents in the flash from flash address 0. When the synchronization header in the configuration field after the update storage modification is detected, it starts reading the load time register address. After obtaining the address, fill in the load time value field in the corresponding register address;

[0062] Step 2.3, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the i-th version, fill in the jump address field in the corresponding register address with the address of the i-th version;

[0063] Step 2.4: Jump to the flash address of the ith version, start loading the version from the first line address of the ith version, until the end mark of the ith version is detected, and the ith version is loaded.

[0064] {Example 3}

[0065] Combination Figure 1 , 2 , 3 and the above embodiments of the method for efficiently switching FPGA loading logic version, in this embodiment, we combine the attached Figure 4 The specific exemplary configuration of the above-mentioned process of efficiently switching the loaded version is further explained.

[0066] In this embodiment, if the FPGA needs to implement flexible switching between N versions, the content written into the flash includes the configuration field and multiple logical configuration file versions (version A, ending with version A; version B, ending with version B; ...; version N, ending with version N). Figure 3 As shown, each logical configuration file version has an end marker set.

[0067] The configuration field includes information such as synchronization header, loading time register address, loading time value, jump address register address, jump address, etc., wherein the jump address is the flash address of the default loading version. In this example, version A is used as the default loading version for illustration.

[0068] For ease of explanation, the first line address of version A in the flash is a, the first line address of version B in the flash is b, ..., and the first line address of version N in the flash is n.

[0069] (I) FPGA is powered on, and the process of FPGA loading the version from flash is as follows:

[0070] Step 1-1, read the contents of the flash starting from flash address 0, and when the synchronization header in the configuration field is detected, start reading the load time register address, and after obtaining the address, fill in the load time value field in the corresponding register address;

[0071] Step 1-2, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the address, fill in the jump address in the corresponding register address; if the flash address of the default loaded version is a, fill in the value a in the jump address register;

[0072] Step 1-3, jump to address a of the flash to start loading version A, until the end mark of version A is detected, and version A is loaded.

[0073] After version A is loaded, the FPGA device will be able to implement the functions of version A.

[0074] If the FPGA device function needs to be switched to the function of version B at this time, it is necessary to quickly switch to load version B (whose first line address is b). In combination with the method for efficiently switching the loaded version in the above embodiment, the specific operation is as follows:

[0075] Step 2-1, FPGA reads the configuration field content in the flash and stores the read content in the memory;

[0076] Step 2-2, erase the configuration field in the flash;

[0077] Step 2-3, read out the configuration field stored in the memory, and modify the jump address field therein to the first row address b of version B, and rewrite the modified configuration field into the flash;

[0078] Step 2-4: Power off and restart the FPGA;

[0079] Step 2-5: After the FPGA is powered on again, it starts reading the contents of the flash from flash address 0. When the synchronization header in the configuration field is detected, it starts reading the load time register address. After obtaining the address, it fills in the load time value field in the corresponding register address.

[0080] Step 2-6, continue to read the contents of the flash, obtain the jump address register address, after obtaining address b, fill in the jump address b in the corresponding register address;

[0081] Step 2-7: Jump to address b of the flash and start loading version B until the end mark of version B is detected and version B is loaded.

[0082] At this point, after version B is loaded, the FPGA will be able to implement the corresponding functions of version B.

[0083] On this basis, if you need to switch to other versions, continue to repeat the aforementioned steps 2-1 to 2-7, modify the jump address to the first row address of the version you need to switch, rewrite the FPGA to the flash and reload it after powering off and restarting, to achieve fast switching and loading of the new version and complete fast function switching.

[0084] like Figure 4 As shown, three versions A, B, and C written in the flash are taken as an example.

[0085] Configure the default version B to load, such as Figure 5 The configuration fields are shown as examples.

[0086] Among them, the synchronization field is AA995566, the load time register address is 30022001, the load time value is 4003D000, the jump address register address is 30020001, and the jump address is 01000000, that is, the default jump flash address is 01000000, which is the starting address of version B.

[0087] Thus, version B is loaded from the starting address of version B until the end mark of version B is detected and the loading is terminated. At this time, the FPGA has the corresponding functions of version B.

[0088] If you need to switch the FPGA to version C, you need to switch to loading version C. The specific operations according to steps 2-1 to 2-7 above are as follows:

[0089] Step 2-1, FPGA reads the configuration field content in the flash and stores the read content in the memory;

[0090] Step 2-2, erase the configuration field in the flash;

[0091] Step 2-3, read out the configuration field stored in the memory, and modify the jump address field to the starting address 02000000 of version C, such as Figure 6 As shown, the modified configuration fields are then rewritten into the flash;

[0092] Step 2-4: Power off and restart the FPGA;

[0093] Step 2-5: After the FPGA is powered on again, it starts reading the contents of the flash from flash address 0. When the synchronization header in the configuration field is detected, it starts reading the load time register address. After obtaining the address, it fills in the load time value field in the corresponding register address.

[0094] Step 2-6, continue to read the contents of the flash, obtain the jump address register address, after obtaining the address 02000000, fill in the jump address 02000000 in the corresponding register address;

[0095] Step 2-7: Jump to the address 02000000 of the flash to start loading version C until the end mark of version C is detected, and version C is loaded.

[0096] At this point, the FPGA logic configuration file is quickly switched and loaded from version B to version C. At this point, the FPGA has the functions of version C, and fast switching of functions is achieved.

[0097] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A method for efficiently switching FPGA loading logic versions, characterized in that: The following steps are involved: Writing a configuration field and m logic configuration file versions that can be loaded into the FPGA into the flash, and configuring one of the multiple logic configuration file versions as a default loading version, wherein the flash address of the default loading version is written into the jump address in the configuration field, and m is a positive integer greater than or equal to 2; After power-on, the FPGA reads the configuration field from the flash and loads the default loading version configured in the configuration field, and after the loading is completed, the FPGA is enabled to implement the FPGA function corresponding to the default loading version; In response to the FPGA function switching and the need to load the i-th version of the plurality of logic configuration file versions, the FPGA reads the configuration field in the flash and stores it in the memory; FPGA erases the configuration fields stored in the flash; The FPGA reads the configuration field in the memory, modifies the jump address therein to the address of the i-th version, and then rewrites the modified configuration field into the flash, so that the flash updates and stores the modified configuration field, where i≤m; The FPGA is powered off and restarted, and after powering on again, the modified configuration field is read from the flash, the jump address is read and the i-th version is loaded, and after the loading is completed, the FPGA is enabled to implement the FPGA function corresponding to the i-th version, thereby realizing the function switching of the FPGA.

2. The method for efficiently switching FPGA loading logic versions according to claim 1, characterized in that: The configuration field includes a synchronization header, a load time register address, a load time value, a jump address register address, and a jump address, and the jump address is configured to be used to write a flash address corresponding to the storage of the logic configuration file version.

3. The method for efficiently switching FPGA loading logic versions according to claim 1, characterized in that: Each of the m logic configuration file versions is independently stored in the flash, and the first line address and the end mark of each logic configuration file version stored in the flash are recorded.

4. The method for efficiently switching FPGA loading logic versions according to claim 1, characterized in that: After power-on, the FPGA reads the configuration field from the flash and loads the default loading version configured in the configuration field, including the following process: Step 1.1, read the contents in the flash starting from flash address 0, and when the synchronization header in the configuration field is detected, start reading the load time register address, and after obtaining the address, fill in the load time value field in the corresponding register address; Step 1.2, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the address, fill in the jump address in the corresponding register address, that is, the flash address of the default loaded version; Step 1.3: Jump to the flash address of the default loaded version, start loading the default loaded version from the first row address, and until the end mark of the default loaded version is detected, the version loading is completed.

5. The method for efficiently switching FPGA loading logic versions according to claim 1, characterized in that: The FPGA is powered off and restarted, and after being powered on again, the modified configuration field is read from the flash, the jump address is read, and the i-th version is loaded, including the following processes: Step 2.1, power off and restart the FPGA; Step 2.2, after powering on again, the FPGA starts reading the contents in the flash from flash address 0. When the synchronization header in the configuration field after the update storage modification is detected, it starts reading the load time register address. After obtaining the address, fill in the load time value field in the corresponding register address; Step 2.3, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the i-th version, fill in the jump address field in the corresponding register address with the address of the i-th version; Step 2.4: Jump to the flash address of the ith version, start loading the version from the first line address of the ith version, until the end mark of the ith version is detected, and the ith version is loaded.

6. A system for efficiently switching FPGA loading logic versions, characterized in that: include: flash, which is connected to the FPGA and used to store a configuration field and m logic configuration file versions that can be loaded into the FPGA, one of the multiple logic configuration file versions is configured as a default loading version, and a flash address of the default loading version is written into a jump address in the configuration field, wherein m is a positive integer greater than or equal to 2; The FPGA is configured to read the configuration field from the flash to obtain the address of the default loaded version, complete the loading of the default loaded version, and store and modify the configuration field, modify the jump address therein to the flash address of the i-th logical configuration file version to be switched and loaded, and then erase the configuration field in the flash and rewrite the modified configuration field into the flash, so that the modified configuration field is updated and stored in the flash; Among them, after the FPGA completes rewriting the modified configuration field in the flash, it reads the configuration field in the flash again by powering off and restarting, reads the jump address and loads the i-th version. After the loading is completed, the FPGA can implement the FPGA function corresponding to the i-th version, thereby realizing the function switching of the FPGA.

7. The system for efficiently switching FPGA loading logic versions according to claim 6, characterized in that: The configuration field includes a synchronization header, a load time register address, a load time value, a jump address register address, and a jump address, and the jump address is configured to be used to write a flash address corresponding to the storage of the logic configuration file version.

8. The system for efficiently switching FPGA loading logic versions according to claim 6, characterized in that: Each of the m logic configuration file versions is independently stored in the flash, and the first line address and the end mark of each logic configuration file version stored in the flash are recorded.

9. The system for efficiently switching FPGA loading logic versions according to claim 6, characterized in that: The FPGA is configured to complete the operation of reading the configuration field from the flash to obtain the address of the default loaded version therein and completing the loading of the default loaded version in the following manner: Step 1.1, read the contents in the flash starting from flash address 0, and when the synchronization header in the configuration field is detected, start reading the load time register address, and after obtaining the address, fill in the load time value field in the corresponding register address; Step 1.2, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the address, fill in the jump address in the corresponding register address, that is, the flash address of the default loaded version; Step 1.3: Jump to the flash address of the default loaded version, start loading the default loaded version from the first row address, and until the end mark of the default loaded version is detected, the version loading is completed.

10. The system for efficiently switching FPGA loading logic versions according to claim 6, characterized in that: The FPGA is configured to complete the operations of reading the configuration field in the flash again by powering off and restarting, reading the jump address and loading the i-th version in the following manner: Step 2.1, power off and restart the FPGA; Step 2.2, after powering on again, the FPGA starts reading the contents in the flash from flash address 0. When the synchronization header in the configuration field after the update storage modification is detected, it starts reading the load time register address. After obtaining the address, fill in the load time value field in the corresponding register address; Step 2.3, continue to read the contents in the flash, obtain the jump address register address, and after obtaining the i-th version, fill in the jump address field in the corresponding register address with the address of the i-th version; Step 2.4: Jump to the flash address of the ith version, start loading the version from the first line address of the ith version, until the end mark of the ith version is detected, and the ith version is loaded.

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