Control system and server

Abstract

The invention provides a control system and a server, and relates to the technical field of computer mainboards, the control system comprises a processor, a CPLD unit module, a BMC module and a plurality of BIOS chips; wherein the processor, the BMC module and the plurality of BIOS chips are all connected with the CPLD unit module; the BMC module is used for monitoring a system state so as to determine whether the currently used BIOS chip is available or not; if yes, notifying the currently used BIOS chip to be connected with the processor; and if not, the CPLD unit module is notified to switch the currently used BIOS chip. The CPLD unit module is used as a control center, and the characteristics of dynamic monitoring, automatic switching, efficient control center, system-level integrated management and the like are introduced, so that on the premise of not greatly increasing the hardware cost, the system function and reliability can be enhanced, and the downtime of a server and the workload of maintenance personnel can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computer mainboards, and in particular to a control system and a server. Background Art

[0002] In recent years, with the improvement of information technology, the application of servers has become more and more extensive, and the resulting information security issues have attracted more and more attention from countries around the world. At present, a large number of domestic servers have emerged under the information security, most of which use a single BIOS chip. If the BIOS chip fails, the machine will be down and unusable, which will cause serious consequences. Considering the lack of security performance, this involves redundant backup and encryption algorithms, which have become urgent problems to be solved in the field of domestic servers.

[0003] Therefore, how to solve the problem that the existing motherboards based on domestic servers are relatively complex in design, high in cost, low in integration, and the management chip performance expansion is insufficient, which is far from meeting users' management and maintenance needs for domestic server products has become an urgent problem to be solved by technical personnel in this field. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a control system and a server with high integration and cost advantages, which can reduce the response time of motherboard failures and improve the reliability and safety of the server.

[0005] In a first aspect, an embodiment of the present invention provides a control system, wherein the control system includes: a processor, a CPLD unit module, a BMC module, and multiple BIOS chips; wherein the processor, the BMC module, and the multiple BIOS chips are all connected to the CPLD unit module; the BMC module is used to monitor the system status to determine whether the currently used BIOS chip is available; if so, notify the currently used BIOS chip to connect to the processor; if not, notify the CPLD unit module to switch the currently used BIOS chip.

[0006] In combination with the first aspect, an embodiment of the present invention also provides a first implementation of the first aspect, wherein the above-mentioned control system also includes a TCM module; the TCM module is connected to the CPLD unit module, and the TCM module is also connected to the processor for running an encryption function.

[0007] In combination with the first aspect, an embodiment of the present invention also provides a second implementation of the first aspect, wherein the above-mentioned CPLD unit module includes a first interconnection unit and a second interconnection unit, and the first interconnection unit is connected to the second interconnection unit; the TCM module is connected to the first interconnection unit; the processor, multiple BIOS chips and the BMC module are connected to the second interconnection unit.

[0008] In combination with the first aspect, an embodiment of the present invention also provides a third implementation method of the first aspect, wherein the above-mentioned BIOS chip includes a first BIOS chip and a second BIOS chip; the first BIOS chip is the BIOS chip currently used; the BMC module notifies the CPLD unit module to switch the currently used BIOS chip, including: the BMC module notifies the CPLD unit module to switch the current connection state, switching the first BIOS chip to the second BIOS chip, so that the second BIOS chip is interconnected with the processor.

[0009] In combination with the first aspect, an embodiment of the present invention also provides a fourth implementation of the first aspect, wherein the above-mentioned second interconnection unit includes a first port for connecting to the first BIOS chip, a second port for connecting to the second BIOS chip, a third port for connecting to the BMC module and a fourth port for connecting to the processor; a CPLD unit module is used to switch the connection status of the first port and the second port and the fourth port to switch the first BIOS chip and the second BIOS chip.

[0010] In combination with the first aspect, an embodiment of the present invention also provides a fifth implementation of the first aspect, wherein the above-mentioned BMC module monitors the system status to determine whether the currently used BIOS chip is available, comprising: the BMC module responds to the power-on signal and monitors whether a return signal from the first BIOS chip is received within a preset time range; if so, the first BIOS chip is indeed available; if not, it is determined that the first BIOS chip is not available.

[0011] In combination with the first aspect, an embodiment of the present invention also provides a sixth implementation of the first aspect, wherein the above-mentioned first port, second port, third port and fourth port are respectively connected to the first BIOS chip, the second BIOS chip, the BMC module and the processor through corresponding communication buses.

[0012] In combination with the first aspect, an embodiment of the present invention also provides a seventh implementation method of the first aspect, wherein the step of the above-mentioned TCM module running the encryption function includes: the TCM module responds to the encryption signal and sends an interrupt signal to the processor; the processor is used to respond to the interrupt signal, notify the CPLD unit module to disconnect the connection between the BIOS chip and the processor, and switch the connection between the TCM module and the processor.

[0013] In combination with the first aspect, an embodiment of the present invention also provides an eighth implementation of the first aspect, wherein the TCM module is connected to the first interconnection unit via a second communication bus.

[0014] In a second aspect, an embodiment of the present invention provides a server, wherein the server is configured with a control system according to any one of the above embodiments.

[0015] The embodiments of the present invention bring the following beneficial effects: The embodiments of the present invention provide a control system and a server, which use the CPLD unit module as the control center, introduce the characteristics of dynamic monitoring, automatic switching, efficient control center and system-level integrated management, and realize the enhancement of system functions and reliability without significantly increasing hardware costs through highly integrated CPLD and multi-BIOS architecture. Compared with the traditional approach of relying on external hardware or complex software solutions, the embodiments of the present invention are more economical and efficient. Moreover, the embodiments of the present invention realize remote real-time monitoring and maintenance of the BIOS layer through the intelligent monitoring of the BMC module and the automatic switching mechanism of CPLD control. The need for physical access to the server for local debugging is greatly reduced, the labor cost and time consumption are reduced, the processing speed is improved, and the response time of the motherboard failure is shortened. In addition, the embodiments of the present invention can autonomously identify and quickly respond to BIOS failures, reduce server downtime and the workload of maintenance personnel, and improve the overall operation and maintenance efficiency. Moreover, the highly redundant BIOS design of the embodiments of the present invention cooperates with the intelligent monitoring and management strategy, which fundamentally enhances the server's ability to resist single point failures, ensuring that even if problems occur at the BIOS level, they can be quickly recovered, which is crucial to improving the reliability and data security of the server.

[0016] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the structure of a control system provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of the structure of another control system provided by an embodiment of the present invention;

[0021] Figure 3A schematic diagram of a connection structure corresponding to a CPLD unit module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described in combination with the embodiments below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] The present invention provides a control system and a server with high integration and cost advantages, shortens the response time of mainboard failures, and improves the reliability and safety of the server.

[0024] To facilitate understanding of this embodiment, a control system disclosed in an embodiment of the present invention is first described in detail. Figure 1 The structural diagram of a control system shown in FIG. 1 is a control system provided by an embodiment of the present invention, comprising: a processor 200, a CPLD unit module 100, a BMC module 300, and multiple BIOS chips. Figure 1 In the embodiment, multiple BIOS chips are distinguished by 400a and 400b. The processor 200, the BMC module 300, and the multiple BIOS chips are all connected to the CPLD unit module 100. In a specific implementation, the BMC module 300 is used to monitor the system status to determine whether the currently used BIOS chip is available; if yes, the currently used BIOS chip is notified to connect to the processor 200; if not, the CPLD unit module 100 is notified to switch the currently used BIOS chip.

[0025] Specifically, the BMC (Baseboard Management Controller) is a baseboard management controller that can monitor the working status of each BIOS chip in real time and determine whether the currently activated BIOS chip is operating normally. If the current BIOS chip is operating normally, the BMC maintains its connection with the processor 200 (CPU) to ensure stable operation of the system. If it is detected that the current BIOS chip is unavailable, the BMC immediately notifies the CPLD unit module 100 to trigger the switching operation of the BIOS chip.

[0026] BIOS (Basic Input / Output System) is a firmware integrated on the computer motherboard, which is responsible for initializing and testing hardware components at startup and loading the operating system. CPLD (Complex Programmable Logic Device), in the embodiment of the present invention, a CPLD unit module 100 is used as the control center, which is a flexible switching intermediary and is responsible for efficient and accurate switching operations between BIOS chips. It not only enhances the flexibility of the system in handling faults, but also optimizes the switching speed and reduces the system interruption time. Specifically, after receiving the switching instruction from the BMC, the CPLD unit module 100 is responsible for reconfiguring the system connection. In the embodiment of the present invention, the connection with the faulty BIOS chip is disconnected, and another spare BIOS chip is activated to establish a connection with the processor 200, thereby achieving seamless switching and ensuring the continuity of system startup and operation.

[0027] In addition, the design of multiple BIOS chips in the embodiment of the present invention provides hardware-level redundancy. Each BIOS should have the same system boot and management functions to ensure that the system can still start and run normally when a single chip fails. Furthermore, the processor 200, CPLD, BMC and multiple BIOS chips in the embodiment of the present invention are tightly integrated and work together to achieve system robustness and fault switching functions. It is not limited to simple hardware redundancy, but also forms an ecosystem that can be intelligently managed and self-repaired, which can ensure the continuous operation of the system.

[0028] In summary, a control system provided by an embodiment of the present invention uses a CPLD unit module as a control center, introduces features such as dynamic monitoring, automatic switching, efficient control center, and system-level integrated management, and achieves enhanced system functionality and reliability without significantly increasing hardware costs through a highly integrated CPLD and multi-BIOS architecture. Compared with the traditional approach of relying on external hardware or complex software solutions, the embodiment of the present invention is more economical and efficient. Moreover, the embodiment of the present invention realizes remote real-time monitoring and maintenance of the BIOS layer through the intelligent monitoring of the BMC module and the automatic switching mechanism of CPLD control. This greatly reduces the need for physical access to the server for local debugging, reduces labor costs and time consumption, while increasing processing speed and reducing motherboard failure response time.

[0029] Furthermore, the automated fault detection and switching process of the embodiment of the present invention reduces the possibility of human intervention and reduces the security risks caused by operational errors. In addition, the system's real-time monitoring of the BIOS chip can promptly detect and respond to potential security threats, such as malware tampering with the BIOS, thereby improving the server's security protection level. In addition, the embodiment of the present invention can autonomously identify and quickly respond to BIOS failures, reducing server downtime and the workload of maintenance personnel, and improving overall operation and maintenance efficiency. Moreover, the highly redundant BIOS design of the embodiment of the present invention, combined with the intelligent monitoring and management strategy, fundamentally enhances the server's ability to resist single point failures, ensuring that even if problems occur at the BIOS level, they can be quickly recovered, which is crucial to improving server reliability and data security.

[0030] Furthermore, based on the above embodiment, the embodiment of the present invention also provides another control system: Figure 2 A structural schematic diagram of another control system provided by an embodiment of the present invention is shown. Among them, the processor of the embodiment of the present invention can be a domestic C86 architecture, which has the characteristics of flexible configuration, low power consumption, high storage access time efficiency, etc., and provides industry-leading computing performance, memory access bandwidth and IO expansion capabilities, and the chip supports SPI interface inside. The BIOS chip of the embodiment of the present invention can be interconnected with the CPU and BMC through the SPI channel through the CPLD unit module. Moreover, intelligent switching can be achieved through algorithms inside the CPLD to realize BIOS backup function and remote online update. The BMC chip can be interconnected with the BIOS chip through the CPLD unit module through the SPI channel, and can use a simple terminal program to input commands for remote debugging without CPU support.

[0031] In one embodiment, the CPLD unit module of the embodiment of the present invention adopts the Anlogic CPLDEF2L25BG256B chip, which performs level conversion on the one hand and flexibly processes signals on the other hand. It has the characteristics of instantaneous power-on, non-volatile storage, high I / O count, etc., and also integrates a user flash memory (UFM) block and an enhanced in-system programmability (ISP) device, which can effectively reduce cost and power. At the same time, it also provides programmable solutions for applications such as bus bridging, I / O expansion and sequencing control, and device configuration control.

[0032] Furthermore, the control system of the embodiment of the present invention also includes a TCM module (Trusted Computing Module), which refers to a trusted computing module. The TCM module is connected to the CPLD unit module, and the TCM module is also connected to the processor for running encryption functions. The TCM module focuses on running encryption algorithms and security-related tasks, providing a secure execution environment for storing encryption keys, certificates and other sensitive information. Protecting the confidentiality and integrity of data and instructions, and protecting these data from illegal access and tampering are crucial to improving the security level of the server.

[0033] In the embodiment of the present invention, by working in collaboration with the CPLD and the processor, the TCM can intervene quickly when a security incident is detected, isolate the affected parts, protect key system resources from being maliciously used, and ensure system continuity and stability. When the system is initialized, the BIOS firmware (such as BIOS flash) is first connected to the server, responsible for basic hardware configuration checks and booting and loading the operating system. When encryption-related operations need to be performed, the TCM module starts running its encryption function according to preset conditions or external triggers. Among them, the TCM module is used to respond to the encryption signal and send an interrupt signal to the processor in order to request the CPU to temporarily interrupt the current communication with the BIOS flash and prepare for security-related processing. The processor is used to respond to the interrupt signal and, in accordance with a predetermined security policy, notify the CPLD unit module to disconnect the connection between the BIOS chip and the processor, and instruct it to perform the next operation - switching the connection between the TCM module and the processor. After the encryption algorithm is run and processed, the CPLD is notified to restore the BIOS flash connection and continue to run.

[0034] In the specific implementation, the TCM module is interconnected with the CPLD unit module, and is interconnected with the CPU through the CPLD unit module through the SPI channel. It can also perform intelligent switching through the algorithm inside the CPLD to realize the trusted computing function.

[0035] In an embodiment of the present invention, the CPLD unit module includes a first interconnection unit and a second interconnection unit, and the first interconnection unit is connected to the second interconnection unit to form a flexible and efficient bridge. The TCM module is connected to the first interconnection unit, and the processor, multiple BIOS chips and the BMC module are connected to the second interconnection unit. The first interconnection unit enables the TCM module to quickly respond to security requirements, perform encryption operations or verification tasks, and intervene in the control path of the BIOS chip when necessary to ensure security during startup and operation; the second interconnection unit can not only ensure the highest level of instruction delivery and system control, but also enhance the robustness of the system based on multi-BIOS design; the access of the BMC module makes remote management and monitoring possible, further improving the maintainability and security of the system. Among them, the CPLD can generate an internal SPI switching switch through Verilog code, including a TCM switching module representing the first interconnection unit and a BIOS switching module representing the second interconnection unit. In specific implementation, the BIOS switching module of the embodiment of the present invention is based on two main logic unit modules of BIOS flash, CPU, BMC, and TCM. Its implementation logic is that the BIOS flash, CPU, BMC, and TCM are all connected to the CPLD through the SPI interface, so that the CPLD code must switch the SPI interconnection communication under different conditions through the logic algorithm in the same SPI module, and can achieve low-latency seamless and accurate switching of multiple SPI master-slave devices. The code algorithm involves signal synchronous sampling and signal competition risk arbitration judgment mechanism under multiple devices.

[0036] Figure 3 The schematic diagram of the connection structure corresponding to the CPLD unit module is shown in Figure 3 In the example, TCM_SWITCH is the first interconnection unit, and BIOS_SWITCH is the second interconnection unit, and the two are interconnected through SPI_3. The TCM module communicates via the second communication bus (such as Figure 3The BIOS chip includes a first BIOS chip (BIOS_1) and a second BIOS chip (BIOS_2); the first BIOS chip is the currently used BIOS chip; the second interconnection unit includes a first port for connecting to the first BIOS chip, a second port for connecting to the second BIOS chip, a third port for connecting to the BMC module, and a fourth port for connecting to the processor. The first port, the second port, the third port, and the fourth port are connected to the first BIOS chip, the second BIOS chip, the BMC module, and the processor through corresponding communication buses (such as SPI_1, SPI_2, SPI4, SPI_0, etc.). In addition, the BMC module is also connected to the second interconnection unit through GPIO; the CPU is also connected to the TCM module through GPIO. As a general input and output interface, GPIO provides the capability of simple and fast signal exchange.

[0037] Based on the above connection, the BMC module, by responding to the power-on signal, monitors whether the return signal of the first BIOS chip is received within the preset time range; if so, the first BIOS chip is indeed available; if not, it is determined that the first BIOS chip is unavailable. In the specific implementation, after the server is powered on, BIOS_1 (the first BIOS chip) is run first, and the BMC starts timing according to the power-on signal to wait for the GPIO to return the BIOS_CMPLT signal. If the power-on is normal, the signal will be pulled high and become 1, that is, the return signal is obtained, and the BMC notifies the CPLD to keep BIOS_1 connected to the CPU. If the BMC does not recognize that the BIOS_CMPLT signal is pulled high within the specified waiting time after powering on, the BMC notifies the CPLD to switch the SPI connection state and switch to BIOS2 to connect to the CPU.

[0038] Furthermore, the BMC module also switches the first BIOS chip to the second BIOS chip by notifying the CPLD unit module to switch the current connection state, so that the second BIOS chip is interconnected with the processor. Specifically, the CPLD unit module switches the connection state of the first port and the second port and the fourth port to switch the first BIOS chip and the second BIOS chip. Figure 3 When the BIOS_1 chip fails, the BMC chip determines whether the BIOS chip is invalid by monitoring the system status. If the system cannot be started, it will notify the CPLD to switch SPI to BIOS_2, and then start the system normally.

[0039] In summary, another control system provided by an embodiment of the present invention is to provide a design method based on a domestic Gemini server, which can realize the trusted computing function and the BIOS backup function on the server, and can also realize remote online BIOS update. This method is feasible, cost-effective, and highly integrated. It fully meets the specification requirements of the server. The embodiment of the present invention combines new features such as dynamic monitoring, automatic switching, efficient control center, and system-level integrated management with the CPLD unit module, solving the problems of time-consuming and labor-intensive local debugging of traditional servers and insufficient security. It shortens the response time of motherboard failures, reduces the maintenance workload of the server, and improves the reliability and safety of the server.

[0040] On the basis of the above embodiments, an embodiment of the present invention further provides a server, which is configured with a control system of any of the above embodiments. The server can use a domestically produced high-performance CPU to ensure data security while providing powerful computing power. Moreover, through a carefully designed CPLD integration method, the intelligent switching function on the SPI bus can be realized, which enhances the flexibility and security of the system in coping with different startup or operation requirements. Under the premise of ensuring performance, the entire server optimizes the cost and space in the selection and layout of hardware components, thereby improving the overall integration. Moreover, the embodiment of the present invention can also make full use of the system monitoring function of the BMC module, autonomously identify and quickly respond to BIOS failures, reduce server downtime and the workload of maintenance personnel, reduce physical access requirements, and make maintenance work more convenient.

[0041] Furthermore, a server provided in an embodiment of the present invention has the same implementation principle and technical effects as those in the aforementioned control system embodiment. For the sake of brief description, for matters not mentioned in the server embodiment, reference may be made to the corresponding contents in the aforementioned control system embodiment.

[0042] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances. If the function is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0043] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. Finally, it should be noted that the above embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions recorded in the above embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A control system, characterized in that: include: Processor, CPLD unit module, BMC module, multiple BIOS chips; Wherein, the processor, the BMC module, and the plurality of BIOS chips are all connected to the CPLD unit module; The BMC module is used to monitor the system status to determine whether the currently used BIOS chip is available; If yes, then notify the currently used BIOS chip to connect to the processor; If not, the CPLD unit module is notified to switch the currently used BIOS chip.

2. The control system according to claim 1, characterized in that: The control system also includes a TCM module; the TCM module is connected to the CPLD unit module, and the TCM module is also connected to the processor for running an encryption function.

3. The control system according to claim 2, characterized in that: The CPLD unit module includes a first interconnection unit and a second interconnection unit, and the first interconnection unit is connected to the second interconnection unit; The TCM module is connected to the first interconnection unit; The processor, the plurality of BIOS chips and the BMC module are connected to the second interconnection unit.

4. The control system according to claim 3, characterized in that: The BIOS chip includes a first BIOS chip and a second BIOS chip; the first BIOS chip is the BIOS chip currently used; The step of the BMC module notifying the CPLD unit module to switch the currently used BIOS chip includes: The BMC module notifies the CPLD unit module to switch the current connection state, and switches the first BIOS chip to the second BIOS chip, so that the second BIOS chip is interconnected with the processor.

5. The control system according to claim 4, characterized in that: The second interconnection unit includes a first port for connecting to the first BIOS chip, a second port for connecting to the second BIOS chip, a third port for connecting to the BMC module, and a fourth port for connecting to the processor; The CPLD unit module is used to switch the connection status between the first port and the second port and the fourth port, so as to switch the first BIOS chip and the second BIOS chip.

6. The control system according to claim 4, characterized in that: The step of the BMC module monitoring the system status to determine whether the currently used BIOS chip is available includes: The BMC module responds to the power-on signal and monitors whether a return signal from the first BIOS chip is received within a preset time range; If yes, the first BIOS chip is indeed available; If not, it is determined that the first BIOS chip is unavailable.

7. The control system according to claim 5, characterized in that: The first port, the second port, the third port and the fourth port are respectively connected to the first BIOS chip, the second BIOS chip, the BMC module and the processor through corresponding communication buses.

8. The control system according to claim 2, characterized in that: The steps of the TCM module running the encryption function include: The TCM module, in response to the encryption signal, sends an interrupt signal to the processor; The processor is used to respond to the interrupt signal, notify the CPLD unit module to disconnect the connection between the BIOS chip and the processor, and switch the connection between the TCM module and the processor.

9. The control system according to claim 3, characterized in that: The TCM module is connected to the first interconnection unit via a second communication bus.

10. A server, characterized in that: A control system according to any one of claims 1 to 9 is provided.

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