Universal input / output port circuit and circuit-based communication method
Connect multiple extenders through the IIC interface, and receive interrupt signals using registers and buffers, solving the problems of insufficient GPIO resources and leakage of processors, achieving more accurate response to GPIO level change and resource saving.
Patent Information
- Application Number
- CN202411131831.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2024-12-13
AI Technical Summary
The processor's GPIO resources are insufficient and there is a leakage problem in the direct-connected circuit, which causes the processor to work abnormally.
Multiple extenders are connected through the IIC interface, each extending multiple GPIOs, using registers and buffers to receive interrupt signals, and the processor reads interrupt signals from registers or buffers to accurately locate GPIO level changes to prevent leakage.
Save the processor's GPIO resources, prevent GPIO leakage, reduce the risk of processor damage, and improve the response speed to GPIO level changes.
Smart Images
Figure CN119127757A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of servers, and in particular to a universal input / output port circuit and a communication method, device, electronic equipment and storage medium based on the circuit. Background Art
[0002] Processors usually have many external interfaces, such as high-speed lines, IIC (Inter-Integrated Circuit) buses, serial ports, SPI (Serial Peripheral lnterface), and JTAG (Joint Test Action Group). In addition to interfaces with special functions, the most common one is GPIO (General Purpose Input Output). This type of pin is more flexible and can be configured as an input or output pin. Usually, if GPIO is configured as an input pin, the processor can use it to collect information from external devices, such as switch status, reset or interrupt information, etc. If GPIO is configured as an output pin, the processor can use it to control the operation of external devices, such as controlling LED (Light Emitting Diode) lights, resetting external devices, etc.
[0003] The circuit design of the common processor GPIO as input pin is as follows Figure 1 As shown in the figure, the GPIO of the external device is directly connected to the GPIO of the processor. This design is relatively simple and direct, but when more input pins are required, the GPIO resources of the processor may not be enough. In addition, this direct connection circuit has a leakage problem. If the power-on timing of some devices is earlier than that of the processor, the voltage will leak into the processor, which may cause the processor to work abnormally. Summary of the invention
[0004] In view of the above problems, embodiments of the present invention are proposed to provide a universal input / output port circuit and a circuit-based communication method, device, electronic device and storage medium that overcome the above problems or at least partially solve the above problems.
[0005] In a first aspect, an embodiment of the present invention discloses a universal input / output port circuit, which includes a processor, the processor includes a first interface and a second interface, the first interface is used to connect at least one expander, each expander includes at least one universal input / output port; the second interface is used to obtain interrupt signals of each of the expanders.
[0006] Optionally, the first interface is connected to each expander via a first data line and a first clock line.
[0007] Optionally, each expander is provided with an interrupt signal module, and when the level of any target general input / output port of any target expander in each expander changes, the interrupt signal module of the target expander outputs an interrupt signal;
[0008] Each universal input / output port in the target expander and the target expander have the same supply voltage;
[0009] The second interface is connected to a preset register via a second data line and a second clock line, and the second interface obtains an interrupt signal via the register;
[0010] The register is connected to each expander and is used to store the interrupt signal output by the interrupt signal module of each expander;
[0011] The second interface communicates with the register via a preset communication protocol, wherein the communication protocol is half-duplex communication;
[0012] The second interface comprises an interface simulated by two first general purpose input and output ports of the processor.
[0013] Optionally, the second interface further includes a second general input / output port, the second interface is connected to a preset buffer, and the second interface obtains interrupt signals of each of the expanders through the buffer.
[0014] Optionally, the buffer is connected to each expander, and the buffer is used to output an interrupt signal to the processor when an interrupt signal of any target expander among the expanders is obtained.
[0015] In a second aspect, an embodiment of the present invention discloses a communication method based on a universal input / output port circuit, characterized in that the universal input / output port circuit includes a processor, the processor includes a first interface and a second interface, the first interface is used to connect at least one expander, each expander includes at least one universal input / output port; the second interface is used to obtain an interrupt signal of each of the expanders; the method includes:
[0016] generating an interrupt signal when a level of any target general purpose input / output port of any target expander in the at least one expander changes;
[0017] The interrupt signal is output to the second interface.
[0018] Optionally, the second interface comprises an interface simulated by two general purpose input and output ports of the processor, and the processor is connected to a preset register;
[0019] The outputting the interrupt signal to the second interface comprises:
[0020] The interrupt signal is output to the register so that the processor obtains the interrupt signal from the register.
[0021] Optionally, the second interface further includes a second general input and output port, and the second interface is further connected to a preset buffer;
[0022] The outputting the interrupt signal to the second interface comprises:
[0023] The interrupt signal is output to the buffer so that the buffer obtains the interrupt signal from the register.
[0024] In a third aspect, an embodiment of the present invention discloses a communication device based on a universal input / output port circuit, characterized in that the universal input / output port circuit includes a processor, the processor includes a first interface and a second interface, the first interface is used to connect at least one expander, each expander includes at least one universal input / output port; the second interface is used to obtain an interrupt signal of each of the expanders; the device includes:
[0025] A generating module, configured to generate an interrupt signal when a level of any target general purpose input / output port of any target expander in the at least one expander changes;
[0026] An output module, used for outputting the interrupt signal to the second interface.
[0027] In a fourth aspect, the present invention further discloses an electronic device, comprising: a general purpose input / output port circuit including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the general purpose input / output port circuit is such as the circuit described above, and when the computer program is executed by the processor, the steps of the communication method based on the general purpose input / output port circuit are implemented as described above.
[0028] In a fifth aspect, the present invention further discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the communication method based on the general input and output port circuit as described above are implemented.
[0029] The embodiments of the present invention include the following advantages:
[0030] Connect to multiple expanders through the IIC interface, each expander can expand multiple GPIOs, so that the processor can expand multiple GPIOs through one IIC interface, which not only saves the processor's GPIO resources, but also prevents GPIO leakage if the processor does not perform a read operation even if the expander is powered on earlier than the processor, thereby solving the GPIO leakage problem and reducing the risk of processor damage. In order to further save the processor's GPIO resources, the expander's interrupt signal is connected to the register, and the processor reads the interrupt signal from the register, thereby more accurately locating the GPIO level change. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 It is a circuit design that uses the GPIO of a common processor as an input pin;
[0032] Figure 2 It is a general input and output port circuit design provided by an embodiment of the present invention;
[0033] Figure 3 It is another general input and output port circuit design provided by an embodiment of the present invention;
[0034] Figure 4 is a flow chart of the steps of a communication method based on a universal input / output port circuit provided by an embodiment of the present invention;
[0035] Figure 5 is a structural block diagram of an electronic device provided by an embodiment of the present invention;
[0036] Figure 6 It is a structural block diagram of a computer-readable storage medium provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0038] like Figure 2 , shows a general purpose input / output port circuit provided by an embodiment of the present invention, the general purpose input / output port circuit includes a processor, the processor includes a first interface and a second interface, the first interface is used to connect at least one expander, each expander includes at least one general purpose input / output port (in the figure, an expander includes 8 GPIOs as an example); the second interface is used to obtain interrupt signals of each expander. The expander can be an IO (Input / Output) expander.
[0039] It should be noted that, at the same time, the second interface may obtain one interrupt signal or may obtain multiple interrupt signals.
[0040] In one embodiment, the first interface is connected to each expander via a data line SDA (Serial Data) (referred to as “first data line” for easy distinction) and a clock line SCL (Serial Clock Line) (referred to as “first clock line”).
[0041] In one embodiment, each expander is provided with an interrupt signal module. When the level of any target general input / output port of any target expander in each expander changes, the interrupt signal module of the target expander generates and outputs an interrupt signal.
[0042] Furthermore, each general purpose input / output port in the target expander has the same power supply voltage as the target expander. For example, if the eight GPIOs in expander 1 are all connected to 3V3 powered devices, then expander 1 can also use 3V3 power supply voltage.
[0043] Furthermore, the second interface is connected to a preset register via a data line (referred to as a "second data line") and a clock line (referred to as a "second clock line"), the register is connected to each expander, the interrupt signal output by the interrupt signal module of each expander can be stored in the register, and the second interface obtains the interrupt signal via the register. The register can be a complex programmable logic device CPLD (Complex Programmable Logic Device).
[0044] Furthermore, the second interface communicates with the register via a preset communication protocol, and the communication protocol is half-duplex communication, such as the IIC communication protocol.
[0045] The first interface may be an IIC interface, and the second interface may be an IIC interface simulated by two general purpose input and output ports (referred to as “first general purpose input and output ports”) in the processor.
[0046] In the embodiment of the present invention, multiple expanders are connected through an IIC interface, and each expander can expand multiple GPIOs. In this way, the processor can expand multiple GPIOs through an IIC interface, which not only saves the GPIO resources of the processor, but also prevents GPIO leakage if the processor does not perform a read operation even if the expander is powered on earlier than the processor, thereby solving the GPIO leakage problem and reducing the risk of damage to the processor. In order to further save the GPIO resources of the processor, the interrupt signal of the expander is connected to the register, and the processor reads the interrupt signal from the register, thereby more accurately locating the GPIO level change.
[0047] like Figure 3, shows another general purpose input / output port circuit provided by an embodiment of the present invention, the general purpose input / output port circuit includes a processor, the processor includes a first interface and a second interface, the first interface is used to connect at least one expander, each expander includes at least one general purpose input / output port (in the figure, an expander includes 8 GPIOs as an example); the second interface is used to obtain interrupt signals of each expander. The expander may be an IO expander.
[0048] In one embodiment, the second interface may also be a general purpose input / output port of the processor (referred to as a "second general purpose input / output port"), the second interface is connected to a preset buffer, and the second interface obtains interrupt signals of each expander through the buffer. The preset buffer may be an OD buffer (buffer with open-drain output).
[0049] In one embodiment, the buffer is connected to each expander, and when the buffer obtains an interrupt signal from any target expander among the expanders, the buffer outputs an interrupt signal to the processor.
[0050] In the embodiment of the present invention, the IIC interface is connected to multiple expanders, and each expander can expand multiple GPIOs. In this way, the processor can expand multiple GPIOs through one IIC interface, which not only saves the GPIO resources of the processor, but also prevents GPIO leakage if the processor has no read operation even if the expander is powered on earlier than the processor, thereby solving the GPIO leakage problem and reducing the risk of damage to the processor. Furthermore, the interrupt signal of each expander is output to the processor through the buffer, so that the processor can respond to GPIO level changes more quickly.
[0051] like Figure 4 , shows a flow chart of the steps of a communication method based on a universal input / output port circuit provided by an embodiment of the present invention, wherein the universal input / output port circuit is as follows Figure 2 or Figure 3 As shown, the method may include the following steps:
[0052] Step 201 : When the level of any target general purpose input / output port of any target expander in the at least one expander changes, an interrupt signal is generated.
[0053] For any expander in each expander (referred to as "target expander"), when the level of any general input / output port in the target expander (referred to as "target general input / output port") changes, the interrupt signal module in the target expander can generate an interrupt signal.
[0054] Step 202: output the interrupt signal to the second interface.
[0055] After generating the interrupt signal, the target expander may output the interrupt signal to the second interface, so that the processor obtains the interrupt signal through the second interface.
[0056] In one embodiment, the second interface comprises an interface simulated by two general purpose input and output ports of the processor, and the processor is connected to a preset register;
[0057] The outputting the interrupt signal to the second interface comprises:
[0058] The interrupt signal is output to the register so that the processor obtains the interrupt signal from the register.
[0059] Specifically, the second interface can be an IIC interface simulated by two GPIOs in the processor, and a preset register can be connected between the second interface and each expander, so that after the target expander generates an interrupt signal, it can output the interrupt signal to the register, and the processor obtains the interrupt signal from the register through the second interface. In this way, the interrupt signal of the expander is connected to the register, and the processor reads the interrupt signal from the register, which not only further saves the GPIO resources of the processor, but also more accurately locates the GPIO level change.
[0060] In one embodiment, the second interface further includes a second general purpose input and output port, and the second interface is further connected to a preset buffer;
[0061] The outputting the interrupt signal to the second interface comprises:
[0062] The interrupt signal is output to the buffer so that the buffer obtains the interrupt signal from the register.
[0063] Specifically, the second interface may also be a GPIO of the processor, and a preset buffer may be connected between the second interface and each expander, so that after the target expander generates an interrupt signal, the interrupt signal may be output to the buffer, and the processor obtains the interrupt signal from the buffer through the second interface. In this way, the interrupt signal of each expander is output to the processor through the buffer, so that the processor can respond to the GPIO level change more quickly.
[0064] In an embodiment of the present invention, a general purpose input / output port circuit includes a processor, and the processor includes a first interface and a second interface, wherein the first interface is used to connect at least one expander, and each expander includes at least one general purpose input / output port; and the second interface is used to obtain interrupt signals of each of the expanders. When the level of any target general purpose input / output port of any target expander in at least one expander changes, an interrupt signal is generated; and the interrupt signal is output to the second interface. In this way, the processor can expand multiple GPIOs through an IIC interface, which not only saves the GPIO resources of the processor, but also, even if the expander is powered on earlier than the processor, if the processor has no read operation, it can prevent GPIO leakage, thereby solving the GPIO leakage problem and reducing the risk of damage to the processor.
[0065] The present invention also provides a communication device based on a universal input / output port circuit, wherein the universal input / output port circuit comprises a processor, wherein the processor comprises a first interface and a second interface, wherein the first interface is used to connect at least one expander, each expander comprising at least one universal input / output port; and the second interface is used to obtain an interrupt signal of each expander; and the device comprises:
[0066] A generating module, configured to generate an interrupt signal when a level of any target general purpose input / output port of any target expander in the at least one expander changes;
[0067] An output module, used for outputting the interrupt signal to the second interface.
[0068] In one embodiment, the second interface comprises an interface simulated by two general purpose input and output ports of the processor, and the processor is connected to a preset register;
[0069] The output module is specifically used for:
[0070] The interrupt signal is output to the register so that the processor obtains the interrupt signal from the register.
[0071] In one embodiment, the second interface further includes a second general purpose input and output port, and the second interface is further connected to a preset buffer;
[0072] The output module is further specifically used for:
[0073] The interrupt signal is output to the buffer so that the buffer obtains the interrupt signal from the register.
[0074] like Figure 5 , showing a structural block diagram of an electronic device 50 provided in an embodiment of the present invention, including:
[0075] The present invention comprises a general purpose input / output port circuit 302 of a processor 301, a memory 303, and a computer program 3031 stored in the memory 303 and capable of running on the processor 301. The general purpose input / output port circuit 302 is such as the circuit described above. When the computer program 3031 is executed by the processor 301, the various processes of the embodiment of the communication method based on the general purpose input / output port circuit are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.
[0076] like Figure 6 , shows a structural block diagram of a computer-readable storage medium 60 provided in an embodiment of the present invention. A computer program 601 is stored on the computer-readable storage medium 60. When the computer program 601 is executed by the processor, the various processes of the above-mentioned communication method embodiment based on the general input and output port circuit are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0077] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0078] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
[0079] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0080] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0082] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0083] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.
[0084] The above is a detailed introduction to a universal input / output port circuit and a communication method, device, electronic device and storage medium based on the circuit provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A general input / output port circuit, characterized in that: The universal input / output port circuit includes a processor, the processor includes a first interface and a second interface, the first interface is used to connect at least one expander, each expander includes at least one universal input / output port; the second interface is used to obtain interrupt signals of each expander.
2. The universal input / output port circuit according to claim 1, characterized in that: The first interface is connected to each expander via a first data line and a first clock line.
3. The universal input / output port circuit according to claim 1, characterized in that: Each expander is provided with an interrupt signal module, and when the level of any target general input / output port of any target expander in each expander changes, the interrupt signal module of the target expander outputs an interrupt signal; Each universal input / output port in the target expander and the target expander have the same supply voltage; The second interface is connected to a preset register via a second data line and a second clock line, and the second interface obtains an interrupt signal via the register; The register is connected to each expander and is used to store the interrupt signal output by the interrupt signal module of each expander; The second interface communicates with the register via a preset communication protocol, wherein the communication protocol is half-duplex communication; The second interface comprises an interface simulated by two first general purpose input and output ports of the processor.
4. The universal input / output port circuit according to claim 1, characterized in that: The second interface also includes a second general input and output port, and the second interface is connected to a preset buffer. The second interface obtains the interrupt signal of each expander through the buffer.
5. The universal input / output port circuit according to claim 4, characterized in that: The buffer is connected to each expander, and is used to output an interrupt signal to the processor when an interrupt signal of any target expander among the expanders is obtained.
6. A communication method based on a universal input / output port circuit, characterized in that: The universal input-output port circuit includes a processor, the processor includes a first interface and a second interface, the first interface is used to connect at least one expander, each expander includes at least one universal input-output port; The second interface is used to obtain the interrupt signal of each of the expanders; the method includes: generating an interrupt signal when a level of any target general purpose input / output port of any target expander in the at least one expander changes; The interrupt signal is output to the second interface.
7. The communication method based on the universal input and output port circuit according to claim 6, characterized in that: The second interface comprises an interface simulated by two general purpose input and output ports of the processor, and the processor is connected to a preset register; The outputting the interrupt signal to the second interface comprises: The interrupt signal is output to the register so that the processor obtains the interrupt signal from the register.
8. The communication method based on the universal input and output port circuit according to claim 6, characterized in that: The second interface also includes a second general purpose input and output port, and the second interface is also connected to a preset buffer; The outputting the interrupt signal to the second interface comprises: The interrupt signal is output to the buffer so that the buffer obtains the interrupt signal from the register.
9. A communication device based on a universal input / output port circuit, characterized in that: The universal input-output port circuit includes a processor, the processor includes a first interface and a second interface, the first interface is used to connect at least one expander, each expander includes at least one universal input-output port; The second interface is used to obtain the interrupt signal of each of the expanders; the device includes: A generating module, configured to generate an interrupt signal when a level of any target general purpose input / output port of any target expander in the at least one expander changes; An output module, used for outputting the interrupt signal to the second interface.
10. An electronic device, characterized in that: include: A general purpose input / output port circuit comprising a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the general purpose input / output port circuit is a circuit as described in any one of claims 1 to 5, and when the computer program is executed by the processor, the steps of a communication method based on a general purpose input / output port circuit are implemented as described in any one of claims 6 to 8.
11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the communication method based on a general purpose input / output port circuit as described in any one of claims 6 to 8 are implemented.