Design and simulation method of two-dimensional semiconductor nanometer transistor

Abstract

The invention discloses a design and simulation method of a two-dimensional semiconductor nanometer transistor, and belongs to the technical field of design and application of two-dimensional materials, and the method comprises the following steps: S1, material selection; s2, surface treatment; s3, metal contact design; s4, optimizing the structure of the device; s5, simulation tools and methods; by optimizing a metal-semiconductor interface, the contact resistance is reduced; by adopting a novel interface engineering strategy, controllable energy band alignment is realized; a simplified manufacturing process is provided, and the cost is reduced; the electrical properties of the device, such as on-state current and on-off ratio, are improved; the contact resistance is reduced, and the carrier mobility is improved; the invention provides a low-cost and high-efficiency manufacturing process.

Description

Technical Field

[0001] The present invention relates to the technical field of design and application of two-dimensional materials, and in particular to a design and simulation method of a two-dimensional semiconductor nano transistor. Background Art

[0002] In the current field of semiconductor technology, as Moore's Law gradually approaches its physical limits, two-dimensional (2D) semiconductor materials are regarded as key materials for continuing Moore's Law and promoting the development of electronic devices in the post-Moore era due to their unique physical properties and ultra-thin characteristics. Although two-dimensional semiconductors exhibit high mobility, easy electrostatic control, and potential ultra-low power consumption, there are still many challenges in achieving the integration and application of high-performance transistors, especially in terms of metal-semiconductor contact resistance, band engineering, ohmic contact formation, and the manufacturing process of extremely small-sized devices.

[0003] It has been found that the Fermi level pinning effect (FLP) of metal-semiconductor contacts severely limits device performance, which is caused by factors such as metal-induced gap states (MIGS), interface defects, and local strain. Therefore, exploring new material systems and innovative interface engineering strategies to achieve ultra-low contact resistance and controllable band alignment has become the key to breaking through the performance bottleneck of two-dimensional semiconductor devices.

[0004] Recently, research teams at home and abroad have made significant progress in two-dimensional semiconductor integration and contact engineering. For example, the team of Professor Zhang Wenjing of Shenzhen University proposed the graphene-enhanced van der Waals contact technology, which effectively solved the Schottky barrier problem in the contact between three-dimensional metals and two-dimensional semiconductors, and significantly improved the electrical performance of the device. The team of Academician Peng Lianmou of Tsinghua University achieved p-type doping of two-dimensional semiconductors through yttrium doping, providing a feasible strategy for vertical three-dimensional integrated circuits. Researcher Li Xiuyan of the Institute of Metal Research, Chinese Academy of Sciences and others have jointly developed a simple and stable p-type doping strategy to achieve the integration of complementary logic devices of two-dimensional semiconductors. In addition, the research team of the Institute of Basic Science (IBS) in South Korea has made a breakthrough in demonstrating transistor technology less than 1 nanometer, using one-dimensional metal materials as gate electrodes, opening up a new path for the manufacture of ultra-miniaturized transistors.

[0005] These studies not only demonstrate innovative solutions for realizing high-performance transistors in two-dimensional semiconductors, but also demonstrate that through precise material design, interface engineering and new contact technology, the limitations of traditional processes have been overcome, promoting the transformation of two-dimensional electronics from laboratory to industrial applications. However, how to precisely control the band structure of materials at the atomic scale, achieve more efficient charge transport, and develop integrated technologies compatible with large-scale production are still core issues in current research.

[0006] Therefore, this invention intends to design and simulate two-dimensional semiconductor nano-transistors, using first-principles calculation and simulation technology to deeply explore the electronic structure, energy band arrangement and carrier transport characteristics of materials, aiming to develop new two-dimensional semiconductor material systems, optimize device structure design, and explore new interface engineering strategies, so as to provide theoretical support and technical reserves for the realization of low-power, high-integration next-generation electronic devices. The project will focus on solving key technical problems such as high contact resistance, difficult energy level matching, and interface quality control, aiming to promote the overall improvement of the performance of two-dimensional semiconductor devices and meet the future information technology demand for high-performance, low-energy devices. Summary of the invention

[0007] The present invention aims to provide a design and simulation method of a two-dimensional semiconductor nano-transistor to solve the problems raised in the above-mentioned background technology.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] A design and simulation method for a two-dimensional semiconductor nanotransistor comprises the following steps:

[0010] S1: Material selection, selecting two-dimensional semiconductor materials suitable for high-performance nanotransistors;

[0011] S2: Surface treatment: Surface treatment of two-dimensional materials to ensure the surface is clean and reduce defects, thereby improving the electrical properties of the materials;

[0012] S3: Metal contact design, designing the contact mode between metal electrodes and two-dimensional semiconductors, and reducing contact resistance by selecting appropriate metal materials and optimizing the contact interface;

[0013] S4: Device structure optimization: Optimize the device structure of nano transistors to improve the on-state current, on / off ratio and subthreshold swing of the device;

[0014] S5: Simulation tools and methods, using high-precision first-principles calculations and quantum transport simulation technology, simulate carrier transport characteristics through reasonable initial condition settings, self-consistent calculations and non-equilibrium Green's function methods, and accurately analyze the results to guide device design and optimization.

[0015] Preferably, the step S1 specifically includes the following steps:

[0016] S101: Consider high mobility, good electrical properties and mechanical flexibility;

[0017] S102: Choose MoS 2 ,WSe 2 As a two-dimensional semiconductor material.

[0018] Preferably, the step S1 specifically includes the following steps:

[0019] The step S2 specifically includes the following steps:

[0020] S201: Perform chemical cleaning or plasma treatment;

[0021] S202: Ensure surface cleanliness and reduce defects.

[0022] Preferably, the step S1 specifically includes the following steps:

[0023] The step S3 specifically comprises the following steps:

[0024] S301: Determine suitable metal materials, including gold or molybdenum;

[0025] S302: Use technologies such as graphene insertion layer to optimize the contact interface and reduce contact resistance.

[0026] Preferably, the step S1 specifically includes the following steps:

[0027] The step S4 specifically comprises the following steps:

[0028] S401: Optimizing parameters including gate length, gate dielectric thickness, and channel length.

[0029] Preferably, the step S1 specifically includes the following steps:

[0030] The step S5 specifically comprises the following steps:

[0031] S501: Simulation tool selection, using high-precision first-principles calculations and quantum transport simulation technology;

[0032] S502: Initial condition setting: setting the initial conditions of the simulation according to the structure and material parameters of the designed two-dimensional semiconductor nanotransistor, including the electronic structure and boundary conditions of the material;

[0033] S503: Simulation process, the ground state electronic structure of the system is obtained through self-consistent calculation, and the carrier transport characteristics are simulated using the non-equilibrium Green's function method;

[0034] S504: Result analysis: Analyze the simulation results, including the band structure, carrier mobility and contact resistance, and compare the performance of different design schemes.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] Reduce contact resistance: By adopting innovative metal contact designs, such as graphene insertion layer technology, the contact resistance of the metal-semiconductor interface is effectively reduced, which has obvious advantages in improving device performance compared to existing technologies.

[0037] Achieving controllable energy band alignment: Utilizing a novel interface engineering strategy, the present invention can more accurately achieve controllable energy band alignment of two-dimensional materials, solving the problem of energy band engineering difficulties in the prior art, thereby improving the performance and functionality of the device.

[0038] Simplify the manufacturing process and reduce costs: The optimized device structure design and manufacturing process make the present invention simpler and more efficient in the production process, reduce the production cost, and have significant improvement compared with the existing complex and costly manufacturing process.

[0039] Improve the electrical performance of the device: Through improvements in material selection, surface treatment, metal contact design and device structure optimization, the present invention significantly improves the electrical performance of the device, such as on-state current and switching ratio, providing strong support for the development of high-performance electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of atomic arrangement for a simulation method of a two-dimensional semiconductor nanotransistor;

[0041] Figure 2 A schematic diagram of carrier transport simulation for a simulation method of a two-dimensional semiconductor nanotransistor;

[0042] Figure 3 The figure is a flow chart of a design and simulation method of a two-dimensional semiconductor nanotransistor. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments:

[0044] The specific implementation process is as follows:

[0045] A method for designing a two-dimensional semiconductor nanotransistor comprises the following steps:

[0046] a. Select two-dimensional semiconductor materials suitable for nanotransistors;

[0047] b. Perform surface treatment on the materials to ensure the surface is clean;

[0048] c. designing a contact mode between the metal electrode and the two-dimensional semiconductor material to reduce the contact resistance;

[0049] d. Optimize the device structure of nanotransistors, including gate length, gate dielectric thickness and channel length.

[0050] Material selection: Select two-dimensional semiconductor materials suitable for high-performance nanotransistors, such as MoS2, WSe2, etc. These materials have high mobility, good electrical properties and mechanical flexibility.

[0051] Surface treatment: Surface treatment of 2D materials is performed to ensure a clean surface and reduce defects, thereby improving the electrical properties of the material.

[0052] Metal contact design: Design the contact mode between metal electrodes and two-dimensional semiconductors, and reduce contact resistance by selecting appropriate metal materials (such as gold, molybdenum, etc.) and optimizing the contact interface. Innovative technologies such as graphene insertion layers can be used to reduce the Schottky barrier.

[0053] Device optimization and performance control: Optimize the device structure of nano-transistors, including parameters such as gate length, gate dielectric thickness, and channel length, to increase the device's on-state current, switching ratio, and subthreshold swing.

[0054] A simulation method for a two-dimensional semiconductor nanotransistor comprises the following steps:

[0055] a. Select high-precision simulation tools, including first-principles calculations and quantum transport simulation technology;

[0056] b. Set the initial conditions for the simulation, including the electronic structure of the material and boundary conditions;

[0057] c. Obtain the ground-state electronic structure of the system through self-consistent calculation and simulate the carrier transport characteristics;

[0058] d. Analyze the simulation results, including band structure, carrier mobility and contact resistance.

[0059] Step a: Simulation tool selection: Select the DFT software packages QuantumATK and VASP.

[0060] Step b: Initial condition setting (such as Figure 1 As shown in Figure 3), the unit cell parameters of MoS2 and the work function of the metal electrode are set, and the atomic arrangement at the interface is defined.

[0061] Step c: Simulation process (such as Figure 2 ): Run a DFT calculation, obtain the electronic structure data, and then input it into the calculation for carrier transport simulation.

[0062] Step d: Result analysis: By comparing the simulation results with and without graphene intercalation, the effectiveness of the graphene / MoS2 heterojunction in reducing contact resistance and improving device performance is verified.

[0063] The above is only an embodiment of the present invention, and the common knowledge such as the known specific technical solutions and / or characteristics in the solution is not described in detail here. It should be pointed out that for those skilled in the art, without departing from the technical solution of the present invention, several modifications and improvements can be made, which should also be regarded as the protection scope of the present invention, and these will not affect the effect of the implementation of the present invention and the practicality of the patent. The scope of protection required by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to interpret the content of the claims.

Claims

1. A design and simulation method for a two-dimensional semiconductor nanotransistor, characterized in that: The following steps are involved: S1: Material selection, selecting two-dimensional semiconductor materials suitable for high-performance nanotransistors; S2: Surface treatment: Surface treatment of two-dimensional materials to ensure the surface is clean and reduce defects, thereby improving the electrical properties of the materials; S3: Metal contact design, designing the contact mode between metal electrodes and two-dimensional semiconductors, and reducing contact resistance by selecting appropriate metal materials and optimizing the contact interface; S4: Device structure optimization: Optimize the device structure of nano transistors to improve the on-state current, on / off ratio and subthreshold swing of the device; S5: Simulation tools and methods, using high-precision first-principles calculations and quantum transport simulation technology, simulate carrier transport characteristics through reasonable initial condition settings, self-consistent calculations and non-equilibrium Green's function methods, and accurately analyze the results to guide device design and optimization.

2. The design and simulation method of a two-dimensional semiconductor nanotransistor according to claim 1, characterized in that: The step S1 specifically includes the following steps: S101: Consider high mobility, good electrical properties and mechanical flexibility; S102: Select MoS2 and WSe2 as two-dimensional semiconductor materials.

3. The design and simulation method of a two-dimensional semiconductor nano-transistor according to claim 1, characterized in that: The step S2 specifically includes the following steps: S201: Perform chemical cleaning or plasma treatment; S202: Ensure surface cleanliness and reduce defects.

4. The design and simulation method of a two-dimensional semiconductor nano-transistor according to claim 1, characterized in that: The step S3 specifically comprises the following steps: S301: Determine suitable metal materials, including gold or molybdenum; S302: Use technologies such as graphene insertion layer to optimize the contact interface and reduce contact resistance.

5. The design and simulation method of a two-dimensional semiconductor nano-transistor according to claim 1, characterized in that: The step S4 specifically comprises the following steps: S401: Optimizing parameters including gate length, gate dielectric thickness, and channel length.

6. The design and simulation method of a two-dimensional semiconductor nano-transistor according to claim 1, characterized in that: The step S5 specifically comprises the following steps: S501: Simulation tool selection, using high-precision first-principles calculations and quantum transport simulation technology; S502: Initial condition setting: setting the initial conditions of the simulation according to the structure and material parameters of the designed two-dimensional semiconductor nanotransistor, including the electronic structure and boundary conditions of the material; S503: Simulation process, the ground state electronic structure of the system is obtained through self-consistent calculation, and the carrier transport characteristics are simulated using the non-equilibrium Green's function method; S504: Result analysis: Analyze the simulation results, including the band structure, carrier mobility and contact resistance, and compare the performance of different design schemes.

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