Method, device, equipment, medium and program product for determining sampling circuit layout

Abstract

The present application provides a method, device, equipment, medium and program product for determining a sampling circuit layout. The method includes: creating an initial reference capacitor unit; verifying the initial reference capacitor unit to obtain a verification result, determining a capacitance adjustment amount corresponding to the verification result, and adjusting the initial reference capacitor unit using the capacitance adjustment amount to obtain a target capacitor unit; arranging at least one target capacitor unit to obtain an initial sampling circuit layout; performing an error analysis on the initial sampling circuit layout, and adjusting the arrangement of the initial sampling circuit layout according to the error analysis result to obtain a target sampling circuit layout. In this way, the initial reference capacitor unit can be automatically adjusted to obtain a target capacitor unit, and the arranged initial sampling circuit layout can be automatically adjusted to obtain a target sampling circuit layout, thereby obtaining the target capacitor unit and the target sampling circuit layout more quickly and accurately, effectively avoiding errors caused by human involvement.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a method, device, equipment, medium and program product for determining a sampling circuit layout. Background Art

[0002] With the rapid development of science and technology, the application of sampling circuits is becoming more and more extensive. The sampling circuit is a circuit composed of at least one capacitor connected to a corresponding switch. Specifically, the switch can be turned on to charge the capacitor to input voltage, and then the switch is turned off to allow the capacitor to maintain the corresponding input voltage.

[0003] Currently, sampling circuits require repeated manual adjustments to the layout in order to be obtained. The corresponding manual adjustment process consumes a long time and has a relatively high labor cost. Summary of the invention

[0004] In view of this, the purpose of this application is to propose a method, device, equipment, medium and program product for determining a sampling circuit layout, so as to solve or partially solve the above technical problems.

[0005] Based on the above purpose, the present application provides a method for determining a sampling circuit layout, comprising:

[0006] Create an initial reference capacitor unit;

[0007] Verifying the initial reference capacitor unit to obtain a verification result, determining a capacitance adjustment amount corresponding to the verification result, and adjusting the initial reference capacitor unit using the capacitance adjustment amount to obtain a target capacitor unit;

[0008] Arrange at least one target capacitor unit to obtain an initial sampling circuit layout;

[0009] An error analysis is performed on the initial sampling circuit layout, and the arrangement of the initial sampling circuit layout is adjusted according to the error analysis result to obtain a target sampling circuit layout.

[0010] Based on the same inventive concept, the present disclosure also provides a device for determining a sampling circuit layout, comprising:

[0011] A reference capacitor creation module, configured to create an initial reference capacitor unit;

[0012] a reference capacitance adjustment module configured to verify the initial reference capacitance unit to obtain a verification result, determine a capacitance adjustment amount corresponding to the verification result, and adjust the initial reference capacitance unit using the capacitance adjustment amount to obtain a target capacitance unit;

[0013] A sampling capacitor arrangement module is configured to arrange at least one target capacitor unit to obtain an initial sampling circuit layout;

[0014] The sampling capacitor adjustment module is configured to perform an error analysis on the initial sampling circuit layout, and adjust the arrangement of the initial sampling circuit layout according to the error analysis result to obtain a target sampling circuit layout.

[0015] Based on the same inventive concept, the present disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method as described above when executing the computer program.

[0016] Based on the same inventive concept, the present disclosure also provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute the method as described above.

[0017] Based on the same inventive concept, the present application also provides a computer program product, including computer program instructions, which enable the computer to execute the above-mentioned method when the computer program instructions are executed on a computer.

[0018] From the above, it can be seen that the method, device, equipment, medium and program product for determining the sampling circuit layout provided by the present application, after creating the initial reference capacitor unit, will verify the initial reference capacitor unit, and automatically adjust the initial reference capacitor unit according to the capacitance adjustment amount corresponding to the verification result, so as to obtain a more accurate target capacitor unit; and after arranging at least one target capacitor unit to obtain the initial sampling circuit layout, in order to ensure the accuracy of the initial sampling circuit layout, an error analysis will be performed on it, and the arrangement of the initial sampling circuit layout will be automatically adjusted according to the error analysis results, so as to obtain an accurate target sampling circuit layout more quickly; in this way, the workload of sampling circuit layout can be reduced to one ten-thousandth of the original workload, which greatly improves the layout efficiency, reduces labor costs, and effectively reduces errors in human operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A flowchart of a method for determining a sampling circuit layout according to an embodiment of the present application;

[0021] Figure 2A structural block diagram of a device for determining a sampling circuit layout according to an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0024] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] The design process of the sampling circuit in the related art is:

[0026] (1) Engineers design a custom capacitor layout based on experience, extract the parasitic capacitance value of the custom capacitor through the parasitic extraction program qrc, and check the parasitic capacitance value by back-marking on the circuit diagram of the custom capacitor. Then, engineers adjust the custom capacitor layout and repeat the process until the parasitic capacitance value of the custom capacitor layout reaches the design target.

[0027] (2) Engineers generate a custom capacitor module based on the layout of the custom capacitor and call it proportionally in the sampling circuit according to the design requirements.

[0028] (3) Engineers, in the layout design of the sampling circuit, call the customized capacitor module of the customized capacitor according to the proportion, and arrange it in a dispersed and cross-wise manner according to certain matching rules. Place the floating and unconnected customized capacitors in the empty positions.

[0029] (4) Connect the upper and lower plates of the capacitor according to the circuit connection relationship, verify the circuit connection relationship through the circuit connection relationship verification program lvs, and then use the parasitic extraction program to extract the parasitics. Use the parasitic capacitance value extracted by circuit back-labeling to check whether the ratio between the capacitance values ​​is correct and whether the capacitance error is within the index requirements.

[0030] (5) If the requirements are not met, adjust the sampling circuit and repeat the operation of (4) to prevent the requirements from being met.

[0031] However, the above description of related technologies has the following disadvantages:

[0032] (1) Manual adjustment is usually difficult to achieve the required result in one go and requires repeated adjustments and repeated parasitic extraction and circuit back-labeling processes, which is time-consuming and labor-intensive.

[0033] (2) Due to human involvement, the layout design rules are not unified. Different engineers, due to different experiences, will trigger various problems during layout design. For example, the capacitance ratio of the lower plate to the upper plate of the capacitor is incorrect, the parasitic resistance of the upper plate to the ground is too large, etc. These problems also need to be repeatedly determined and solved, wasting a lot of time and making it inconvenient to use.

[0034] Based on the above description, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0035] The method for determining the sampling circuit layout proposed in the embodiment of the present application is as follows: Figure 1 As shown, including:

[0036] Step 101: Create an initial reference capacitor unit.

[0037] In specific implementation, after setting the parameters required to create the initial reference capacitor unit, the corresponding initial reference capacitor unit will be generated. The parameters of the initial reference capacitor unit can also be adjusted.

[0038] Step 102 , verifying the initial reference capacitor unit to obtain a verification result, determining a capacitance adjustment amount corresponding to the verification result, and adjusting the initial reference capacitor unit using the capacitance adjustment amount to obtain a target capacitor unit.

[0039] In specific implementation, the initial reference capacitor unit created is not necessarily a capacitor unit that can be arranged for the sampling circuit. It is necessary to verify the layout of the initial reference capacitor unit. If the verification fails, the corresponding capacitor adjustment amount will be automatically determined, and then the initial reference capacitor unit will be automatically adjusted according to the capacitor adjustment amount. This adjustment process does not require human participation and can be completed automatically, which can effectively avoid errors caused by human participation, and the automatic adjustment process is relatively fast, which can effectively save time.

[0040] Step 103: Arrange at least one target capacitor unit to obtain an initial sampling circuit layout.

[0041] In a specific implementation, the required arrangement parameters (e.g., ratio data) corresponding to the input arrangement can be automatically retrieved for copying and arranging the required target capacitor units to form an initial sampling circuit layout. The number of target capacitor units in each initial sampling circuit layout is determined based on the input arrangement parameters.

[0042] Step 104 , performing an error analysis on the initial sampling circuit layout, and adjusting the arrangement of the initial sampling circuit layout according to the error analysis result to obtain a target sampling circuit layout.

[0043] During specific implementation, the created initial sampling circuit layout may have layout errors, so it is necessary to perform an error analysis on the layout situation in the initial sampling circuit layout and the layout requirements corresponding to the input arrangement parameters. The corresponding error analysis results include compliance with the layout requirements or non-compliance with the layout requirements.

[0044] If the layout requirements are not met, the corresponding layout adjustment amount will be automatically determined based on the error analysis results, and then the initial sample circuit layout will be automatically adjusted based on the layout adjustment amount. This adjustment process does not require human intervention and can be completed automatically, effectively avoiding errors caused by human intervention. The automatic adjustment process is relatively fast, which can effectively save time.

[0045] Through the above scheme, after the initial reference capacitor unit is created, the initial reference capacitor unit will be verified, and the initial reference capacitor unit will be automatically adjusted according to the capacitance adjustment amount corresponding to the verification result, so as to obtain a more accurate target capacitor unit; and after at least one target capacitor unit is arranged to obtain an initial sampling circuit layout, in order to ensure the accuracy of the initial sampling circuit layout, an error analysis will be performed on it, and the arrangement of the initial sampling circuit layout will be automatically adjusted according to the error analysis result, so as to obtain an accurate target sampling circuit layout more quickly; in this way, the workload of sampling circuit layout can be reduced to one ten-thousandth of the original workload, which greatly improves the layout efficiency, reduces labor costs, and effectively reduces errors in human operations.

[0046] In some embodiments, step 101 includes:

[0047] Step 1011, setting the capacitor unit shape of the first electrode plate surrounding the second electrode plate, and / or capacitor size parameters, and / or the plate layer where the capacitor is located.

[0048] Step 1012: Form the initial reference capacitor unit according to at least one of the capacitor unit shape, the capacitor size parameter, and the capacitor layer.

[0049] In a specific implementation, the first electrode plate is an upper electrode plate, and the second electrode plate is a lower electrode plate; or, the first electrode plate is a lower electrode plate, and the second electrode plate is an upper electrode plate.

[0050] The capacitor size parameters include at least one of the following: capacitor length, capacitor width, line width, and line spacing.

[0051] The capacitor layer is the corresponding layer on the circuit board where the initial reference capacitor unit is located, and the layers are arranged in sequence with the layer where the substrate is located as the first layer. For example, the initial reference capacitor unit is set to be located in the M1 to M2 layers.

[0052] After setting, the corresponding initial reference capacitor unit will be generated. The generated initial reference capacitor unit can be displayed. Engineers can adjust and modify the capacitor unit shape, capacitor size parameters and any item in the board layer where the capacitor is located based on the displayed initial reference capacitor unit.

[0053] Through the above solution, the initial reference capacitor unit can be preset as needed, which facilitates subsequent adjustment and arrangement based on the initial reference capacitor.

[0054] In some embodiments, step 102 includes:

[0055] Step 1021: derive initial reference capacitance format data based on the initial reference capacitance unit.

[0056] In specific implementation, since the constructed initial reference capacitor unit cannot be directly subjected to parasitic extraction, it needs to be exported into initial reference capacitor format data.

[0057] Step 1022: Use a parasitic extraction program to perform parasitic capacitance extraction on the initial reference capacitance format data to obtain a first parasitic capacitance value.

[0058] In specific implementation, a parasitic extraction program is created in advance using a script programming language, so that the parasitic extraction program can be used to perform a parasitic capacitance extraction process, thereby obtaining a first parasitic capacitance value between two plates corresponding to an initial reference capacitor unit.

[0059] Step 1023: compare the first parasitic capacitance value with a first predetermined range to obtain a comparison result.

[0060] Step 1024 , in response to the comparison result being outside the first predetermined range, determining a capacitance adjustment amount according to the comparison result, and adjusting the initial reference capacitance unit using the capacitance adjustment amount until the comparison result is within the first predetermined range.

[0061] Step 1025 : In response to the comparison result being within the first predetermined range, taking the final initial reference capacitor unit as the target capacitor unit.

[0062] In specific implementation, a first predetermined range will be set in advance according to the needs, and the first predetermined range can be determined according to the capacitance value of the target capacitor unit required, and the first predetermined range can have a certain floating range above and below the capacitance value of the required target capacitor unit. In this way, if the first parasitic capacitance value exceeds the first predetermined range, it is proved that the initial reference capacitor unit does not meet the requirements, and it is necessary to adjust the capacitor unit shape, capacitor size parameters and any one of the board layers where the capacitor is located in the initial reference capacitor unit. After the adjustment, the above steps 1022 and 1023 will continue to be executed until the first parasitic capacitance value falls within the first predetermined range, and the final initial reference capacitor unit is used as the target capacitor unit.

[0063] Through the above solution, the adjustment process of the initial reference capacitor unit can be automatically completed without human intervention, which can speed up the adjustment process, reduce human errors, and make the determined target capacitor unit more accurate.

[0064] In some embodiments, step 1021 includes:

[0065] Step 10211, constructing an initial circuit diagram according to the initial reference capacitor unit using a circuit creation program.

[0066] In a specific implementation, a circuit creation program in an interactive programming language is used to construct a basic initial circuit diagram. For example, a label corresponding to the initial circuit diagram may be created and named name(1), and the first electrode plate is defined as P and the second electrode plate is defined as M.

[0067] Step 10212: construct an initial layout according to the initial reference capacitor unit through a layout creation program.

[0068] In the specific implementation, a layout creation program in an interactive programming language is used to construct a basic initial layout. For example, the initial layout is named name(1), and the first electrode plate is defined as P and the second electrode plate is defined as M.

[0069] Step 10213, using a layout export program to export the initial circuit diagram and the initial layout to obtain initial reference capacitor format data.

[0070] In the specific implementation, a layout export program is created in advance using a script programming language according to the instruction data in the auxiliary document provided by the integrated circuit and layout tool. In this way, the layout export program can be used to perform the export process on the initial circuit diagram and the initial layout. For example, the initial circuit diagram and the initial layout of name (1) are exported into layout format data and circuit format data.

[0071] Through the above solution, the process of constructing and deriving the initial reference capacitor unit can be effectively guaranteed.

[0072] In some embodiments, step 1022 includes:

[0073] Step 10221, using a layout circuit connection relationship verification program to verify the circuit connection relationship of the initial reference capacitor format data, and obtaining a layout circuit connection relationship verification result.

[0074] In the specific implementation, a layout circuit connection relationship verification program is created in advance using a script programming language, and then the corresponding verification instructions in the layout circuit connection relationship verification program are used to verify the circuit connection relationship of the initial reference capacitor format data, thereby obtaining the layout circuit connection relationship verification result.

[0075] Step 10222: Convert the layout circuit connection relationship verification result into a parasitic input file.

[0076] During specific implementation, a conversion program is created in advance using a script programming language, so that the created conversion program can be used to convert the layout circuit connection relationship verification result into a parasitic input file.

[0077] Step 10223: Perform parasitic extraction on the parasitic input file using a parasitic extraction program to obtain the first parasitic capacitance value.

[0078] In a specific implementation, a parasitic extraction program is created using a script programming language, so that parasitic extraction instructions corresponding to the parasitic extraction program can be used to perform parasitic extraction to obtain a parasitic file including the first parasitic capacitance value.

[0079] Through the above solution, the process of circuit relationship verification and parasitic capacitance extraction can be accurately completed. This process is completed automatically, conveniently and quickly.

[0080] In some embodiments, step 1024 includes:

[0081] Step 10241: In response to the comparison result that the difference between the preset capacitance threshold and the first parasitic capacitance value is greater than the first threshold, a predetermined number of board layers are added to the initial reference capacitance unit.

[0082] Alternatively, in step 10242, in response to the comparison result that the difference between the preset capacitance threshold and the first parasitic capacitance value is greater than the second threshold and less than or equal to the first threshold, an increase is determined based on the difference, and the capacitance length of the initial reference capacitance unit is increased by the increase; wherein the first threshold>the second threshold≥0.

[0083] Alternatively, in step 10243, in response to the comparison result that the difference between the preset capacitance threshold and the first parasitic capacitance value is less than a third threshold, a reduction amount is determined based on the difference, and the capacitance length of the initial reference capacitance unit is reduced by the reduction amount; wherein the third threshold ≤0.

[0084] In specific implementation, the required preset capacitance threshold is preset, and then the preset capacitance threshold is compared with the first parasitic capacitance value to calculate the preset capacitance threshold-first parasitic capacitance value=difference. The difference value can be directly compared with the numerical values ​​of the first threshold (e.g., H1, unit f), the second threshold (e.g., H2, unit f), and the third threshold (e.g., -H1, unit f).

[0085] The difference may also be converted into a percentage (difference / first parasitic capacitance value)*100%, and the corresponding first threshold (eg, J1%), second threshold (eg, J2%) and third threshold (eg, -J1%).

[0086] After the above steps 10241 or 10242 or 10243 are executed, the processes of 1022 and 1023 will be repeated until the difference falls within the range from the third threshold to the first threshold.

[0087] Through the above solution, the adjustment process of the initial reference capacitor unit can be automatically completed without human intervention, which is convenient to use and reduces labor costs.

[0088] In some embodiments, step 103 includes:

[0089] Step 1031 : using a circuit creation program to retrieve at least one target capacitor unit according to set ratio data to create a first sampling capacitor circuit.

[0090] In a specific implementation, the set ratio data is the ratio data input by the engineer according to the needs of the sampling circuit (for example, a1: a2: a3: a4: a5), so that the number of target capacitor units can be determined according to the ratio data, and these target capacitor units are connected by circuits to obtain the first sampling capacitor circuit.

[0091] Step 1032: Create a first sampling capacitor circuit layout based on the first sampling capacitor circuit by using a layout creation program.

[0092] Step 1033 , performing regional arrangement on at least one target capacitor unit in the first sampling capacitor circuit layout to obtain an initial sampling circuit layout.

[0093] In specific implementation, the size parameters corresponding to the first sampling capacitor circuit layout are first set according to the needs of the actual layout, and a first sampling capacitor circuit layout can be created according to the first sampling capacitor circuit and the size parameters of the target capacitor unit. In this way, the target capacitor unit can be arranged in the first sampling capacitor circuit layout according to a certain arrangement principle, so that the capacitance distribution can be relatively uniform, and the corresponding initial sampling circuit layout can be obtained after the arrangement.

[0094] Through the above solution, the user only needs to input the set ratio data and the corresponding layout size requirements to automatically generate the corresponding initial sampling circuit layout, which is convenient and fast.

[0095] In some embodiments, step 1031 includes:

[0096] Step 10311, create a sampling capacitor circuit model using a circuit creation program.

[0097] During specific implementation, a circuit creation function in a circuit creation program constructed using an interactive programming language is used to create a sampling capacitor circuit model.

[0098] Step 10312: In the sampling capacitor circuit model, retrieve the target capacitor unit, and determine the set number of the target capacitor unit according to the ratio data.

[0099] Step 10313: Based on the sampling capacitor circuit model, a set number of target capacitor units are distributed and connected according to the proportion data to obtain a connected sampling capacitor circuit model.

[0100] Step 10314: Use the connected sampling capacitor circuit model as the first sampling capacitor circuit.

[0101] Through the above solution, the creation process of the first sampling capacitor circuit can be automatically completed, the creation process is simplified, and the use is convenient.

[0102] In some embodiments, step 10313 includes:

[0103] Step 103131, connecting the first plates (eg, upper plates) of a set number of target capacitor units to form a first end (eg, VOUT) of the sampling capacitor circuit model.

[0104] Step 103132, the second plates (for example, the lower plates) of the set number of target capacitor units are allocated in quantity according to each proportional value of the proportional data, and all target capacitor units corresponding to each proportional value after allocation are connected to form the second end (for example, VIN) of the sampling capacitor circuit model to obtain a connected sampling circuit model.

[0105] Through the above scheme, the connection can be automatically distributed according to the proportional data to obtain an accurate sampling circuit model without human intervention, which is convenient and fast.

[0106] In some embodiments, step 1033 includes:

[0107] Step 10331: determine the number of rows of at least one target capacitor unit in the first sampling capacitor circuit layout, and allocate at least one target capacitor unit according to the number of rows.

[0108] In a specific implementation, the number of rows of the capacitor array corresponding to the first sampling capacitor circuit layout is calculated according to the total number of target capacitor units required, the size of each target capacitor unit, and the size (for example, length, width, or aspect ratio) of the received set first sampling capacitor circuit layout, and the target capacitor units are arranged according to the number of rows.

[0109] Step 10332, determine the number of target capacitor cells corresponding to each row.

[0110] Step 10333: divide the capacitor arrangement position into at least three areas, namely a middle area and edge areas distributed on both sides of the middle area.

[0111] Step 10334, placing the rows whose number of cells is less than a first number threshold (eg, N1) in the middle area.

[0112] Step 10335: arrange the rows whose number of cells is greater than or equal to the first number threshold in two edge areas respectively to obtain an initial sampling circuit layout.

[0113] In a specific implementation, after the middle area and the edge area are arranged, a floating metal pattern (for example, dummy) is placed in the corresponding blank space.

[0114] Through the above scheme, the target capacitor units are arranged based on the principle of less capacitance in the middle and more capacitance on both sides, so that the corresponding parasitic capacitance can be relatively stable when the parasitic capacitance is extracted.

[0115] As a further preferred embodiment, the middle area can also be arranged in a manner that the middle capacitance is small and the capacitance on both sides is large; the edge areas on both sides can also be arranged in a manner that the middle capacitance is small and the capacitance on both sides is large, so that the capacitance distribution is further stabilized.

[0116] In some embodiments, the step 10335 of arranging the rows having the number of cells greater than or equal to the first number threshold in two edge regions respectively includes:

[0117] Divide each edge region into at least one edge sub-region, and perform the following operations on each edge sub-region:

[0118] Step 103351, dividing the edge sub-region into at least three regions, namely a middle sub-region and edge sub-regions distributed on both sides of the middle sub-region.

[0119] Step 103352, arranging rows whose number of cells is greater than or equal to a first number threshold and less than a second number threshold (for example, N2) in the middle sub-region;

[0120] Step 103353: Set the rows whose number of cells is greater than or equal to the second number threshold in two edge sub-regions respectively.

[0121] During specific implementation, the number of edge sub-regions divided into each edge region can be set according to actual needs.

[0122] Through the above solution, each edge sub-region is arranged according to the principle of less number in the middle and more number on both sides, which can make the target capacitor unit more symmetrical, thereby further improving the stability of the parasitic capacitance.

[0123] In some embodiments, step 104 includes:

[0124] Step 1041, exporting the initial sampling circuit layout using a layout export program to obtain initial sampling capacitor format data.

[0125] During specific implementation, a layout export program is called, and the layout export program is used to perform an export process on the initial sampling circuit layout to obtain corresponding initial sampling capacitor format data.

[0126] Step 1042: extract the parasitic capacitance of the initial sampled capacitance format data through a parasitic extraction program to obtain a second parasitic capacitance value.

[0127] In the specific implementation, the layout circuit connection relationship verification program is called, and the layout circuit connection relationship verification program is used to verify the circuit connection relationship of the initial sampling capacitance format data, thereby obtaining the layout circuit connection relationship verification result. After the layout circuit connection relationship verification result is converted into a parasitic input file, the parasitic extraction program is used to extract the parasitic capacitance of the parasitic input file to obtain a parasitic extraction file including the second parasitic capacitance value.

[0128] Step 1043, comparing the second parasitic capacitance value with a second predetermined range, adjusting the layout of the initial sampling circuit according to the comparison result, and using the adjusted initial sampling circuit as the target sampling circuit.

[0129] In specific implementation, the specific value of the second predetermined range can be pre-set based on the corresponding ratio data according to actual needs. In this way, if the second parasitic capacitance value exceeds the second predetermined range, it proves that the second parasitic capacitance value does not meet the requirements, and the layout of the initial sampling circuit layout needs to be adjusted, specifically adjusting the corresponding arrangement order or adjusting the corresponding board layer. After the adjustment, the corresponding second parasitic capacitance value is extracted and compared with the second predetermined range, and the process is repeated until the second parasitic capacitance value is within the second predetermined range, and the adjusted initial sampling circuit layout is used as the target sampling circuit layout.

[0130] Through the above solution, the adjustment process of the initial sampling circuit layout is automatically completed, which can ensure the accuracy of the adjustment process, reduce human errors, and improve adjustment efficiency.

[0131] In some embodiments, at least one target capacitor unit in the initial sampling circuit layout is arranged in quantity according to each proportional value of the proportional data; the second parasitic capacitance includes: a first sub-parasitic capacitance value of the target capacitor unit corresponding to each proportional value, and the second predetermined range includes: a proportional error range.

[0132] Step 1043 includes:

[0133] Step 10431, determining whether the ratio difference between the capacitance ratio of each first sub-parasitic capacitance value and the ratio data is within a ratio error range.

[0134] For example, the proportional error range is -X to X, and the calculated proportional difference Y is used to determine whether -X≤Y≤X is satisfied.

[0135] For example, the determined proportional error range is 0 to X, and the absolute value of the proportional difference Y is calculated , determine whether ≤X.

[0136] Step 10432, in response to the ratio difference exceeding the ratio error range, the target capacitor units arranged in the initial sampling circuit layout are adjusted according to the rule that the number of target capacitor units in the two side areas is higher than the number of target capacitor units in the middle area, until the ratio difference is within the ratio error range.

[0137] In specific implementation, the rows corresponding to the target capacitor units in the edge areas on both sides can be adjusted, and the rows corresponding to the same number of target capacitor units in the edge areas on both sides can be swapped, and then the above steps 1041 and 1042 are repeated until the proportional difference is within the proportional error range. In addition, during the adjustment process, the arrangement of the edge areas can be increased, and the edge areas are arranged in a manner with a small number in the middle and a large number on both sides. If the proportional difference still exceeds the proportional error range, the edge area will be divided into multiple edge sub-areas, and each edge sub-area will be divided according to the process of steps 103351 to 103353; if the proportional difference still exceeds the proportional error range, the number of edge sub-areas in each edge area will continue to be increased, and each edge sub-area will be divided according to the process of steps 103351 to 103353; this process is repeated until the proportional difference is within the proportional error range.

[0138] Step 10433: In response to the ratio difference being within the ratio error range, taking the final initial sampling circuit layout as the target sampling circuit layout.

[0139] Through the above scheme, the layout adjustment process of the target sampling circuit layout can be automatically completed according to the proportional data, ensuring that the parasitic capacitance in the obtained target sampling circuit layout meets the requirements of the proportional data.

[0140] In some embodiments, the second parasitic capacitance includes: a second sub-parasitic capacitance value between a first end and a ground line of at least one target capacitance unit in the initial sampling circuit layout, and the second predetermined range includes: a capacitance setting range to ground.

[0141] Step 1043 includes:

[0142] Step 10431', comparing the second sub-parasitic capacitance value with the set range of ground capacitance to obtain a comparison result.

[0143] For example, the capacitance setting range to ground is determined according to the set capacitance threshold value to ground Z, the capacitance range to ground is 0 to Z, the obtained second sub-parasitic capacitance value C is determined, and it is judged whether C≤Z is satisfied.

[0144] Step 10432', in response to the comparison result that the second sub-parasitic capacitance value exceeds the set range of the ground capacitance, the board layer where the target capacitor unit is currently located is increased by a predetermined number of layers (for example, an overall increase of n layers, from n1 to n2 layers to n1+n to n2+n layers) until the second sub-parasitic capacitance value is within the set range of the ground capacitance.

[0145] The board layer is the metal layer of the circuit board corresponding to the target sampling circuit layout, and each circuit board will be arranged with multiple metal layers. The board layer is counted based on the metal layer on one side of the substrate, and increasing the predetermined number of layers means increasing the predetermined number of layers away from the substrate, because increasing the distance from the substrate will reduce the second sub-parasitic capacitance value, thereby enabling it to meet the requirement that the second sub-parasitic capacitance value is within the set range of the ground capacitance.

[0146] Step 10433': in response to the comparison result that the second sub-parasitic capacitance value is within the set range of the capacitance to ground, the final initial sampling circuit layout is used as the target sampling circuit layout.

[0147] Through the above scheme, the board layer corresponding to the initial sampling circuit layout can be automatically adjusted, so that the final initial sampling circuit layout is more in line with the requirements of the setting range of the ground capacitance, and a more accurate target sampling circuit layout is obtained.

[0148] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0149] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0150] Based on the same inventive concept, corresponding to any of the above embodiments, refer to Figure 2 , the present application also provides a device 200 for determining a sampling circuit layout.

[0151] The sampling circuit layout determination device 200 comprises:

[0152] A reference capacitor creation module 201 is configured to create an initial reference capacitor unit;

[0153] The reference capacitance adjustment module 202 is configured to verify the initial reference capacitance unit to obtain a verification result, determine a capacitance adjustment amount corresponding to the verification result, and adjust the initial reference capacitance unit using the capacitance adjustment amount to obtain a target capacitance unit;

[0154] The sampling capacitor arrangement module 203 is configured to arrange at least one target capacitor unit to obtain an initial sampling circuit layout;

[0155] The sampling capacitor adjustment module 204 is configured to perform an error analysis on the initial sampling circuit layout, and adjust the arrangement of the initial sampling circuit layout according to the error analysis result to obtain a target sampling circuit layout.

[0156] In some embodiments, the reference capacitance creation module 201 is specifically configured as follows:

[0157] Setting the shape of the capacitor unit in which the first electrode plate surrounds the second electrode plate, and / or the capacitor size parameters, and / or the plate layer where the capacitor is located;

[0158] The initial reference capacitor unit is formed according to at least one of the capacitor unit shape, the capacitor size parameter and the capacitor layer.

[0159] In some embodiments, the reference capacitance adjustment module 202 includes:

[0160] A first exporting unit is configured to export initial reference capacitance format data based on the initial reference capacitance unit;

[0161] A first parasitic extraction unit is configured to perform parasitic capacitance extraction on the initial reference capacitance format data using a parasitic extraction program to obtain a first parasitic capacitance value;

[0162] A first comparison unit is configured to compare the first parasitic capacitance value with a first predetermined range to obtain a comparison result; in response to the comparison result exceeding the first predetermined range, determine a capacitance adjustment amount according to the comparison result, and use the capacitance adjustment amount to adjust the initial reference capacitance unit until the comparison result is within the first predetermined range; in response to the comparison result being within the first predetermined range, use the final initial reference capacitance unit as the target capacitance unit.

[0163] In some embodiments, the first exporting unit is specifically configured to:

[0164] Using a circuit creation program to construct an initial circuit diagram according to the initial reference capacitor unit;

[0165] Constructing an initial layout according to the initial reference capacitor unit by a layout creation program;

[0166] The initial circuit diagram and the initial layout are exported using a layout export program to obtain initial reference capacitor format data.

[0167] In some embodiments, the first parasitic extraction unit is specifically configured as follows:

[0168] Using a layout circuit connection relationship verification program to verify the circuit connection relationship of the initial reference capacitor format data, and obtain a layout circuit connection relationship verification result;

[0169] Converting the layout circuit connection relationship verification result into a parasitic input file;

[0170] A parasitic extraction program is used to perform parasitic extraction on the parasitic input file to obtain the first parasitic capacitance value.

[0171] In some embodiments, the first comparison unit is specifically configured as follows:

[0172] In response to the comparison result being that the difference between the preset capacitance threshold and the first parasitic capacitance value is greater than the first threshold, adding a predetermined number of board layers to the initial reference capacitance unit;

[0173] or,

[0174] In response to the comparison result that the difference between the preset capacitance threshold and the first parasitic capacitance value is greater than the second threshold and less than or equal to the first threshold, determining an increase amount according to the difference, and increasing the capacitance length of the initial reference capacitance unit by the increase amount; wherein the first threshold>the second threshold≥0;

[0175] or,

[0176] In response to the comparison result that the difference between the preset capacitance threshold and the first parasitic capacitance value is less than a third threshold, a reduction amount is determined according to the difference, and the capacitance length of the initial reference capacitance unit is reduced by the reduction amount; wherein the third threshold ≤0.

[0177] In some embodiments, the sampling capacitor arrangement module 203 includes:

[0178] A sampling capacitor circuit creation unit is configured to use a circuit creation program to retrieve at least one target capacitor unit according to set ratio data to create a first sampling capacitor circuit;

[0179] A sampling capacitor circuit layout creation unit, configured to create a first sampling capacitor circuit layout based on the first sampling capacitor circuit by using a layout creation program;

[0180] The area arrangement unit is configured to perform area arrangement on at least one target capacitor unit in the first sampling capacitor circuit layout to obtain an initial sampling circuit layout.

[0181] In some embodiments, the sampling capacitor circuit creation unit is specifically configured as follows:

[0182] Create a sampling capacitor circuit model using a circuit creation program;

[0183] In the sampling capacitor circuit model, the target capacitor unit is retrieved, and a set number of the target capacitor unit is determined according to the ratio data;

[0184] Based on the sampling capacitor circuit model, a set number of target capacitor units are distributed and connected according to the proportion data to obtain a connected sampling capacitor circuit model;

[0185] The connected sampling capacitor circuit model is used as the first sampling capacitor circuit.

[0186] In some embodiments, the sampling capacitor circuit creation unit is further configured to:

[0187] Connecting a set number of first plates of target capacitor units to form a first end of a sampling capacitor circuit model;

[0188] The second plates of the set number of target capacitor units are allocated in quantity according to each proportional value of the proportional data, and all target capacitor units corresponding to each proportional value after allocation are connected to form the second end of the sampling capacitor circuit model to obtain a connected sampling circuit model.

[0189] In some embodiments, the area arrangement unit is specifically configured as follows:

[0190] Determine the number of rows of at least one target capacitor unit in the first sampling capacitor circuit layout, and allocate at least one target capacitor unit according to the number of rows;

[0191] Determine the number of target capacitor cells corresponding to each row;

[0192] The capacitor arrangement position is divided into at least three areas, namely a middle area and edge areas distributed on both sides of the middle area;

[0193] The rows whose number of cells is less than the first number threshold are arranged in the middle area;

[0194] The rows with the number of cells greater than or equal to the first number threshold are respectively arranged in two edge areas to obtain an initial sampling circuit layout.

[0195] In some embodiments, the area arrangement unit is further configured as follows:

[0196] Divide each edge region into at least one edge sub-region, and perform the following operations on each edge sub-region:

[0197] Dividing the edge sub-region into at least three regions, namely a middle sub-region and edge sub-regions distributed on both sides of the middle sub-region;

[0198] Arrange the rows whose number of cells is greater than or equal to a first number threshold and less than a second number threshold in the middle sub-region;

[0199] The rows whose number of cells is greater than or equal to the second number threshold are respectively arranged in two edge sub-regions.

[0200] In some embodiments, the sampling capacitance adjustment module 204 includes:

[0201] A second exporting unit is configured to export the initial sampling circuit layout using a layout exporting program to obtain initial sampling capacitor format data;

[0202] A second parasitic extraction unit is configured to perform parasitic capacitance extraction on the initial sampled capacitance format data through a parasitic extraction program to obtain a second parasitic capacitance value;

[0203] The second comparison unit is configured to compare the second parasitic capacitance value with a second predetermined range, adjust the layout of the initial sampling circuit according to the comparison result, and use the adjusted initial sampling circuit layout as the target sampling circuit layout.

[0204] In some embodiments, at least one target capacitance unit in the initial sampling circuit layout is arranged in quantity according to each proportional value of the proportional data; the second parasitic capacitance includes: a first sub-parasitic capacitance value of the target capacitance unit corresponding to each proportional value, and the second predetermined range includes: a proportional error range;

[0205] The second comparison unit is specifically configured as follows:

[0206] Determine whether a ratio difference between a capacitance ratio of each first sub-parasitic capacitance value and the ratio data is within a ratio error range;

[0207] In response to the ratio difference exceeding the ratio error range, adjusting the target capacitor units arranged in the initial sampling circuit layout according to a rule that the number of target capacitor units in the two side regions is higher than the number of target capacitor units in the middle region until the ratio difference is within the ratio error range;

[0208] In response to the ratio difference being within the ratio error range, the final initial sampling circuit layout is used as the target sampling circuit layout.

[0209] In some embodiments, the second parasitic capacitance includes: a second sub-parasitic capacitance value between a first end and a ground line of at least one target capacitance unit in the initial sampling circuit layout, and the second predetermined range includes: a capacitance setting range to ground;

[0210] The second comparison unit is specifically configured as follows:

[0211] Comparing the second sub-parasitic capacitance value with a set range of ground capacitance to obtain a comparison result;

[0212] In response to the comparison result that the second sub-parasitic capacitance value exceeds the set range of ground capacitance, the board layer where the target capacitance unit is currently located is increased by a predetermined number of layers until the second sub-parasitic capacitance value is within the set range of ground capacitance;

[0213] In response to the comparison result that the second sub-parasitic capacitance value is within the set range of the capacitance to ground, the final initial sampling circuit layout is used as the target sampling circuit layout.

[0214] For the convenience of description, the above device is described in terms of functions divided into various modules. Of course, when implementing the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0215] The device of the above embodiment is used to implement the corresponding method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0216] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method described in any of the above embodiments when executing the program.

[0217] Figure 3 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0218] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0219] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0220] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0221] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0222] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010 , the memory 1020 , the input / output interface 1030 , and the communication interface 1040 ).

[0223] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0224] The electronic device of the above embodiment is used to implement the corresponding method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0225] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the method described in any of the above embodiments.

[0226] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0227] The computer instructions stored in the storage medium of the above embodiments are used to enable the computer to execute the method described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0228] Based on the same concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a computer program product, including computer program instructions. When the computer program instructions are run on a computer, the computer executes the method described in any of the above embodiments, which has the beneficial effects of the corresponding method embodiments and will not be repeated here.

[0229] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0230] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power / ground connections to the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device may be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0231] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0232] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A method for determining a sampling circuit layout, characterized in that: include: Create an initial reference capacitor unit; Verifying the initial reference capacitor unit to obtain a verification result, determining a capacitance adjustment amount corresponding to the verification result, and adjusting the initial reference capacitor unit using the capacitance adjustment amount to obtain a target capacitor unit; Arrange at least one target capacitor unit to obtain an initial sampling circuit layout; Performing an error analysis on the initial sampling circuit layout, and adjusting the arrangement of the initial sampling circuit layout according to the error analysis result to obtain a target sampling circuit layout; The verifying the initial reference capacitor unit to obtain a verification result, determining a capacitance adjustment amount corresponding to the verification result, and adjusting the initial reference capacitor unit using the capacitance adjustment amount to obtain a target capacitor unit, includes: Based on the initial reference capacitance unit, deriving initial reference capacitance format data; Using a parasitic extraction program to extract parasitic capacitance from the initial reference capacitance format data to obtain a first parasitic capacitance value; Comparing the first parasitic capacitance value with a first predetermined range to obtain a comparison result; In response to the comparison result being outside a first predetermined range, determining a capacitance adjustment amount according to the comparison result, and adjusting the initial reference capacitance unit using the capacitance adjustment amount until the comparison result is within the first predetermined range; In response to the comparison result being within the first predetermined range, taking the final initial reference capacitor unit as the target capacitor unit; The performing error analysis on the initial sampling circuit layout, and adjusting the arrangement of the initial sampling circuit layout according to the error analysis result to obtain the target sampling circuit layout, includes: Exporting the initial sampling circuit layout using a layout export program to obtain initial sampling capacitor format data; Performing parasitic capacitance extraction on the initial sampled capacitance format data through a parasitic extraction program to obtain a second parasitic capacitance value; The second parasitic capacitance value is compared with a second predetermined range, and the initial sampling circuit layout is arranged and adjusted according to the comparison result, and the adjusted initial sampling circuit layout is used as the target sampling circuit layout.

2. The method according to claim 1, characterized in that: The creating of the initial reference capacitor unit comprises: Setting the shape of the capacitor unit in which the first electrode plate surrounds the second electrode plate, and / or the capacitor size parameters, and / or the plate layer where the capacitor is located; The initial reference capacitor unit is formed according to at least one of the capacitor unit shape, the capacitor size parameter and the capacitor layer.

3. The method according to claim 1, characterized in that: The deriving the initial reference capacitance format data based on the initial reference capacitance unit includes: Using a circuit creation program to construct an initial circuit diagram according to the initial reference capacitor unit; Constructing an initial layout according to the initial reference capacitor unit by a layout creation program; The initial circuit diagram and the initial layout are exported using a layout export program to obtain initial reference capacitor format data.

4. The method according to claim 1 or 3, characterized in that: The using a parasitic extraction program to extract the parasitic capacitance of the initial reference capacitance format data to obtain a first parasitic capacitance value includes: Using a layout circuit connection relationship verification program to verify the circuit connection relationship of the initial reference capacitor format data, and obtain a layout circuit connection relationship verification result; Converting the layout circuit connection relationship verification result into a parasitic input file; A parasitic extraction program is used to perform parasitic extraction on the parasitic input file to obtain the first parasitic capacitance value.

5. The method according to claim 1 or 3, characterized in that: In response to the comparison result exceeding the first predetermined range, determining a capacitance adjustment amount according to the comparison result, and adjusting the initial reference capacitance unit using the capacitance adjustment amount, comprises: In response to the comparison result being that the difference between the preset capacitance threshold and the first parasitic capacitance value is greater than the first threshold, adding a predetermined number of board layers to the initial reference capacitance unit; or, In response to the comparison result that the difference between the preset capacitance threshold and the first parasitic capacitance value is greater than the second threshold and less than or equal to the first threshold, determining an increase amount according to the difference, and increasing the capacitance length of the initial reference capacitance unit by the increase amount; wherein the first threshold>the second threshold≥0; or, In response to the comparison result that the difference between the preset capacitance threshold and the first parasitic capacitance value is less than a third threshold, a reduction amount is determined according to the difference, and the capacitance length of the initial reference capacitance unit is reduced by the reduction amount; wherein the third threshold ≤0.

6. The method according to claim 1 or 2, characterized in that: Arranging at least one target capacitor unit to obtain an initial sampling circuit layout includes: Using a circuit creation program to retrieve at least one target capacitor unit according to set ratio data to create a first sampling capacitor circuit; Using a layout creation program to create a first sampling capacitor circuit layout based on the first sampling capacitor circuit; At least one target capacitor unit in the first sampling capacitor circuit layout is regionally arranged to obtain an initial sampling circuit layout.

7. The method according to claim 6, characterized in that The method of using the circuit creation program to retrieve at least one target capacitor unit according to the set ratio data to create a first sampling capacitor circuit includes: Create a sampling capacitor circuit model using a circuit creation program; In the sampling capacitor circuit model, the target capacitor unit is retrieved, and a set number of the target capacitor unit is determined according to the ratio data; Based on the sampling capacitor circuit model, a set number of target capacitor units are distributed and connected according to the proportion data to obtain a connected sampling capacitor circuit model; The connected sampling capacitor circuit model is used as the first sampling capacitor circuit.

8. The method according to claim 7, characterized in that Based on the sampling capacitor circuit model, the set number of target capacitor units are distributed and connected according to the proportion data to obtain a connected sampling capacitor circuit model, including: Connecting a set number of first plates of target capacitor units to form a first end of a sampling capacitor circuit model; The second plates of the set number of target capacitor units are allocated in quantity according to each proportional value of the proportional data, and all target capacitor units corresponding to each proportional value after allocation are connected to form the second end of the sampling capacitor circuit model to obtain a connected sampling circuit model.

9. The method according to claim 6, characterized in that The step of performing regional arrangement on at least one target capacitor unit in the first sampling capacitor circuit layout to obtain an initial sampling circuit layout includes: Determine the number of rows of at least one target capacitor unit in the first sampling capacitor circuit layout, and allocate at least one target capacitor unit according to the number of rows; Determine the number of target capacitor cells corresponding to each row; The capacitor arrangement position is divided into at least three areas, namely a middle area and edge areas distributed on both sides of the middle area; The rows whose number of cells is less than the first number threshold are arranged in the middle area; The rows with the number of cells greater than or equal to the first number threshold are respectively arranged in two edge areas to obtain an initial sampling circuit layout.

10. The method according to claim 9, characterized in that The step of arranging the rows having the number of cells greater than or equal to the first number threshold in two edge areas respectively includes: Divide each edge region into at least one edge sub-region, and perform the following operations on each edge sub-region: Dividing the edge sub-region into at least three regions, namely a middle sub-region and edge sub-regions distributed on both sides of the middle sub-region; Arrange the rows whose number of cells is greater than or equal to a first number threshold and less than a second number threshold in the middle sub-region; The rows whose number of cells is greater than or equal to the second number threshold are respectively arranged in two edge sub-regions.

11. The method according to claim 1, characterized in that: Arranging the quantity of at least one target capacitance unit in the initial sampling circuit layout according to each proportional value of the proportional data; The second parasitic capacitance includes: a first sub-parasitic capacitance value of the target capacitance unit corresponding to each proportional value, and the second predetermined range includes: a proportional error range; The step of comparing the second parasitic capacitance value with a second predetermined range, adjusting the layout of the initial sampling circuit according to the comparison result, and using the adjusted initial sampling circuit layout as the target sampling circuit layout includes: Determine whether a ratio difference between a capacitance ratio of each first sub-parasitic capacitance value and the ratio data is within a ratio error range; In response to the ratio difference exceeding the ratio error range, adjusting the target capacitor units arranged in the initial sampling circuit layout according to a rule that the number of target capacitor units in the two side regions is higher than the number of target capacitor units in the middle region, until the ratio difference is within the ratio error range; In response to the ratio difference being within the ratio error range, the final initial sampling circuit layout is used as the target sampling circuit layout.

12. The method according to claim 1, characterized in that The second parasitic capacitance includes: a second sub-parasitic capacitance value between a first end and a ground line of at least one target capacitance unit in the initial sampling circuit layout, and the second predetermined range includes: a capacitance setting range to ground; The step of comparing the second parasitic capacitance value with a second predetermined range, adjusting the layout of the initial sampling circuit according to the comparison result, and using the adjusted initial sampling circuit layout as the target sampling circuit layout includes: Comparing the second sub-parasitic capacitance value with a set range of ground capacitance to obtain a comparison result; In response to the comparison result that the second sub-parasitic capacitance value exceeds the set range of ground capacitance, the board layer where the target capacitance unit is currently located is increased by a predetermined number of layers until the second sub-parasitic capacitance value is within the set range of ground capacitance; In response to the comparison result that the second sub-parasitic capacitance value is within the set range of the capacitance to ground, the final initial sampling circuit layout is used as the target sampling circuit layout.

13. A device for determining a sampling circuit layout, characterized in that: include: A reference capacitor creation module, configured to create an initial reference capacitor unit; a reference capacitance adjustment module configured to verify the initial reference capacitance unit to obtain a verification result, determine a capacitance adjustment amount corresponding to the verification result, and adjust the initial reference capacitance unit using the capacitance adjustment amount to obtain a target capacitance unit; A sampling capacitor arrangement module is configured to arrange at least one target capacitor unit to obtain an initial sampling circuit layout; A sampling capacitor adjustment module is configured to perform an error analysis on the initial sampling circuit layout, and adjust the arrangement of the initial sampling circuit layout according to the error analysis result to obtain a target sampling circuit layout; Reference capacitor adjustment module, including: A first exporting unit is configured to export initial reference capacitance format data based on the initial reference capacitance unit; A first parasitic extraction unit is configured to perform parasitic capacitance extraction on the initial reference capacitance format data using a parasitic extraction program to obtain a first parasitic capacitance value; a first comparison unit, configured to compare the first parasitic capacitance value with a first predetermined range to obtain a comparison result; in response to the comparison result being beyond the first predetermined range, determine a capacitance adjustment amount according to the comparison result, and adjust the initial reference capacitance unit using the capacitance adjustment amount until the comparison result is within the first predetermined range; in response to the comparison result being within the first predetermined range, use the final initial reference capacitance unit as the target capacitance unit; Sampling capacitor adjustment module, including: A second exporting unit is configured to export the initial sampling circuit layout using a layout exporting program to obtain initial sampling capacitor format data; A second parasitic extraction unit is configured to perform parasitic capacitance extraction on the initial sampled capacitance format data through a parasitic extraction program to obtain a second parasitic capacitance value; The second comparison unit is configured to compare the second parasitic capacitance value with a second predetermined range, adjust the layout of the initial sampling circuit according to the comparison result, and use the adjusted initial sampling circuit layout as the target sampling circuit layout.

14. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 12 is implemented.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 12.

16. A computer program product comprising computer program instructions, characterized in that When the computer program instructions are executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 12.

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