Electron source, manufacturing method thereof and electron beam direct writing machine

Abstract

The invention provides an electron source, a manufacturing method thereof and an electron beam direct writing machine. The electron source comprises a substrate; the porous structure 2 is formed on the surface of the substrate; a pore wall insulating film (4) formed on the surface of the pore wall of the porous structure; a plurality of silicon nanocrystals 6 formed inside the pores of the porous structure; a crystal grain insulating film (7) formed on the surface of the silicon nanocrystal grains; a first electrode (8) formed on the substrate; and a second electrode 9 formed on the porous structure, in which the thickness of the pore wall insulating film 4 is not less than 20 nm, and the thickness of the grain insulating film 7 is in the range of 0.5 nm to 5 nm. According to the invention, the breakdown voltage of the hole wall insulating film can be improved, and the electron emission capability of the electron source can be maintained.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an electron source and a manufacturing method thereof and an electron beam direct writer. Background Art

[0002] High-performance electron sources are widely used in electron beam direct writing technology, flat panel displays, and X-ray sources.

[0003] The matrixization and high performance of electron sources are the requirements of many high-end applications. The electron source disclosed in reference 1 (reference 1: Japanese Journal of Applied Physics 61, SD0807 (2022), https: / / doi.org / 10.35848 / 1347-4065 / ac4ce1) is an array-type electron source that is conducive to miniaturization and high performance. The key technology of this array-type electron source is: growing a columnar polycrystalline silicon film with a high resistance on a low-resistance silicon substrate, forming a porous silicon structure on the polycrystalline silicon film by etching, and forming nanowires composed of nanosilicon grains in the pores of the porous silicon structure. When an appropriate voltage is applied between the silicon substrate and the porous silicon structure, the electrons will be accelerated to a certain energy through the nanowires, so that the electrons are emitted from the surface of the device into the atmosphere or vacuum. Reference 2 (Reference 2: Nobuyoshi Koshida, "Device Applications of Silicon Nanocrystals and Nanostructures," ISBN: 978-0-387-78688-9, e-ISBN: 978-0-387-78689-6, DOI: 10.1007 / 978-0-387-78689-6, Springer Science+Business Media, LLC 2009) discloses a technique for preparing such an electron source by forming a porous silicon structure on a columnar polycrystalline silicon film using a photoelectrochemical etching method.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] The inventors found that in the existing electron source, if the insulating film on the surface of the porous structure, especially the insulating film on the surface of the porous structure parallel to the emission surface, has insufficient breakdown voltage resistance, the insulating film will be broken down at a relatively low voltage, causing the electron source device to fail. When the breakdown voltage is relatively close to the driving voltage of the electron source, the reliability and life of the electron source will be reduced. Therefore, it is necessary to form an insulating film with a sufficiently high breakdown voltage on the surface of the porous structure so that the breakdown voltage is much greater than the driving voltage of the electron source. For example, the driving voltage of the electron source is 10V, and the breakdown voltage is preferably not less than 20V. In terms of structure, when the material and quality of the insulating film are certain, increasing the thickness of the insulating film is an effective means to increase the breakdown voltage of the insulating film. At the same time, in order to ensure the electron emission efficiency, the thickness of the insulating film wrapping the nano-silicon grains cannot be too thick. If the insulating film on the surface of the nano-silicon grains is too thick, the electron emission ability of the device will be reduced, or even completely unable to emit electrons. In terms of manufacturing methods, it is generally necessary to manufacture the insulating film on the surface of the porous structure after the porous structure and the nano-silicon grains are processed. If the manufacturing process is not appropriate, it is difficult to ensure that the thickness of the insulating film on the surface of the porous structure is thick enough and the thickness of the insulating film covering the nano-silicon grains is within a range suitable for electron emission. Therefore, how to set the appropriate thickness for the insulating film on the surface of the porous structure and the insulating film covering the nano-silicon grains becomes a problem that needs to be solved.

[0006] In order to solve the above problems or at least similar problems, the embodiments of the present application provide an electron source and a manufacturing method thereof and an electron beam direct writer. The thickness of the hole wall insulation film of the porous structure of the electron source is not less than 20nm, and the thickness of the grain insulation film in the porous structure is in the range of 0.5nm-5nm, thereby ensuring that the thickness of the hole wall insulation film on the surface of the porous structure is thick enough, and the thickness of the grain insulation film wrapping the nano-silicon grains is in a range suitable for electron emission, thereby improving the breakdown voltage of the hole wall insulation film and maintaining the electron emission capability of the electron source.

[0007] One aspect of an embodiment of the present application provides an electron source, the electron source comprising:

[0008] substrate;

[0009] A porous structure (2) formed on the surface of the substrate;

[0010] A pore wall insulating film (4) formed on the surface of the pore wall of the porous structure;

[0011] A plurality of silicon nanocrystals (6) formed inside the pores of the porous structure;

[0012] a grain insulating film (7) formed on the surface of the silicon nanocrystal grains,

[0013] a first electrode (8) formed on the substrate; and

[0014] a second electrode (9) formed on the porous structure,

[0015] in,

[0016] The thickness of the hole wall insulating film (4) is not less than 20 nm.

[0017] The thickness of the grain insulation film (7) is in the range of 0.5nm-5nm.

[0018] In some embodiments, the substrate comprises a silicon substrate, and the porous structure is formed in the silicon substrate; or

[0019] The substrate includes a silicon substrate and a polysilicon film formed on the silicon substrate, and the porous structure is at least partially formed in the polysilicon film.

[0020] In some embodiments, the hole wall insulating film or the grain insulating film is silicon oxide and / or silicon nitride.

[0021] In some embodiments, the second electrode is composed of a plurality of independent second electrode units.

[0022] A plurality of the second electrode units are arranged in an array.

[0023] Another aspect of an embodiment of the present application provides an electron beam direct writer, which includes the electron source described in any of the above embodiments.

[0024] Another aspect of the present application provides a method for manufacturing an electron source, which is used to manufacture the electron source described in the above embodiment. The manufacturing method includes:

[0025] Forming a porous structure on a substrate by an electrochemical etching method, wherein a plurality of silicon nanocrystals are contained in the voids of the porous structure;

[0026] Performing low-temperature film formation at a temperature T1 to form a grain insulating film on the surface of the silicon nanocrystal grains, so that the thickness of the grain insulating film is in the range of 0.5-5 nm, and forming a first layer of pore wall insulating film on the surface of the pore wall of the porous structure; and

[0027] High-temperature film formation is performed at temperature T2 to form a second layer of hole wall insulating film on the surface of the first layer of hole wall insulating film, so that the total thickness of the hole wall insulating film composed of the first layer of hole wall insulating film and the second layer of hole wall insulating film is not less than 20nm, wherein T2>T1.

[0028] In some embodiments, T1≤500°C, T2>500°C.

[0029] In some embodiments, the low temperature film forming includes electrochemical oxidation or thermal oxidation in an atmosphere containing oxygen;

[0030] The high-temperature film formation includes thermal oxidation in an atmosphere containing oxygen.

[0031] In some embodiments, the substrate comprises a silicon substrate, and the porous structure is formed in the silicon substrate; or

[0032] The substrate includes a silicon substrate and a polysilicon film formed on the silicon substrate, and the porous structure is at least partially formed in the polysilicon film.

[0033] In some embodiments, the hole wall insulating film or the grain insulating film is silicon oxide and / or silicon nitride.

[0034] The beneficial effect of the present application is that the thickness of the pore wall insulating film of the porous structure of the electron source is not less than 20nm, and the thickness of the grain insulating film in the porous structure is in the range of 0.5nm-5nm. Therefore, while ensuring that the thickness of the pore wall insulating film on the surface of the porous structure is thick enough, the thickness of the grain insulating film wrapping the nano-silicon grains is in a range suitable for electron emission, thereby both improving the breakdown voltage of the pore wall insulating film and maintaining the electron emission capability of the electron source.

[0035] With reference to the following description and accompanying drawings, the specific embodiments of the present application are disclosed in detail, indicating the way in which the principles of the present application can be adopted. It should be understood that the embodiments of the present application are not limited in scope. Within the scope of the spirit and clauses of the appended claims, the embodiments of the present application include many changes, modifications and equivalents.

[0036] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0037] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0039] Figure 1 is a schematic diagram of an electron source;

[0040] Figure 2 yes Figure 1 Enlarged view of part E in the middle;

[0041] Figure 3 is another schematic diagram of the electron source;

[0042] Figure 4 yes Figure 3 Enlarged view of part F;

[0043] Figure 5 yes Figure 3 Enlarged view of section G;

[0044] Figure 6 It is a schematic diagram of a method for manufacturing an electron source;

[0045] Figure 7 It is a flow chart of a method for manufacturing an electron source according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The foregoing and other features of the present application will become apparent through the following description with reference to the accompanying drawings. In the description and the accompanying drawings, specific embodiments of the present application are specifically disclosed, which show some embodiments in which the principles of the present application can be adopted. It should be understood that the present application is not limited to the described embodiments, on the contrary, the present application includes all modifications, variations and equivalents falling within the scope of the attached claims.

[0047] In the description of the various embodiments of the present application, for the convenience of description, the direction parallel to the first main surface of the substrate is called "lateral", the direction perpendicular to the first main surface of the substrate is called "longitudinal", and the longitudinal dimension of each component can be called "height" or "thickness".

[0048] It should be noted that the above-mentioned “horizontal” and “vertical” are only for the convenience of explanation and do not limit the orientation or posture of the electron source of the present application during manufacture or use.

[0049] Example 1

[0050] This embodiment utilizes Figure 1 and 2 The schematic diagram of FIG. 1 illustrates the main structure of the electron source of the present invention.

[0051] like Figure 1As shown, the structure of the electron source 100 includes a silicon substrate 1. In a special case, the silicon substrate 1 is an N-type silicon substrate with a resistivity in the range of 0.1-0.001Ωcm and a thickness in the range of 100-800 microns. A porous structure 2 is formed on a first main surface 1a of the silicon substrate, a first electrode 8 is formed on a second main surface 1b of the silicon substrate, and a second electrode 9 is formed on the porous structure 2.

[0052] Figure 2 Shows Figure 1 The microstructure of the area enclosed by the dotted box E in the figure. Figure 2 As shown, the porous structure 2 is a structure having a plurality of pores 5 formed in a silicon substrate 1. The porous structure 2 is composed of a portion of the silicon substrate 1 to form a skeleton 1c, and the pores 5 are formed in the middle of the skeleton 1c. In this embodiment, the thickness of the side wall of the skeleton 1c perpendicular to the first main surface 1a of the silicon substrate is approximately in the range of 10-1000nm, and the height is approximately in the range of 50-3000nm; the cross-sectional size of the pores 5 formed in the middle of the skeleton 1c parallel to the first main surface 1a of the silicon substrate is approximately in the range of 10-1000nm. A pore wall insulating film 4 is formed on the surface 3 of the skeleton 1c (i.e., the surface of the pore wall of the porous structure 2). The pore wall insulating film 4 is silicon oxide or silicon nitride, or a composite film of the two. The thickness of the pore wall insulating film 4 is not less than 20nm, for example, in the range of 20-500nm, preferably, the thickness of the pore wall insulating film 4 is in the range of 30-50nm. Preferably, the thickness of the hole wall insulating film 4a on the upper surface 3a of the skeleton 1c is not less than the thickness of the hole wall insulating film on other surfaces of the skeleton 1c. A plurality of silicon nanocrystal grains 6 are formed inside the pores 5, and the size of the silicon nanocrystal grains 6 is in the range of 1-10nm. A grain insulating film 7 is formed on the surface of the silicon nanocrystal grains 6. The grain insulating film 7 is silicon oxide or silicon nitride, or a composite film of the two. The thickness of the grain insulating film 7 is in the range of 0.5-5nm, and preferably, the thickness of the grain insulating film 7 is in the range of 1-3nm. Preferably, the grain insulating film 7 covers the surface of the silicon nanocrystal grain 6 relatively completely without nano-level defects. A silicon nanocrystal grain 6 and the grain insulating film 7 that wraps it constitute a nanocrystal grain unit 6a.

[0053] The first electrode 8 is made of a metal material. A special case is that the first electrode 8 is made of aluminum (Al) or an alloy of Al, and has a thickness of 500nm. The second electrode 9 is made of a conductive material. A special case is that the second electrode 9 is made of a single layer or a multilayer of graphene. Another special case is that the second electrode 9 is formed by stacking Ti and Au films, the Ti film is in close contact with the surface of the porous structure 2, and the Au film is superimposed on the Ti film. Among them, the thickness of the Ti film is in the range of 0.5-3nm, and the thickness of the Au film is in the range of 5-15nm. Preferably, the thickness of the Au film is in the range of 6-10nm.

[0054] for Figure 1-2 In the electron source 100 shown, when a certain voltage is applied between the first electrode 8 and the second electrode 9, the electrons pass through the porous structure 2 and are gradually accelerated in the direction of the electric field by the nanocrystalline grain units 6a therein, and eventually obtain energy greater than the surface potential of the second electrode 9, and are emitted from the surface of the second electrode 9 into the external environment to form emitted electrons.

[0055] A special case is that the second electrode 9 is composed of a plurality of independent second electrode units (not shown), and these second electrode units can be arranged in an array, and each second electrode unit can be insulated or electrically connected to each other, so that the electron source structure 100 forms an array electron source with a plurality of electron emission units. When each second electrode unit is insulated from each other, the electron source structure 100 is an array electron source with a plurality of independent electron emission units. A special case is that the above-mentioned array electron source contains 100-300,000 electron emission units. When the electron source structure 100 is an array electron source composed of a plurality of independent electron emission units, a dedicated integrated circuit (ASIC) chip can be used to drive and control the electron emission of each electron emission unit. The electron source 100 of this embodiment can be applied as an electron source of an electron beam direct writer. A special case is that the array electron source of this embodiment contains 250,000 electron emission units and is applied as an electron source of a multi-beam electron beam direct writer. As a special case, a multi-beam electron beam direct writer can be equipped with a plurality of array-type electron sources of the present embodiment.

[0056] Based on the electron source 100 of this embodiment, because the thickness of the hole wall insulating film 4 is not less than 20nm, the breakdown voltage of the electron source can be not less than 20V, ensuring that the electron source can stably operate at a driving voltage below 15V and has a long service life. On the other hand, since the thickness of the grain insulating film 7 is in the range of 0.5-5nm, the thickness is moderate, which can allow electrons to pass through each nano-grain unit through the tunneling effect and enable the electrons to obtain sufficient kinetic energy during the passing process. In this way, after the electrons pass through the porous structure 2, they can obtain kinetic energy greater than the work function of the second electrode 9 and be emitted from the surface of the second electrode 9 into the external environment to form an electron beam.

[0057] Example 2

[0058] This embodiment utilizes Figure 3-5 The schematic diagram of FIG. 1 illustrates the main structure of the electron source of the present invention.

[0059] contrast Figure 1 and Figure 3 It can be seen that the structure of the electron source 100 of this embodiment is substantially the same as that of the electron source of Embodiment 1. For the sake of simplicity, only the differences between this embodiment and Embodiment 1 are described below, and the similarities are omitted.

[0060] The biggest difference between the structure of the electron source 100 of this embodiment and the structure of the electron source of Embodiment 1 is that: the electron source 100 of this embodiment further forms a polycrystalline silicon film 10 on the first main surface 1a of the silicon substrate 1, and the porous structure 2 is at least partially formed inside the polycrystalline silicon film 10, for example, the porous structure 2 is mainly formed inside the polycrystalline silicon film 10, that is, the thickness of the part of the porous silicon structure 2 formed inside the polycrystalline silicon film 10 is greater than the thickness of the part of the porous silicon structure 2 formed inside the silicon substrate 1, or the porous silicon structure 2 is completely formed inside the polycrystalline silicon film 10. The thickness of the polycrystalline silicon film 10 is in the range of 200-5000nm, and the resistivity is more than 100 times the resistivity of the silicon substrate 1.

[0061] Figure 4 yes Figure 3 The enlarged image of the area enclosed by the dashed box F. Figure 4 As shown, the polysilicon film 10 is composed of a plurality of crystal columns (such as 10m, 10n) extending longitudinally in a direction perpendicular to the first main surface 1a of the silicon substrate 1, and grain boundaries are formed between adjacent crystal columns (for example, the grain boundary between crystal column 10m and crystal column 10n is 10mn).

[0062] Figure 5 yes Figure 3 The enlarged image of the area enclosed by the dashed box G. Figure 5 As shown, the skeleton 1c of the porous structure 2 is composed of crystal columns of polycrystalline silicon, and the pores 5 are mainly formed at the grain boundaries.

[0063] In the present application, as shown in Example 1, the substrate may include a silicon substrate 1, and a porous structure 2 is formed in the silicon substrate 1; or, as shown in Example 2, the substrate may include a silicon substrate 1 and a polycrystalline silicon film 10 formed on the silicon substrate 1, and the porous structure 2 is mainly formed in the polycrystalline silicon film 10.

[0064] Example 3

[0065] Embodiment 3 provides a method for manufacturing an electron source. Figure 7 It is a schematic diagram of a method for manufacturing an electron source according to an embodiment of the present application.

[0066] like Figure 7 As shown, the manufacturing method of the electron source of the present application includes:

[0067] 701. Forming a porous structure on a substrate by an electrochemical etching method, wherein a plurality of silicon nanocrystals are contained in the voids of the porous structure;

[0068] 702. Perform low-temperature film formation at a temperature T1 to form a grain insulating film on the surface of the silicon nanocrystal grains, so that the thickness of the grain insulating film is in the range of 0.5-5 nm, and form a first layer of pore wall insulating film on the surface of the pore wall of the porous structure; and

[0069] 703. Perform high-temperature film formation at temperature T2 to form a second layer of hole wall insulating film on the surface of the first layer of hole wall insulating film, so that the total thickness of the hole wall insulating film composed of the first layer of hole wall insulating film and the second layer of hole wall insulating film is not less than 20nm, wherein T2>T1.

[0070] In this embodiment, T1≤500°C, T2>500°C.

[0071] In this embodiment, the low-temperature film formation includes electrochemical oxidation or thermal oxidation in an atmosphere containing oxygen, and the high-temperature film formation includes thermal oxidation in an atmosphere containing oxygen.

[0072] In this embodiment, the substrate includes a silicon substrate in which the porous structure is formed; or the substrate includes a silicon substrate and a polysilicon film formed on the silicon substrate, and the porous structure is at least partially formed in the polysilicon film.

[0073] In this embodiment, the hole wall insulating film or the grain insulating film is silicon oxide and / or silicon nitride.

[0074] This embodiment provides a method for manufacturing an electron source 100. Figure 6 The schematic diagram of FIG. 1 illustrates the main points of the manufacturing method of this embodiment.

[0075] like Figure 6 As shown in a), a silicon substrate 1 is prepared first. In a special case, the silicon substrate 1 is an N-type silicon substrate with a resistivity of about 0.005Ωcm and a thickness of 400 microns.

[0076] Then, if Figure 6As shown in b), a porous structure 2 having a plurality of pores is formed on the first main surface 1a of the silicon substrate. The porous structure 2 is formed by an electrochemical etching method. During electrochemical etching, the silicon substrate 1 serves as an anode, and a cathode is placed parallel to and opposite to the first main surface 1a of the silicon substrate. The etching liquid is a mixture of hydrofluoric acid and ethanol, and a certain current is applied between the anode and the cathode. The current applied between the anode and the cathode can be a direct current or a pulse current. During the electrochemical etching process, light can also be irradiated to the first main surface 1a of the silicon substrate, and the irradiated light contains light of a wavelength that can be absorbed by the silicon substrate 1, so that sufficient electron-hole pairs are generated in the substrate, wherein at least some of the holes participate in the electrochemical corrosion. By controlling the conditions of electrochemical etching, that is, by controlling the composition of the etching liquid, the magnitude of the current, the illumination, and the etching time, the depth, pore size, and porosity of the porous structure 2 can be controlled.

[0077] Figure 6 c) shows Figure 6 The enlarged image of the area enclosed by the dotted frame H in b). Figure 6 As shown in c), while the porous structure 2 is formed, a plurality of silicon nanocrystal grains 6 are simultaneously formed inside the pores 5. By adjusting the conditions of electrochemical etching, the size of the silicon nanocrystal grains 6 is in the range of 1-5 nm; the depth of the porous structure 2 is about 0.5 microns, the cross-sectional size of the pores 5 parallel to the first main surface 1a of the silicon substrate is about 10-500 nm, and the porosity is about 20%-80%.

[0078] Then, if Figure 6As shown in c), low-temperature film formation is performed at a temperature T1. Through low-temperature film formation, a first layer of grain insulation film 7-1 is formed on the surface of the silicon nanocrystal 6, and a first layer of pore wall insulation film 4-1 is formed on the surface 3 of the pore wall of the porous structure 2. A special case is that the thickness of the first layer of grain insulation film 7-1 is in the range of 1-3nm, and the thickness of the first layer of pore wall insulation film 4-1 is in the range of 1-10nm. In this low-temperature film formation process, the temperature T1≤500℃. For example, this low-temperature film formation uses electrochemical oxidation (ECO: electro chemical oxidation) with a mixed solution containing sulfuric acid or potassium nitrate. In this electrochemical oxidation process, the temperature T1 is close to room temperature. Since the size of the silicon nanocrystal 6 is in the range of 1-5nm, it is constrained by the quantum effect, and the thickness of the first layer of grain insulation film 7-1 formed on the surface of the silicon nanocrystal 6 exhibits a self-stop phenomenon, which is relatively easy to control within the range of 1-3nm. However, since there is no constraint of quantum effect, by controlling the electrochemical oxidation time, the thickness of the first layer of hole wall insulation film 4-1 can be made thicker than the thickness of the first layer of grain insulation film 7-1. A special case is that the thickness of the first layer of hole wall insulation film 4-1 is in the range of 1-10nm. In order to enable the first layer of grain insulation film 7-1 to cover the surface of the silicon nanocrystalline grains 6 more completely, post-treatment can be performed after electrochemical oxidation. For example, the first layer of grain insulation film 7-1 is treated with high-pressure hot water at 260°C. For another example, the first layer of grain insulation film 7-1 is treated with thermal oxidation below 500°C. Another way of this low-temperature film formation is to directly perform thermal oxidation below 500°C. In the thermal oxidation process below 500°C, the film formation speed of the first layer of grain insulation film 7-1 is very slow, and its thickness is relatively easy to control in the range of 1-3nm. During the thermal oxidation process below 500°C, a first layer of pore wall insulation film 4-1 can also be formed on the surface 3 of the pore wall of the porous structure 2 at the same time, and its thickness is not less than the thickness of the first layer of grain insulation film 7-1. The first layer of grain insulation film 7-1 and the pore wall insulation film 4-1 formed by electrochemical oxidation or thermal oxidation are silicon oxide films. Heat treatment below 500°C in a nitrogen atmosphere can also make the first layer of grain insulation film 7-1 and the pore wall insulation film 4-1 silicon nitride films. During the thermal oxidation process below 500°C or the heat treatment process in a nitrogen atmosphere, huge stress will be generated on the surface of the silicon nano-crystal grains 6, so that the growth rate of the first layer of grain insulation film 7-1 on the surface of the silicon nano-crystal grains 6 is slower than the growth rate of the pore wall insulation film 4-1. As a result, the thickness of the pore wall insulation film 4-1 can be made greater than the thickness of the first layer of grain insulation film 7-1.

[0079] Then, if Figure 6As shown in d), high-temperature film forming is performed at a temperature of T2. Through high-temperature film forming, a second layer of hole wall insulating film 4-2 is further formed, so that the total thickness of the hole wall insulating film 4 composed of the first layer of hole wall insulating film 4-1 and the second layer of hole wall insulating film 4-2 is not less than 20nm. The temperature T2 of high-temperature film forming> the temperature T1 of low-temperature film forming, for example, T2>500℃. For example, T2 is about 900℃, which is thermal oxidation film forming. In the high-temperature thermal oxidation process, the film forming speed of the second layer of hole wall insulating film 4-2 is much greater than the speed of low-temperature film forming, so it is easy to form a thicker second layer of hole wall insulating film 4-2 in a relatively short time. For example, the thickness of the second layer of hole wall insulating film 4-2 is greater than 20nm. A special case is that the thickness of the second layer of hole wall insulating film 4-2 is about 30nm. In the process of high-temperature film formation, because a relatively complete first layer of grain insulation film 7-1 (such as a silicon oxide film) has been formed on the surface of the nano-sized silicon nanocrystal 6 during low-temperature film formation, under the constraints of quantum effects and stress, the thickness of the second layer of grain insulation film 7-2 can be very thin during the high-temperature film formation process using high-temperature oxidation. That is, under appropriate high-temperature film formation conditions, the thickness of the final grain insulation film 7 can be close to the thickness of the first layer of grain insulation film 7-1. When the low-temperature film formation and the high-temperature film formation obtain the same insulation film (for example, both are silicon oxide films), such as Figure 6 As shown in e), the first layer of hole wall insulation film 4-1 and the second layer of hole wall insulation film 4-2 are almost indistinguishable, and together constitute the hole wall insulation film 4; the first layer of grain insulation film 7-1 and the second layer of grain insulation film 7-2 are almost indistinguishable, and together constitute the grain insulation film 7. Each silicon nanocrystalline grain 6 and the grain insulation film 7 that wraps it constitute a nanocrystalline grain unit 6a. In some examples, the thickness of the hole wall insulation film 4a on the upper surface 3a of the skeleton 1c is not less than the thickness of the hole wall insulation film on other surfaces of the skeleton 1c.

[0080] pass Figure 6 c) Low temperature film formation and Figure 6 The high temperature film forming of d) forms a relatively thick (for example, greater than 20 nm) pore wall insulating film 4 on the surface 3 of the pore wall of the porous structure 2, and also forms a grain insulating film 7 with a suitable thickness (for example, 1-3 nm) on the surface of the silicon nano-grains.

[0081] Then, if Figure 6As shown in h), a first electrode 8 is formed on the second main surface 1b of the substrate. The method for forming the first electrode 8 can use the metal film forming and patterning technology commonly used in micro-electromechanical systems (MEMS). Similarly, a second electrode 9 is formed on the first main surface 1a of the substrate and the porous structure 2. A special case is that the first electrode 8 is made of aluminum (Al) or an Al alloy and has a thickness of 500nm. The second electrode 9 is formed by stacking titanium (Ti) and gold (Au) films, the Ti film is in close contact with the surface of the porous structure 2, and the Au film is superimposed on the Ti film. Among them, the thickness of the Ti film is in the range of 0.5-1nm, and the thickness of the Au film is in the range of 6-10nm. As needed, the second electrode 9 can be made into an array pattern composed of a plurality of independent second electrode units (not shown), so that the electron source structure 100 forms an array electron source with a plurality of independent electron emission units.

[0082] Figure 6 Schematic diagram for manufacturing Figure 1 The electron source 100 is taken as an example, that is, the substrate is a silicon substrate 1; the related description can be applied to manufacturing Figure 3 The electron source shown, that is, the substrate is a silicon substrate 1 and a polycrystalline silicon thin film 10 formed on the silicon substrate 1 .

[0083] In the manufacturing method of this embodiment, low-temperature film formation is performed first, and then high-temperature film formation. During low-temperature film formation, an insulating film with a thickness of no more than 5 nm is formed on the surface of the silicon nanocrystal grains, and the insulating film basically completely wraps the surface of the silicon nanocrystal grains. During high-temperature film formation, an insulating film with a total thickness of no less than 20 nm is formed on the surface of the porous structure, but the thickness of the insulating film on the surface of the silicon nanocrystal grains remains almost unchanged. Therefore, through the above-mentioned manufacturing method, it is possible to ensure that the thickness of the insulating film on the surface of the porous structure is thick enough, while the thickness of the insulating film wrapping the nano-silicon grains is within a range suitable for electron emission.

[0084] The electron source 100 manufactured according to the embodiment of the present application has the structure and performance of embodiments 1-2, and can be used as an electron source for an electron beam direct writer.

[0085] The present application is described above in conjunction with specific implementation methods, but it should be clear to those skilled in the art that these descriptions are exemplary and are not intended to limit the scope of protection of the present application. Those skilled in the art can make various modifications and variations to the present application based on the spirit and principles of the present application, and these modifications and variations are also within the scope of the present application.

Claims

1. An electron source, It is characterized in that The electron source comprises: substrate; A porous structure (2) formed on the surface of the substrate; A pore wall insulating film (4) formed on the surface of the pore wall of the porous structure; A plurality of silicon nanocrystals (6) formed inside the pores of the porous structure; a grain insulating film (7) formed on the surface of the silicon nanocrystal grains, a first electrode (8) formed on the substrate; and a second electrode (9) formed on the porous structure, in, The thickness of the hole wall insulating film (4) is not less than 20 nm. The thickness of the grain insulation film (7) is in the range of 0.5nm-5nm.

2. The electron source structure according to claim 1, It is characterized in that The substrate comprises a silicon substrate, and the porous structure is formed in the silicon substrate; or The substrate includes a silicon substrate and a polysilicon film formed on the silicon substrate, and the porous structure is at least partially formed in the polysilicon film.

3. The electron source according to claim 1 or 2, It is characterized in that The hole wall insulating film or the grain insulating film is silicon oxide and / or silicon nitride.

4. The electron source according to claim 1 or 2, It is characterized in that The second electrode is composed of a plurality of independent second electrode units. A plurality of the second electrode units are arranged in an array.

5. An electron beam direct writer, It is characterized in that The electron beam direct writer comprises the electron source according to any one of claims 1 to 4.

6. A method for manufacturing an electron source, for manufacturing the electron source as claimed in any one of claims 1 to 5, It is characterized in that The manufacturing method comprises: Forming a porous structure on a substrate by an electrochemical etching method, wherein a plurality of silicon nanocrystals are contained in the voids of the porous structure; Performing low-temperature film formation at a temperature T1 to form a grain insulating film on the surface of the silicon nanocrystal grains, so that the thickness of the grain insulating film is in the range of 0.5-5 nm, and forming a first layer of pore wall insulating film on the surface of the pore wall of the porous structure; and High temperature film forming is performed at a temperature T2 to form a second hole wall insulating film on the surface of the first hole wall insulating film, so that the total thickness of the hole wall insulating film composed of the first hole wall insulating film and the second hole wall insulating film is not less than 20nm, Among them, T 2 >T 1 .

7. The method for manufacturing an electron source according to claim 6, It is characterized in that T1≤500℃, T2>500℃.

8. The method for manufacturing an electron source according to claim 6, It is characterized in that The low-temperature film formation includes electrochemical oxidation or thermal oxidation in an atmosphere containing oxygen; The high-temperature film formation includes thermal oxidation in an atmosphere containing oxygen.

9. The method for manufacturing an electron source according to claim 6, It is characterized in that The substrate comprises a silicon substrate, and the porous structure is formed in the silicon substrate; or The substrate includes a silicon substrate and a polysilicon film formed on the silicon substrate, and the porous structure is at least partially formed in the polysilicon film.

10. The method for manufacturing an electron source according to claim 6, It is characterized in that The hole wall insulating film or the grain insulating film is silicon oxide and / or silicon nitride.

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