Manufacturing method of semiconductor device with field plate and semiconductor device

Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor device with a field plate and the semiconductor device, and is applied to the technical field of electronic devices. In the process of manufacturing the semiconductor device, formation of a first layer field plate, a source electrode and a drain electrode in the semiconductor device is integrated into the same step, so that the formed source electrode, the drain electrode and the first layer field plate are on the same layer, and the manufacturing steps of the semiconductor device can be simplified; therefore, the implementation cost and time for arranging the field plate in the semiconductor device are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic devices, and in particular to a method for manufacturing a semiconductor device with a field plate and the semiconductor device. Background Art

[0002] As a representative of wide bandgap (WBG) power semiconductor devices, GaN HEMTs have great potential in high-frequency power applications. In the design of lateral GaN HEMT switch devices, the voltage withstand capability of the switch device is a very important performance parameter. When the switch device is turned off, the main voltage withstand structure of the lateral GaN HEMT switch device is the depletion region between the gate (G) and the drain (D). Under the same depletion region size, the electric field distribution determines the size of the voltage withstand value, and there is an electric field concentration effect at the gate corner close to the drain side, resulting in an electric field peak here. When the electric field peak reaches a certain critical value, electric field breakdown will occur, which will affect the reliability of the device and even cause irreversible damage.

[0003] In order to improve the voltage resistance of semiconductor devices, a field plate structure is generally used. The main function of the field plate is to adjust the electric field distribution in the drift region, weaken the electric field spike that originally existed near the gate, and improve the voltage resistance of the semiconductor device. The introduction of the field plate will reduce the original electric field spike, but there will be a new electric field spike at the end of the field plate. For high-voltage semiconductor devices, a single field plate is often difficult to achieve an ideal electric field distribution. Generally, high-voltage semiconductor devices have a multi-level field plate structure for modulating the electric field distribution. Using this method, each layer of field plate from the gate to the drain will further modulate the electric field spike generated by the previous field plate. By adjusting the length and height of each level of field plate, an optimized electric field distribution is obtained to achieve higher voltage resistance and reliability.

[0004] In order to realize multi-layer field plates in semiconductor devices, the existing structure often requires etching of multiple layers of dielectrics and metals and multiple photolithography steps. Moreover, as the number of field plate layers increases, the process cost and time cost will increase significantly. For example, in the current mainstream 650V GaN HEMT chip, 3 to 4 layers of field plates are generally required, and the production of gate and field plate metals requires a total of 4 to 5 photolithography steps, accounting for 20% to 30% of the process cost and time cost of the entire chip tape-out process. Summary of the invention

[0005] The embodiments of the present invention provide a method for manufacturing a semiconductor device with a field plate and a semiconductor device, which simplifies the implementation cost and time of setting a field plate in a semiconductor device.

[0006] An embodiment of the present invention provides a method for manufacturing a semiconductor device having a field plate, comprising: Depositing a first dielectric layer and a second dielectric layer on the epitaxial layer of the substrate, and performing dielectric etching on the second dielectric layer and the first dielectric layer to form source and drain dielectrics; Performing metal deposition and metal etching on the source and drain dielectrics to form the source, drain and first field plate of the semiconductor device, and retaining a gate position between the source and the first field plate; Depositing a third dielectric layer, and performing dielectric etching on the third dielectric layer and the second dielectric layer at the gate position to form a gate dielectric; Metal deposition and metal etching are performed on the gate dielectric to form the gate of the semiconductor device.

[0007] Another aspect of an embodiment of the present invention provides a method for manufacturing a semiconductor device having a field plate, comprising: Depositing a first dielectric layer and a second dielectric layer on the epitaxial layer of the substrate, and performing dielectric etching on the second dielectric layer and the first dielectric layer to form source and drain dielectrics; Performing metal deposition and metal etching on the source and drain dielectrics to form the source, drain and first field plate of the semiconductor device, and retaining a gate position between the source and the first field plate; Depositing a third dielectric layer, performing metal deposition and metal etching on the third dielectric layer to form a second field plate, wherein the second field plate is above the first field plate, and projections of the second field plate and the first field plate in the direction of the substrate have an overlapping area; Depositing a fourth dielectric layer, and performing dielectric etching on the fourth dielectric layer, the third dielectric layer, and the second dielectric layer at the gate position to form a gate dielectric; Metal deposition and metal etching are performed on the gate dielectric to form the gate of the semiconductor device.

[0008] Another aspect of the embodiments of the present invention further provides a semiconductor device, wherein the semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device with a field plate according to one or another aspect of the embodiments of the present invention.

[0009] It can be seen that in the process of manufacturing a semiconductor device with a field plate in this embodiment, the formation of the first layer of field plates in the semiconductor device and the source and drain are concentrated in the same step, so that the formed source, drain and first layer of field plates are on the same layer. This can simplify the manufacturing steps of the semiconductor device, thereby simplifying the implementation cost and time of setting the field plate in the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 is a flow chart of a method for manufacturing a semiconductor device with a field plate provided by an embodiment of the present invention; Figure 2a is a cross-sectional view of a semiconductor device with three-layer field plates in an embodiment of the present invention; Figure 2b is a cross-sectional view of a semiconductor device during metal deposition and metal etching in an embodiment of the present invention; Figure 2c is a schematic diagram of a source electrode, a drain electrode and a first field plate formed after metal deposition and metal etching in an embodiment of the present invention; Figure 3 is a cross-sectional view of another semiconductor device including a three-layer field plate in an embodiment of the present invention; Figure 4 is a cross-sectional view of a semiconductor device including four-layer field plates in an embodiment of the present invention; Figure 5 is a flow chart of another method for manufacturing a semiconductor device with a field plate provided by an embodiment of the present invention; Figure 6 is a cross-sectional view of a semiconductor device with three-layer field plates in an embodiment of the present invention; Figure 7 is a cross-sectional view of another semiconductor device including a three-layer field plate in an embodiment of the present invention; Figure 8 is a cross-sectional view of a semiconductor device including four field plates in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0014] An embodiment of the present invention provides a method for manufacturing a semiconductor device with a field plate, which can be mainly used to manufacture but not limited to semiconductor devices with the following structures, such as MIS-HEMT devices, P-GaN HEMT devices, SBD-Gate HEMT, etc. These semiconductor devices can be made of a variety of semiconductor materials, such as gallium nitride (GaN), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium oxide (GaO), etc. Specifically, Figure 1 As shown, the method for manufacturing the semiconductor device of this embodiment includes: Step 101, depositing a first dielectric layer and a second dielectric layer on the epitaxial layer of the substrate, and performing dielectric etching on the second dielectric layer and the first dielectric layer to form source and drain dielectrics.

[0015] Generally speaking, in the process of manufacturing semiconductor devices, the various parts of the semiconductor device, including the source, gate, drain, field plate, etc., are set on the epitaxial layer of the substrate to obtain the semiconductor device. Among them, the epitaxial layer is a new semiconductor layer grown on the substrate, which can improve the performance of the device, increase the conductivity or enhance the control of impurities; the source, gate, drain and field plate are all metal parts. By setting the field plate, the electric field between the electrodes can be optimized to make the electric field evenly distributed and improve the reliability of the semiconductor device.

[0016] When manufacturing the semiconductor device in this embodiment, a multi-layer process is required on the epitaxial layer of the substrate to form the final semiconductor device. First, a first dielectric layer and a second dielectric layer need to be deposited on the epitaxial layer of the substrate. The first dielectric layer and the second dielectric layer mainly play the role of insulation and isolation. Furthermore, when the semiconductor device includes a source and a drain, it is necessary to perform dielectric etching on the second dielectric layer and the first dielectric layer to form a source-drain dielectric, so that the source and drain formed later are in the same layer.

[0017] Among them, dielectric etching is mainly a process of selectively removing unnecessary materials from the surface of the wafer (specifically the first layer of dielectric and the second layer of dielectric in this embodiment). This process can be achieved through a variety of methods, including physical means (such as ion milling etching) and chemical means (such as plasma etching). During the dielectric etching process, a mask is used to protect the material that needs to be retained, and the exposed material is removed.

[0018] In this embodiment, the source and the gate in the semiconductor device are arranged in different layers, that is, the depths of the source and the gate are different, which can effectively prevent the short circuit between the source and the gate. In order to facilitate the layering of the source and the gate, it is necessary to set a first layer of dielectric and a second layer of dielectric on the epitaxial layer. When the second layer of dielectric and the first layer of dielectric are subjected to dielectric etching to form the source and drain dielectrics, it is necessary to etch through the second layer of dielectric and the first layer of dielectric to expose the epitaxial layer of the source region and the drain region; when dielectric etching is subsequently performed to form the gate dielectric, it is not necessary to etch through the first layer of dielectric, but only to etch through the second layer of dielectric to expose the first layer of dielectric in the gate region.

[0019] Among them, the manufacturing processes between two adjacent layers of dielectrics can be different, such as the first layer of dielectric and the second layer of dielectric, and the dielectric layer at the lower layer is denser, so that the dielectric etching speed is slower. In this way, when etching to the junction of two adjacent layers of dielectrics, the etching speed will slow down, and the etching depth can be well controlled.

[0020] like Figure 2a The figure shows a cross-sectional schematic diagram of a semiconductor device, in which the parts provided on the epitaxial layer 11 of the substrate 10 include: a source 110, a gate 111, a drain 112, and a multi-layer field plate (three-layer field plates are used as an example in the figure) near the gate 111, wherein the first layer of field plates 1131 in the multi-layer field plates are in the same layer as the source 110 and the drain 112, and the second layer of field plates 1132 are connected to the gate 111. In this embodiment, a first layer of dielectric 12 is deposited on the epitaxial layer 11 of the substrate 10, and then a second layer of dielectric 13 is deposited, and then dielectric etching is performed on the second layer of dielectric 13 and the first layer of dielectric 12 to form source and drain dielectrics, specifically through holes that pass through the second layer of dielectric 13 and the first layer of dielectric 12 and expose the epitaxial layer 11 in the source region and the drain region.

[0021] Step 102, performing metal deposition and metal etching on the source and drain dielectrics to form the source, drain and first field plate of the semiconductor device, and retaining the gate position between the source and the first field plate.

[0022] Specifically, for example Figure 2b As shown, during metal deposition, a metal layer 130 can be deposited on the source and drain dielectric, and then metal etching is performed on the metal layer 130 to form a source 110 (such as an ohmic metal of the source), a drain 112 (such as an ohmic metal of the drain), and a first field plate 1131. The gate position is reserved between the source 110 and the first field plate 1131, and the positions of other multi-layer field plates (such as the second field plate 1132 and the third field plate 1133) are reserved between the drain 112 and the first field plate 1131. In this way, the formation of the source 110, the drain 112, and the first field plate 1131 is concentrated in the same step, which simplifies the steps of setting various parts on the epitaxial layer 11, and the source 110, the drain 112, and the first field plate 1131 are finally formed on the same layer.

[0023] When metal etching is performed, a photoresist 131 may be provided at a position where the metal needs to be retained, and then the metal layer 130 is etched, so that the metal at the position where the photoresist 131 is provided is retained, while the metal at other positions is etched away, and finally the photoresist 131 is removed to form a Figure 2c The source 110, drain 112 and first field plate 1131 are shown. The distance between the source 110 and the first field plate 1131 needs to be large enough to accommodate the gate 111 formed later, and the distance between the first field plate 1131 and the drain 112 also needs to be large enough to accommodate the other field plates formed later.

[0024] Step 103 , depositing a third dielectric layer, and performing dielectric etching on the third dielectric layer and the second dielectric layer at the gate position to form a gate dielectric, wherein the gate position is the position between the source and the first field plate.

[0025] like Figure 2a As shown, after forming the source 110, the drain 112 and the first field plate 1131, the third dielectric layer 14 can be deposited, and then only the third dielectric layer 14 and the second dielectric layer 13 are dielectrically etched at the gate position between the source 110 and the first field plate 1131 to form a gate dielectric. Specifically, when forming the gate dielectric, it is necessary to etch through the third dielectric layer 14 and the second dielectric layer 13 and expose the first dielectric layer 12.

[0026] In this way, by depositing the second dielectric layer 13 on the first dielectric layer 12, the gate 111 and the source 110 finally formed can have different distances from the substrate 10, that is, there is a certain depth difference between the depths of the gate 111 and the source 110, and the source 110 and the first field plate 1131 are in the same layer, so there is a certain depth difference between the depths of the gate 111 and the first field plate 1131.

[0027] Step 104 , performing metal deposition and metal etching on the gate dielectric to form a gate of the semiconductor device, that is, forming a gate 111 on the first dielectric layer 12 in the gate region.

[0028] It should be noted that the method in the above steps 101 to 104 is mainly a method for setting a layer of field plates in a semiconductor device. In other embodiments, multiple layers of field plates, a second layer of field plates, a third layer of field plates and a fourth layer of field plates, etc., may also be set in the semiconductor device. Specifically: (1) When forming the second field plate: Metal deposition and metal etching are performed on the gate dielectric to form a second field plate, wherein the second field plate is above the first field plate, and the projections of the second field plate and the first field plate in the direction of the substrate have an overlapping area, wherein the gate is connected to the second field plate, or the gate is disconnected from the second field plate.

[0029] For example Figure 2a As shown, metal deposition and metal etching are performed on the gate dielectric to simultaneously form the gate 111 and the second field plate 1132, and the gate 111 is connected to the second field plate 1132. In other embodiments, as Figure 3 As shown, the gate 111 and the second field plate 1132 can be disconnected, so that the independent second field plate 1132 can be more flexibly connected to the source 110 or the gate 111 through a subsequent metal interconnection process. The projections of the second field plate 1132 and the first field plate 1131 in the direction of the substrate 10 have an overlapping area.

[0030] (2) When forming the third field plate: A fourth dielectric layer is deposited, and metal deposition and metal etching are performed on the fourth dielectric layer to form a third field plate. The third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the substrate direction have an overlapping area.

[0031] For example Figure 2a As shown, after forming the gate 111 and the second field plate 1132, a fourth dielectric layer 15 can be deposited, and metal deposition and metal etching are performed on the fourth dielectric layer 15 to form a third field plate 1133, and the projections of the third field plate 1133 and the second field plate 1132 in the direction of the substrate 10 have an overlapping area.

[0032] (3) When the fourth field plate is formed: A fifth dielectric layer is deposited, and metal deposition and metal etching are performed on the fifth dielectric layer to form a fourth field plate. The fourth field plate is above the third field plate, and the projections of the fourth field plate and the third field plate in the substrate direction have an overlapping area.

[0033] For example Figure 4 As shown, after forming the third field plate 1133, a fifth dielectric layer 16 can be deposited, and metal deposition and metal etching can be performed on the fifth dielectric layer 16 to form a fourth field plate 1134, and the projections of the fourth field plate 1134 and the third field plate 1133 in the direction of the substrate 10 have an overlapping area.

[0034] It can be seen that in the embodiment of the present invention, in the process of manufacturing the semiconductor device, the formation of the first layer of field plate and the source in the semiconductor device is concentrated in the same step, so that the formed source and the first layer of field plate are on the same layer. This can simplify the manufacturing steps of the semiconductor device, thereby simplifying the implementation cost and time of setting the field plate in the semiconductor device.

[0035] An embodiment of the present invention provides another method for manufacturing a semiconductor device with a field plate, which can be mainly used to manufacture but not limited to semiconductor devices with the following structures, such as MIS-HEMT devices, P-GaN HEMT devices, SBD-GateHEMT, etc. These semiconductor devices can be made of a variety of semiconductor materials, such as GaN, Si, SiC, GaAs, GaO and other semiconductor materials. The method for manufacturing the semiconductor device in this embodiment is similar to the above Figure 1 The manufacturing method shown is similar, except that, in this embodiment, when manufacturing the semiconductor device, after forming the source and the first field plate and before forming the gate, a second field plate needs to be formed.

[0036] Specifically, Figure 5 As shown, the method for manufacturing the semiconductor device of this embodiment includes: Step 201 , depositing a first dielectric layer and a second dielectric layer on the epitaxial layer of the substrate, and performing dielectric etching on the second dielectric layer and the first dielectric layer to form source and drain dielectrics.

[0037] Generally, in the process of manufacturing semiconductor devices, various parts of the semiconductor device, including a source, a gate, a drain, a field plate, etc., are arranged mainly on the epitaxial layer of the substrate to obtain the semiconductor device.

[0038] When manufacturing the semiconductor device in the present embodiment, first, a first dielectric layer and a second dielectric layer need to be deposited on the epitaxial layer of the substrate. Furthermore, when the semiconductor device includes a source and a drain, dielectric etching needs to be performed on the second dielectric layer and the first dielectric layer to form source-drain dielectrics, so that the source and drain to be formed later are in the same layer.

[0039] like Figure 6 The figure shows a cross-sectional schematic diagram of a semiconductor device, in which the parts provided on the epitaxial layer 21 of the substrate 20 include: a source 210, a gate 211, a drain 212, and a multi-layer field plate (three-layer field plates are used as an example in the figure) near the gate 211, wherein the first layer of field plates 2131 in the multi-layer field plates are on the same layer as the source 210 and the drain 212, and the third layer of field plates 2133 are connected to the gate 211. In this embodiment, a first layer of dielectric 22 is deposited on the epitaxial layer 21 of the substrate 20, and then a second layer of dielectric 23 is deposited, and then dielectric etching is performed on the second layer of dielectric 23 and the first layer of dielectric 22 to form source and drain dielectrics, specifically, through holes are etched through the second layer of dielectric 23 and the first layer of dielectric 22, and the epitaxial layer 21 in the source region and the drain region are exposed.

[0040] Step 202, performing metal deposition and metal etching on the source and drain dielectrics to form the source, drain and first field plate of the semiconductor device, and retaining the gate position between the source and the first field plate.

[0041] Specifically, Figure 6 As shown, during metal deposition, a metal layer can be deposited on the source and drain dielectric, and then metal etching is performed on the metal layer to form a source 210 (such as an ohmic metal of the source), a drain 212 (such as an ohmic metal of the drain), and a first field plate 2131. The gate position is reserved between the source 210 and the first field plate 2131, and the positions of other multi-layer field plates (such as the second field plate 2132 and the third field plate 2133) are reserved between the drain 212 and the first field plate 2131. In this way, the formation of the source 210, the drain 212, and the first field plate 2131 is concentrated in the same step, which simplifies the steps of setting various parts on the epitaxial layer 21, and the source 210, the drain 212, and the first field plate 2131 are finally formed on the same layer.

[0042] Step 203, depositing a third dielectric layer, performing metal deposition and metal etching on the third dielectric layer to form a second field plate, wherein the second field plate is above the first field plate, and the projections of the second field plate and the first field plate in the substrate direction have an overlapping area.

[0043] like Figure 6As shown, after the source 210, the drain 212 and the first field plate 2131 are formed, a third dielectric layer 24 can be deposited, and then metal deposition and metal etching are performed on the third dielectric layer 24 to form a second field plate 2132. The second field plate 2132 needs to be above the first field plate 2131, and the projections of the second field plate 2132 and the first field plate 2131 in the direction of the substrate 20 have an overlapping area.

[0044] Step 204, depositing a fourth dielectric layer, and performing dielectric etching on the fourth dielectric layer, the third dielectric layer, and the second dielectric layer at the gate position to form a gate dielectric.

[0045] like Figure 6 As shown, after the second layer field plate 2132 is formed, the fourth layer dielectric 25 can be deposited, and then the fourth layer dielectric 25, the third layer dielectric 24 and the second layer dielectric 23 are dielectrically etched at the gate position between the source 210 and the first layer field plate 2131 to form a gate dielectric. Specifically, when forming the gate dielectric, it is necessary to etch through the fourth layer dielectric 25, the third layer dielectric 24 and the second layer dielectric 23 and expose the first layer dielectric 22.

[0046] Step 205 , performing metal deposition and metal etching on the gate dielectric to form a gate of the semiconductor device, that is, forming a gate 211 on the first dielectric layer 22 in the gate region.

[0047] It should be noted that the method in steps 201 to 205 is mainly a method for setting two layers of field plates in a semiconductor device. In other embodiments, a third layer of field plates and a fourth layer of field plates may also be set in the semiconductor device. Specifically: (1) When forming the third field plate: Metal deposition and metal etching are performed on the gate dielectric to form a third field plate, the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the direction of the substrate have an overlapping area, wherein the gate is connected to the third field plate, or the gate is disconnected from the third field plate.

[0048] For example Figure 6 As shown, metal deposition and metal etching are performed on the gate dielectric to simultaneously form the gate 211 and the third field plate 2133, and the gate 211 is connected to the third field plate 2133. In other embodiments, as Figure 7 As shown, the gate 211 and the third field plate 2133 can be disconnected, so that the independent third field plate 2133 can be more flexibly connected to the source 210 or the gate 211 through a subsequent metal interconnection process. The projections of the third field plate 2133 and the second field plate 2132 in the direction of the substrate 20 have an overlapping area.

[0049] (2) When forming the fourth field plate: A fifth dielectric layer is deposited, and metal deposition and metal etching are performed on the fifth dielectric layer to form a fourth field plate. The fourth field plate is above the third field plate, and the projections of the fourth field plate and the third field plate in the substrate direction have an overlapping area.

[0050] For example Figure 8 As shown, after forming the third field plate 2133, a fifth dielectric layer 26 can be deposited, and metal deposition and metal etching can be performed on the fifth dielectric layer 26 to form a fourth field plate 2134, and the projections of the fourth field plate 2134 and the third field plate 2133 in the direction of the substrate 20 have an overlapping area.

[0051] It can be seen that in the embodiment of the present invention, in the process of manufacturing the semiconductor device, the formation of the first layer of field plate and the source in the semiconductor device is concentrated in the same step, so that the formed source and the first layer of field plate are on the same layer. This can simplify the manufacturing steps of the semiconductor device, thereby simplifying the implementation cost and time of setting the field plate in the semiconductor device.

[0052] The method for manufacturing a semiconductor device in this embodiment is similar to the above Figure 1 Compared with the method for manufacturing a semiconductor device shown in the above Figure 1 When manufacturing semiconductor devices according to the method shown, since only one field plate, namely the first field plate, is formed before forming the gate dielectric, when dielectric etching is performed to form the gate dielectric, the dielectric etching depth required is relatively low, and the dielectric only needs to be etched to penetrate the third dielectric layer 14 and the second dielectric layer 13 and expose the first dielectric layer 12. This can reduce the dielectric etching time and better control the gate morphology, and is generally suitable for chip designs with smaller circuit board sizes.

[0053] An embodiment of the present invention further provides a semiconductor device, which is a semiconductor device manufactured according to the method for manufacturing a semiconductor device with a field plate in the above embodiment.

[0054] The above is a detailed introduction to a method for manufacturing a semiconductor device with a field plate and a semiconductor device provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for manufacturing a semiconductor device having a field plate, It is characterized in that include: Depositing a first dielectric layer and a second dielectric layer on the epitaxial layer of the substrate, and performing dielectric etching on the second dielectric layer and the first dielectric layer to form source and drain dielectrics; Performing metal deposition and metal etching on the source and drain dielectrics to form the source, drain and first field plate of the semiconductor device, and reserving a gate position between the source and the first field plate; Depositing a third dielectric layer, and performing dielectric etching on the third dielectric layer and the second dielectric layer at the gate position to form a gate dielectric; Metal deposition and metal etching are performed on the gate dielectric to form the gate of the semiconductor device.

2. The method according to claim 1, It is characterized in that After performing metal deposition and metal etching on the gate dielectric, the method further comprises: A second field plate is formed; the second field plate is above the first field plate, and the projections of the second field plate and the first field plate in the direction of the substrate have an overlapping area; wherein the gate is connected to the second field plate.

3. The method according to claim 1, It is characterized in that After performing metal deposition and metal etching on the gate dielectric, the method further comprises: A second field plate is formed; the second field plate is above the first field plate, and the projections of the second field plate and the first field plate in the direction of the substrate have an overlapping area; wherein the gate is disconnected from the second field plate.

4. The method according to claim 2 or 3, It is characterized in that The method further comprises: A fourth dielectric layer is deposited, and metal deposition and metal etching are performed on the fourth dielectric layer to form a third field plate, wherein the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the direction of the substrate have an overlapping area.

5. The method according to claim 4, It is characterized in that The method further comprises: A fifth dielectric layer is deposited, and metal deposition and metal etching are performed on the fifth dielectric layer to form a fourth field plate, wherein the fourth field plate is above the third field plate, and the projections of the fourth field plate and the third field plate in the direction of the substrate have an overlapping area.

6. A method for manufacturing a semiconductor device having a field plate, It is characterized in that include: Depositing a first dielectric layer and a second dielectric layer on the epitaxial layer of the substrate, and performing dielectric etching on the second dielectric layer and the first dielectric layer to form source and drain dielectrics; Performing metal deposition and metal etching on the source and drain dielectrics to form the source, drain and first field plate of the semiconductor device, and retaining a gate position between the source and the first field plate; Depositing a third dielectric layer, performing metal deposition and metal etching on the third dielectric layer to form a second field plate, wherein the second field plate is above the first field plate, and projections of the second field plate and the first field plate in the direction of the substrate have an overlapping area; Depositing a fourth dielectric layer, and performing dielectric etching on the fourth dielectric layer, the third dielectric layer, and the second dielectric layer at the gate position to form a gate dielectric; Metal deposition and metal etching are performed on the gate dielectric to form the gate of the semiconductor device.

7. The method according to claim 6, It is characterized in that After performing metal deposition and metal etching on the gate dielectric, the method further comprises: A third field plate is formed; the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the direction of the substrate have an overlapping area; wherein the gate is connected to the third field plate.

8. The method according to claim 6, It is characterized in that After performing metal deposition and metal etching on the gate dielectric, the method further comprises: A third field plate is formed; the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the direction of the substrate have an overlapping area; wherein the gate is disconnected from the third field plate.

9. The method according to claim 7 or 8, It is characterized in that The method further comprises: A fifth dielectric layer is deposited, and metal deposition and metal etching are performed on the fifth dielectric layer to form a fourth field plate, wherein the fourth field plate is above the third field plate, and the projections of the fourth field plate and the third field plate in the direction of the substrate have an overlapping area.

10. A semiconductor device, It is characterized in that The semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device with a field plate according to any one of claims 1 to 9.

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