Reconfigurable chip-to-wafer bonding method and device chip

Abstract

The invention discloses a reconfigurable chip-to-wafer bonding method and a device chip, and the method comprises the steps: carrying out the spin coating of a passivation layer on the surface of a substrate wafer, and enabling the substrate wafer to be a wafer with convex points; then, photoresist is laid on the passivation layer, and a graphical area on the photoresist corresponds to a bonding area of the substrate wafer; the passivation layer is etched, the photoresist on the passivation layer is removed, and a plurality of bonding areas used for chip bonding are formed on the passivation layer; respectively placing each chip in the bonding area, and aligning and bonding pad points of the chips with salient points of the bonding area in a mode of rotating the substrate wafer; and finally, coating isolating layers with different viscosities on the substrate wafer twice, and carrying out curing treatment on the chip. Therefore, the packaging efficiency can be greatly improved, complicated mechanical actions of a machine table are not needed, and a plurality of chips can be aligned and the like in a physical adsorption and rotating centrifugal force separation mode.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a reconfigurable chip-to-wafer bonding method and a device chip. Background Art

[0002] Die to wafer bonding (D2W) refers to the process of tightly bonding a polished chip to a wafer through chemical and physical effects. This technology allows the chip and wafer to be bonded together as a whole through covalent bonds and intermolecular forces, thereby achieving a certain strength and achieving integration. Common methods include welding bonding, gold wire bonding, ball position bonding and other process means.

[0003] Solder bonding is one of the most common chip-to-wafer bonding methods. It uses molten solder balls to connect the metal wires between the chip and the wafer. The process is simple and low-cost, but the welding process has high temperature requirements, which may cause thermal stress or bond wire breakage. Gold wire bonding generally uses metal wires (commonly gold or aluminum) for connection. It is a more traditional method and is also the packaging method for most chips in the industry. However, due to its low packaging efficiency and poor integration, it no longer meets the packaging requirements of high-integration, high-performance chips. Ball-limited bonding uses tiny ball limits to achieve the connection between the chip and the wafer. This method has high connection reliability and high integration, but requires high-precision ball planting equipment and processes, and is relatively expensive.

[0004] But no matter welding bonding, gold wire bonding, or ball position bonding, they are all ways of bonding a single chip to a wafer. Although these bonding methods have certain advantages, they have low production efficiency and high production costs. For example, the ball planting process first requires ball planting equipment for high-density ball planting. Although this BGA (Ball Grid Array) method greatly improves the reliability of bonding and can provide more I / O interfaces compared to wire bonding, it still remains in the integration of discrete chips. In addition, the ball planting equipment is expensive, and there are many mechanical actions to pick up the chip, which will inevitably reduce production efficiency and increase production costs. Welding bonding is a traditional bonding method, which is only suitable for the bonding of traditional chips. It has low production efficiency and low integration, and is not suitable for the packaging of high-performance chips. Summary of the invention

[0005] In view of the above problems, the present invention provides a reconfigurable chip-to-wafer bonding method and device chip, which has high packaging efficiency and does not require complex mechanical movements of the machine. Multiple chips can complete the alignment process through physical adsorption and rotational centrifugal separation.

[0006] According to a first aspect of the present invention, a reconfigurable chip-to-wafer bonding method is provided, comprising:

[0007] Spin-coating a passivation layer on the surface of a substrate wafer, wherein the substrate wafer is a wafer with bumps;

[0008] Applying photoresist on the passivation layer, wherein the patterned area on the photoresist corresponds to the bonding area of ​​the substrate wafer;

[0009] Etching the passivation layer and removing the photoresist on the passivation layer, wherein the passivation layer forms a plurality of bonding areas for chip bonding;

[0010] Placing each chip on the bonding area respectively, and aligning and bonding the pad point of the chip with the bump point of the bonding area by rotating the substrate wafer;

[0011] Isolation layers with different viscosities are coated twice on the substrate wafer, and the chip is cured.

[0012] Optionally, applying isolation layers of different viscosities on the substrate wafer twice and curing the chip comprises:

[0013] Applying a first base material on the substrate wafer as a first isolation layer, and the first base material is used to fill the gap between the chip and the passivation layer;

[0014] A second base material is coated on the first isolation layer of the substrate wafer as a second isolation layer, wherein the viscosity of the first base material is lower than that of the second base material, and the thickness of the second isolation layer is greater than that of the first isolation layer.

[0015] Optionally, the method further includes:

[0016] The passivation layer, the chip and the isolation layer are thinned.

[0017] Optionally, the chip is bonded to the substrate wafer by flip chip method.

[0018] Optionally, before spin coating the passivation layer on the surface of the substrate wafer, the method further comprises:

[0019] The substrate wafer is subjected to a surface activation treatment, wherein the surface activation treatment is a physical activation treatment or a chemical activation treatment.

[0020] Optionally, before placing each chip on the bonding area and aligning and bonding the pad points of the chip with the bumps of the bonding area by rotating the substrate wafer, the method further includes:

[0021] The passivation layer is cleaned and subjected to plasma surface activation treatment.

[0022] Optionally, before placing each chip on the bonding area and aligning and bonding the pad points of the chip with the bumps of the bonding area by rotating the substrate wafer, the method further includes:

[0023] The chip is subjected to plasma surface activation treatment.

[0024] According to a second aspect of the present invention, a device wafer is provided, comprising a substrate wafer and a plurality of chips, wherein the plurality of chips are bonded to the substrate wafer by the aforementioned reconfigurable chip-to-wafer bonding method.

[0025] According to a third aspect of the present invention, a device wafer is provided, comprising a substrate wafer and a plurality of groups of chips of different sizes, wherein each group of chips is bonded to the substrate wafer by the aforementioned reconfigurable chip-to-wafer bonding method.

[0026] The above one or more technical solutions in the embodiments of this specification have at least the following technical effects:

[0027] The embodiment of this specification provides a reconfigurable chip-to-wafer bonding method and device chip, first spin-coating a passivation layer on the surface of a substrate wafer, the substrate wafer being a wafer with bumps; then applying a photoresist on the passivation layer, the patterned area on the photoresist corresponding to the bonding area of ​​the substrate wafer; etching the passivation layer, and removing the photoresist on the passivation layer, the passivation layer forms a plurality of bonding areas for chip bonding; then placing each chip in the bonding area, aligning and bonding the pad point of the chip with the bump of the bonding area by rotating the substrate wafer; finally, applying an isolation layer of different viscosities on the substrate wafer twice, and curing the chip. In this way, the packaging efficiency can be greatly improved, and there is no need for complex mechanical movements of the machine, and multiple chips can be aligned and other processes can be completed by physical adsorption and rotational centrifugal separation.

[0028] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings:

[0030] Figure 1 A flow chart of a reconfigurable chip-to-wafer bonding method in an embodiment of the present invention is shown.

[0031] Figure 2 A schematic diagram of coating a first isolation layer on a substrate wafer in an embodiment of the present invention is shown.

[0032] Figure 3 A schematic diagram of coating a second isolation layer on a substrate wafer in an embodiment of the present invention is shown.

[0033] Figure 4 A schematic diagram of a device wafer in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0037] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] Combination Figure 1 As shown, the present invention provides a reconfigurable chip-to-wafer bonding method, and the reconfigurable chip-to-wafer bonding method includes steps 101 to 105:

[0039] Step 101: spin-coating a passivation layer on the surface of a substrate wafer, wherein the substrate wafer is a wafer with bumps;

[0040] In this embodiment, the substrate wafer refers to a wafer to be bonded with at least one chip, and a plurality of bonding areas are planned on the wafer, and the size and position of the bonding areas are carefully designed to provide positioning information for the chip.

[0041] The substrate wafer may be bonded to the wafer multiple times, each time including at least one chip bonded to the substrate wafer. It should be noted that for each bonding process, the chip size used in the same bonding process is the same.

[0042] Before the substrate wafer is spin-coated with a passivation layer, the substrate wafer needs to be subjected to a surface activation treatment to increase the adsorption of the surface. The surface activation treatment is a physical activation treatment or a chemical activation treatment.

[0043] Since the stability and reliability of semiconductor devices are closely related to the properties of the semiconductor surface, in order to avoid the impact of the environment and other external factors on the device, a protective film needs to be covered on the surface of the wafer. In other words, a passivation layer needs to be spin-coated on the surface of the substrate wafer. The material used for the passivation layer can be SOG (Spin on Glass, glass spin-coated material), BCB (Benzocyclobutene, benzocyclobutene resin), SU8 (U-8 Negative Epoxy Resists), PI glue (Polyimide, polyimide), etc.

[0044] Step 102: applying a photoresist on the passivation layer, wherein the patterned area on the photoresist corresponds to the bonding area of ​​the substrate wafer;

[0045] In this embodiment, the photoresist, also known as photoresist, refers to an etching-resistant thin film material whose solubility changes when exposed to ultraviolet light, electron beam, ion beam, X-ray, etc.

[0046] A certain dose of photoresist is dripped in, and the substrate wafer rotates at a certain speed, and a layer of photoresist of ideal thickness is formed on the surface of the passivation layer. After the photoresist is applied, the substrate wafer is baked to bake out the solvent in the photoresist, so that the adhesion between the photoresist and the passivation layer is better, stronger, and not easy to fall off. Then the mask is aligned with the substrate wafer for exposure, and then developed. After development, the area where the photoresist is etched away forms a patterned area, where the patterned area corresponds to the bonding area designed for the substrate wafer.

[0047] Step 103: etching the passivation layer and removing the photoresist on the passivation layer, so that the passivation layer forms a plurality of bonding areas for chip bonding;

[0048] In this embodiment, the passivation layer exposed from the patterned area of ​​the photoresist is etched, and the etching stops at the substrate wafer, so as to realize opening a window on the passivation layer. It should be noted that the window area is slightly larger than the chip area. The window corresponds to the bonding area of ​​the substrate wafer. The chip will be placed in these areas.

[0049] After etching, the photoresist on the passivation layer will be removed. After stripping, the passivation layer will be cleaned and plasma surface activated to increase the adsorption force of the passivation layer surface.

[0050] It should be noted that, in the photolithography and etching process, offset compensation is added in the calculation of the opening position of the passivation layer.

[0051] Step 104: placing each chip in the bonding area, and aligning and bonding the pad points of the chip with the bumps of the bonding area by rotating the substrate wafer;

[0052] In this embodiment, there are multiple chips to be bonded, and each chip has a corresponding bonding area on the substrate wafer.

[0053] Before placing the chip in the bonding area, the chip will be pre-treated, that is, the chip will be plasma-activated by liquid medicine to improve the adsorption capacity of the chip's pad point and the substrate wafer. The pad point refers to the pin pad on the chip. The liquid medicine used is mainly to improve the affinity between the chip and the substrate bonding area, for example, the selective adsorbent, DuPont Rohm and Haas I RC747.

[0054] After the chip is pre-processed, the chip is bonded to the substrate wafer in the FC (Flip-Chip, flip chip technology) manner. That is, each chip is placed in the corresponding bonding area, and the substrate wafer is rotated to increase mechanical movement by centrifugal force, and the physical adsorption between the chip and the substrate wafer is used to achieve contact between the pad point of the flip chip and the bump of the substrate wafer. After alignment, pressure and heat are applied to achieve bonding of the chip to the substrate wafer. This embodiment achieves large-scale and efficient chip-to-wafer bonding by adopting a rotation and physical adsorption pre-processing method.

[0055] Step 105: coating isolation layers of different viscosities on the substrate wafer twice, and curing the chip.

[0056] In this embodiment, the isolation layer is not directly spin-coated, mainly considering the wetting of the isolation layer material and the substrate wafer. Generally, materials with high viscosity are difficult to penetrate into the nano-scale gap. Therefore, this embodiment adopts a dilution treatment method, first pre-filling, and then curing treatment to achieve a certain structural strength and fix the position of the chip. Then, the second base material with higher viscosity is applied again and cured. After curing, the passivation layer, chip and isolation layer are thinned.

[0057] Specifically, combined with Figure 2 , Figure 3 As shown, the first base material is first coated on the substrate wafer as the first isolation layer. The first base material is used to coat the surface of the passivation layer and to fill the gap between the chip and the passivation layer. The first base material has low viscosity, good fluidity, and strong filling ability, and is used to initially fix the chip position.

[0058] Then, a second base material is coated on the first isolation layer of the substrate wafer as a second isolation layer. It should be noted that the viscosity of the first base material is lower than that of the second base material, and the thickness of the second isolation layer is greater than that of the first isolation layer.

[0059] The first matrix material and the second matrix material may be the same material, and the second matrix material may be added with a diluent to obtain the first matrix material. For example, the first matrix material may be obtained by diluting PI glue with acetone.

[0060] In summary, the embodiment of this specification provides a reconfigurable chip-to-wafer bonding method and device chip, first spin-coating a passivation layer on the surface of a substrate wafer, the substrate wafer being a wafer with bumps; then applying a photoresist on the passivation layer, the patterned area on the photoresist corresponding to the bonding area of ​​the substrate wafer; etching the passivation layer, and removing the photoresist on the passivation layer, the passivation layer forms a plurality of bonding areas for chip bonding; then placing each chip in the bonding area, aligning and bonding the pad point of the chip with the bump of the bonding area by rotating the substrate wafer; finally, applying an isolation layer of different viscosities on the substrate wafer twice, and curing the chip. In this way, the packaging efficiency can be greatly improved, and there is no need for complex mechanical movements of the machine, and multiple chips can be aligned and other processes can be completed by physical adsorption and rotation centrifugal separation. The present invention is suitable for the field of heterogeneous heterogeneous integration, large-scale chip-to-wafer integration, and can improve production efficiency and reduce machine costs.

[0061] Based on the same inventive concept, an embodiment of the present invention further provides a device wafer, the device wafer comprising a substrate wafer and a plurality of chips, the plurality of chips being bonded to the substrate wafer by the aforementioned reconfigurable chip-to-wafer bonding method. It should be noted that the above chips are chips of the same size.

[0062] In summary, a device chip provided in an embodiment of the present specification first spin-coats a passivation layer on the surface of a substrate wafer, the substrate wafer being a wafer with bumps; then applies a photoresist on the passivation layer, the patterned area on the photoresist corresponds to the bonding area of ​​the substrate wafer; etches the passivation layer, and removes the photoresist on the passivation layer, the passivation layer forms a plurality of bonding areas for chip bonding; then, each chip is placed in the bonding area, and the pad point of the chip is aligned and bonded with the bumps of the bonding area by rotating the substrate wafer; finally, an isolation layer of different viscosities is applied twice on the substrate wafer, and the chip is cured. In this way, the packaging efficiency can be greatly improved, and there is no need for complex mechanical movements of the machine, and multiple chips can be aligned and other processes can be completed by physical adsorption and separation by rotating centrifugal force.

[0063] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific bonding method of the device wafer described above can refer to the corresponding process in the aforementioned method, and will not be described in detail here.

[0064] Based on the same inventive concept, Figure 4 As shown, an embodiment of the present invention further provides a device wafer, which includes a substrate wafer and multiple groups of chips of different sizes (for example, 3 groups of chips in the figure, each group of chips is chip A, chip B and chip C, and the sizes of chips A, chip B and chip C are different). For each group of chips, the group of chips is bonded to the substrate wafer according to a preset process sequence through the aforementioned reconfigurable chip-to-wafer bonding method.

[0065] It should be noted that the chip size of each group of chips is the same. However, the chip size may be different between different groups. When bonding different groups of chips to the substrate wafer, each group of chips can be bonded to the substrate wafer repeatedly according to the preset process sequence and the aforementioned method.

[0066] In summary, a device chip provided in an embodiment of the present specification first spin-coats a passivation layer on the surface of a substrate wafer, the substrate wafer being a wafer with bumps; then applies a photoresist on the passivation layer, the patterned area on the photoresist corresponds to the bonding area of ​​the substrate wafer; etches the passivation layer, and removes the photoresist on the passivation layer, the passivation layer forms a plurality of bonding areas for chip bonding; then, each chip is placed in the bonding area, and the pad point of the chip is aligned and bonded with the bumps of the bonding area by rotating the substrate wafer; finally, an isolation layer of different viscosities is applied twice on the substrate wafer, and the chip is cured. In this way, the packaging efficiency can be greatly improved, and there is no need for complex mechanical movements of the machine, and multiple chips can be aligned and other processes can be completed by physical adsorption and separation by rotating centrifugal force.

[0067] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific bonding method of the device wafer described above can refer to the corresponding process in the aforementioned method, and will not be described in detail here.

[0068] The above are only various embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A reconfigurable chip-to-wafer bonding method, It is characterized in that include: Spin-coating a passivation layer on the surface of a substrate wafer, wherein the substrate wafer is a wafer with bumps; Applying photoresist on the passivation layer, wherein the patterned area on the photoresist corresponds to the bonding area of ​​the substrate wafer; Etching the passivation layer and removing the photoresist on the passivation layer, wherein the passivation layer forms a plurality of bonding areas for chip bonding; Placing each chip on the bonding area respectively, and aligning and bonding the pad point of the chip with the bump point of the bonding area by rotating the substrate wafer; Isolation layers with different viscosities are coated twice on the substrate wafer, and the chip is cured.

2. The method according to claim 1, It is characterized in that The step of coating the isolation layers with different viscosities on the substrate wafer twice and curing the chip comprises: Applying a first base material on the substrate wafer as a first isolation layer, and the first base material is used to fill the gap between the chip and the passivation layer; A second base material is coated on the first isolation layer of the substrate wafer as a second isolation layer, wherein the viscosity of the first base material is lower than that of the second base material, and the thickness of the second isolation layer is greater than that of the first isolation layer.

3. The method according to claim 1, It is characterized in that The method further comprises: The passivation layer, the chip and the isolation layer are thinned.

4. The method according to claim 1, It is characterized in that The chip is bonded to the substrate wafer in a flip chip manner.

5. The method according to claim 1, It is characterized in that Before spin coating the passivation layer on the surface of the substrate wafer, the method further comprises: The substrate wafer is subjected to a surface activation treatment, wherein the surface activation treatment is a physical activation treatment or a chemical activation treatment.

6. The method according to claim 1, It is characterized in that After etching the passivation layer and removing the photoresist on the passivation layer, the method further comprises: The passivation layer is cleaned and subjected to plasma surface activation treatment.

7. The method according to claim 1, It is characterized in that Before placing each chip on the bonding area and aligning and bonding the pad points of the chip with the bumps of the bonding area by rotating the substrate wafer, the method further includes: The chip is subjected to plasma surface activation treatment.

8. The method according to claim 1, It is characterized in that The material of the passivation layer is SOG or BCB or SU8 or PI glue.

9. A device wafer, It is characterized in that The device wafer comprises a substrate wafer and a plurality of chips, wherein the plurality of chips are bonded to the substrate wafer by the reconfigurable chip-to-wafer bonding method according to any one of claims 1 to 7.

10. A device wafer, It is characterized in that The device wafer includes a substrate wafer and multiple groups of chips of different sizes. For each group of chips, the group of chips is bonded to the substrate wafer according to a preset process sequence through the reconfigurable chip-to-wafer bonding method described in any one of claims 1-7.

Images