Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a semiconductor substrate which is provided with one or more grooves; a single-layer silicon seed crystal layer or a laminated structure of multiple silicon seed crystal layers is formed on the inner wall of each groove, and each silicon seed crystal layer has respective silicon seed crystal layer surface roughness; forming a polycrystalline silicon layer on the single-layer silicon seed crystal layer or the laminated structure so as to fill the groove; wherein the surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove. According to the invention, the surface roughness of the polycrystalline silicon layer can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In the semiconductor manufacturing process, polysilicon is often used to fill trenches (such as channels or deep holes). Specifically, polysilicon is essentially a semiconductor, and its work function can be changed by doping impurities of different polarities, thereby changing the electrical parameters of the transistor, such as the critical voltage of the transistor. In addition, in the semiconductor manufacturing process, annealing and other processes are often used to improve device characteristics, and semiconductors can withstand high temperatures during annealing due to their high melting points. The above characteristics make polysilicon widely used in small and medium-scale integrated circuits.

[0003] With the development of semiconductor technology, the characteristic size of semiconductor devices is getting smaller and smaller, and the integration of integrated circuits is getting higher and higher. When filling trenches with high aspect ratios with polysilicon, gaps are prone to appear, forming defects in subsequent processes, and in severe cases causing yield loss.

[0004] There is an urgent need for a method for forming a semiconductor structure that can alleviate the molecular agglomeration problem of the polysilicon layer and reduce the surface roughness of the polysilicon layer, thereby improving the trench filling effect. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce the surface roughness of a polysilicon layer.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate, the semiconductor substrate having one or more grooves; forming a single-layer silicon seed crystal layer or a stacked structure of multiple silicon seed crystal layers on the inner wall of each groove, wherein each silicon seed crystal layer has its own silicon seed crystal layer surface roughness; forming a polycrystalline silicon layer on the single-layer silicon seed crystal layer or the stacked structure to fill the groove; wherein the surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove.

[0007] Optionally, the surface roughness includes one or more of the following: surface average roughness Ra; surface root mean square roughness Rq; the surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove, including: the surface average roughness of each silicon seed crystal layer is smaller than the surface average roughness Ra_0 of the inner wall of the groove; and / or the surface root mean square roughness of each silicon seed crystal layer is smaller than the surface root mean square roughness Rq_0 of the inner wall of the groove.

[0008] Optionally, the silicon source material used to form the polysilicon layer includes monosilane.

[0009] Optionally, the process parameters for forming the polysilicon layer using the monosilane as the silicon source include one or more of the following: the process temperature is selected from: 500°C to 680°C; the thickness of the polysilicon layer is selected from: 1000A to 8000A; the surface roughness of the polysilicon layer includes one or more of the following: 0.3nm <Ra_p,0.3nm<Rq_p。

[0010] Optionally, a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each groove; wherein, from the bottom to the top of the semiconductor substrate, the surface roughness of each silicon seed crystal layer of the stacked structure increases layer by layer.

[0011] Optionally, the silicon source material for forming the bottom silicon seed layer of the stacked structure includes diisopropylaminosilane; and / or the silicon source material for forming the top silicon seed layer of the stacked structure includes disilane.

[0012] Optionally, the process parameters for forming the bottom silicon seed crystal layer using the diisopropylaminosilane as the silicon source include one or more of the following: the process temperature is selected from: 350° C. to 420° C.; the gas atmosphere is a nitrogen atmosphere; the chamber pressure of the process chamber is selected from: 0.4 Torr to 0.6 Torr; the surface roughness of the bottom silicon seed crystal layer includes one or more of the following: 0 <Ra_1<0.1nm,0<Rq_1<0.1nm。

[0013] Optionally, when the diisopropylaminosilane is used as the silicon source to form the underlying silicon seed crystal layer, the thickness of the underlying silicon seed crystal layer is determined according to the surface average roughness Ra_0 and / or the surface root mean square roughness Rq_0 of the inner wall of the groove; the larger the surface average roughness Ra_0 of the inner wall of the groove, the thicker the underlying silicon seed crystal layer; and / or, the larger the surface root mean square roughness Rq_0 of the inner wall of the groove, the thicker the underlying silicon seed crystal layer.

[0014] Optionally, the thickness of the underlying silicon seed crystal layer is a first preset multiple of the surface average roughness Ra_0 of the inner wall of the groove; or, the thickness of the underlying silicon seed crystal layer is a second preset multiple of the surface root mean square roughness Rq_0 of the inner wall of the groove; or, the thickness of the underlying silicon seed crystal layer is a third preset multiple of the weighted calculated value of the surface average roughness Ra_0 of the inner wall of the groove and the surface root mean square roughness Rq_0 of the inner wall of the groove.

[0015] Optionally, one or more of the first preset multiple, the second preset multiple and the third preset multiple are selected from: [2,100].

[0016] Optionally, the process parameters for forming the top silicon seed layer using the disilane as the silicon source include one or more of the following: the process temperature is selected from: 350°C to 420°C; the gas atmosphere is a nitrogen atmosphere; the chamber pressure of the process chamber is selected from: 0.6 Torr to 1.0 Torr; the surface roughness of the top silicon seed layer includes one or more of the following: 0.2 nm <Ra_3<0.3nm,0.2nm<Rq_3<0.3nm。

[0017] Optionally, the number of silicon seed crystal layers included in the stacked structure is greater than or equal to 3; wherein the silicon source material used to form the middle silicon seed crystal layer of the stacked structure includes bis(diethylamino)silane.

[0018] Optionally, the process parameters for forming the intermediate silicon seed layer using the bis(diethylamino)silane as the silicon source include one or more of the following: the process temperature is selected from: 350°C to 420°C; the gas atmosphere is a nitrogen atmosphere; the chamber pressure of the process chamber is selected from: 0.4 Torr to 0.6 Torr; the surface roughness of the intermediate silicon seed layer includes one or more of the following: 0.1 nm <Ra_2<0.2nm,0.1nm<Rq_2<0.2nm。

[0019] Optionally, a depth-to-width ratio of part or all of the grooves is greater than 1.5:1.

[0020] Optionally, the thickness of the single-layer silicon seed crystal layer is 1 / 100 to 1 / 5 of the standard depth of the trench; or, the thickness of the stacked structure is 1 / 100 to 1 / 5 of the standard depth of the trench.

[0021] Optionally, the step coverage of each silicon seed crystal layer is greater than or equal to 90%.

[0022] Optionally, the semiconductor base comprises: a semiconductor substrate having a plurality of fins; wherein the trench is formed between adjacent fins.

[0023] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate having one or more grooves; a single-layer silicon seed crystal layer or a stacked structure of multiple silicon seed crystal layers, formed on the inner wall of each groove, wherein each silicon seed crystal layer has its own silicon seed crystal layer surface roughness; a polycrystalline silicon layer, formed on the silicon seed crystal layer, and the polycrystalline silicon layer is used to fill the groove; wherein the surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove.

[0024] Optionally, the silicon source material used to form the polysilicon layer includes monosilane.

[0025] Optionally, the polysilicon layer formed by using the monosilane as the silicon source includes one or more of the following: the thickness of the polysilicon layer is selected from: 1000A to 8000A; the surface roughness of the polysilicon layer includes one or more of the following: 0.3nm <Ra_p,0.3nm<Rq_p。

[0026] Optionally, a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each groove; wherein, from the bottom to the top of the semiconductor substrate, the surface roughness of each silicon seed crystal layer of the stacked structure increases layer by layer.

[0027] Optionally, the silicon source material for forming the bottom silicon seed layer of the stacked structure includes diisopropylaminosilane; and / or the silicon source material for forming the top silicon seed layer of the stacked structure includes disilane.

[0028] Optionally, the surface roughness of the bottom silicon seed crystal layer formed by using the diisopropylaminosilane as the silicon source includes one or more of the following: <Ra_1<0.1nm,0<Rq_1<0.1nm。

[0029] Optionally, the surface roughness of the top silicon seed layer formed by using the disilane as the silicon source includes one or more of the following: 0.2 nm <Ra_3<0.3nm,0.2nm<Rq_3<0.3nm。

[0030] Optionally, the number of silicon seed crystal layers included in the stacked structure is greater than or equal to 3; wherein the silicon source material used to form the middle silicon seed crystal layer of the stacked structure includes bis(diethylamino)silane.

[0031] Optionally, the surface roughness of the intermediate silicon seed layer formed by using the bis(diethylamino)silane as the silicon source includes one or more of the following: 0.1 nm <Ra_2<0.2nm,0.1nm<Rq_2<0.2nm。

[0032] Optionally, a depth-to-width ratio of part or all of the grooves is greater than 1.5:1.

[0033] Optionally, the thickness of the single-layer silicon seed crystal layer is 1 / 100 to 1 / 5 of the standard depth of the trench; or, the thickness of the stacked structure is 1 / 100 to 1 / 5 of the standard depth of the trench.

[0034] Optionally, the step coverage of each silicon seed crystal layer is greater than or equal to 90%.

[0035] Optionally, the semiconductor base may include: a semiconductor substrate having a plurality of fins; wherein the trench is formed between adjacent fins.

[0036] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0037] In an embodiment of the present invention, a single-layer silicon seed crystal layer or a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each groove, and a polysilicon layer is formed on the single-layer silicon seed crystal layer or the stacked structure to fill the groove, wherein the surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove. Before forming the polysilicon layer, a single-layer or multi-layer silicon seed crystal layer with less molecular agglomeration and smaller surface roughness is formed first, and then a polysilicon layer is formed on the single-layer or multi-layer silicon seed crystal layer. This can provide a smoother and denser foundation for the polysilicon layer, effectively alleviate the molecular agglomeration problem of the polysilicon layer, and reduce the surface roughness of the polysilicon layer, thereby reducing the possibility of gaps in the trench filling process and effectively improving the filling effect.

[0038] Furthermore, a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each groove; wherein, from the bottom to the top of the semiconductor substrate, the surface roughness of each silicon seed crystal layer of the stacked structure increases layer by layer. By adopting the above scheme, by forming each silicon seed crystal layer with a step-by-step change in surface roughness, a step-by-step improved density can be obtained, and a better balance can be obtained between production cost and roughness improvement.

[0039] Furthermore, the silicon source material for forming the bottom silicon seed layer of the stacked structure includes diisopropylaminosilane; and / or, the silicon source material for forming the top silicon seed layer of the stacked structure includes disilane, so that diisopropylaminosilane with a higher production cost and disilane with a lower production cost can be used to form a stacked structure with a step-by-step decrease in surface roughness and a step-by-step increase in smoothness and density, thereby providing a better foundation for the subsequent polycrystalline silicon layer, further alleviating the molecular agglomeration problem of the polycrystalline silicon layer, reducing the surface roughness of the polycrystalline silicon layer, and controlling the production cost as much as possible.

[0040] Further, the thickness of the bottom silicon seed crystal layer is determined according to the surface average roughness Ra_0 and / or the surface root mean square roughness Rq_0 of the inner wall of the groove; the greater the surface average roughness Ra_0 of the inner wall of the groove, the greater the thickness of the bottom silicon seed crystal layer; and / or, the greater the surface root mean square roughness Rq_0 of the inner wall of the groove, the greater the thickness of the bottom silicon seed crystal layer. By adopting the above scheme, a thicker bottom silicon seed crystal layer can be formed when the surface roughness of the inner wall of the groove is large, so that the bottom silicon seed crystal layer with the highest smoothness and density can be used to compensate the groove to a greater extent.

[0041] Further, the thickness of the bottom silicon seed crystal layer is a first preset multiple of the surface average roughness Ra_0 of the inner wall of the groove; or, the thickness of the bottom silicon seed crystal layer is a second preset multiple of the surface root mean square roughness Rq_0 of the inner wall of the groove; or, the thickness of the bottom silicon seed crystal layer is a third preset multiple of the weighted calculation value of the surface average roughness Ra_0 of the inner wall of the groove and the surface root mean square roughness Rq_0 of the inner wall of the groove. By adopting the above scheme, a more accurate thickness of the bottom silicon seed crystal layer that is more suitable for filling the current groove can be obtained by setting an appropriate ratio.

[0042] Furthermore, one or more of the first preset multiple, the second preset multiple and the third preset multiple are selected from: [2, 100], so that a value between doubling (such as 2 times) and increasing by two orders of magnitude (such as 100 times) can be used as a ratio. When the surface roughness of the inner wall of the groove is greater, a thicker bottom silicon seed crystal layer is formed. On the basis of using the bottom silicon seed crystal layer to compensate the groove to a greater extent, the process cost of the bottom silicon seed crystal layer is further controlled.

[0043] Furthermore, the number of silicon seed crystal layers included in the stacked structure is greater than or equal to 3; wherein the silicon source material used to form the middle silicon seed crystal layer of the stacked structure includes bis(diethylaminosilane). Thus, the silicon seed crystal layer formed by using bis(diethylaminosilane) as the silicon source can be used as a transition layer, and the stability between the seed crystal layers can be improved in the process of forming a stacked structure with a step-wise decrease in surface roughness and a step-wise increase in smoothness and density.

[0044] Furthermore, the aspect ratio of part or all of the trench is greater than 1.5: 1. Therefore, when part or all of the trench has a high aspect ratio and is more prone to filling gaps, by adopting the embodiment of the present invention, a smoother and denser foundation can be provided for the polysilicon layer, effectively alleviating the molecular agglomeration problem of the polysilicon layer, and reducing the surface roughness of the polysilicon layer, thereby reducing the possibility of gaps in the trench filling process and effectively improving the filling effect.

[0045] Furthermore, the thickness of the single-layer silicon seed crystal layer is 1 / 100 to 1 / 5 of the standard depth of the groove; or, the thickness of the stacked structure is 1 / 100 to 1 / 5 of the standard depth of the groove. By setting an appropriate total thickness, better filling effect can be obtained while further controlling production costs.

[0046] Furthermore, the step coverage of each silicon seed crystal layer is greater than or equal to 90%, so that during the trench filling process, the coverage of the top corner of the trench can be improved, further reducing the possibility of gaps and improving the filling effect.

[0047] Furthermore, the semiconductor base includes: a semiconductor substrate having a plurality of fins; wherein the grooves are formed between adjacent fins. Since semiconductor structures having fins often have the characteristics of small size, high device density, and more prone to filling defects, the device effect of the semiconductor structure having fins can be better improved by improving the filling effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic cross-sectional structure diagram of a semiconductor structure in the prior art;

[0049] Figure 2 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present invention;

[0050] Figures 3 to 7 is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention;

[0051] Figure 8 1 is a schematic diagram comparing the surface roughness obtained after forming polysilicon layers on various surfaces respectively in an embodiment of the present invention.

[0052] Description of reference numerals:

[0053] Semiconductor substrate 100 , trench 111 , gap 112 , polysilicon layer 120 , semiconductor substrate 200 , fin 201 , trench 211 , bottom silicon seed layer 221 , middle silicon seed layer 222 , top silicon seed layer 223 , polysilicon layer 230 . DETAILED DESCRIPTION

[0054] As mentioned above, with the development of semiconductor technology, the feature size of semiconductor devices is getting smaller and smaller, and the integration of integrated circuits is getting higher and higher. When filling trenches with high aspect ratios with polysilicon, gaps are prone to appear, forming defects in subsequent processes, and in severe cases causing yield loss.

[0055] After research, it was found that in the prior art, the polysilicon layer is formed by decomposing an appropriate silicon source material at a high temperature. Since molecules are easily agglomerated during decomposition, the surface roughness is relatively large. In addition, due to the large surface roughness, gaps are easily formed during the gap filling process when filling holes with a high aspect ratio.

[0056] Reference Figure 1 , Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure in the prior art.

[0057] exist Figure 1The semiconductor structure shown may include a semiconductor substrate 100 , wherein the semiconductor substrate 100 has a trench 111 , and a polysilicon layer 120 is formed on the semiconductor substrate 100 . The polysilicon layer 120 fills the trench 111 and forms a gap 112 .

[0058] Further research has found that in the process of forming the polysilicon layer 120 to fill the trench 111, the silicon source material is prone to molecular agglomeration when decomposing at high temperature, resulting in a relatively rough surface of the polysilicon layer 120. Since the molecular agglomeration and the rough surface are formed in the trench, it is difficult to improve them by using processes such as planarization, and there is currently no better solution.

[0059] In an embodiment of the present invention, a single-layer silicon seed crystal layer or a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each groove, and a polysilicon layer is formed on the single-layer silicon seed crystal layer or the stacked structure to fill the groove, wherein the surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the polysilicon layer. Before forming the polysilicon layer, a single-layer or multi-layer silicon seed crystal layer with less molecular agglomeration and smaller surface roughness is formed first, and then a polysilicon layer is formed on the single-layer or multi-layer silicon seed crystal layer. This can effectively alleviate the molecular agglomeration problem of the polysilicon layer and reduce the surface roughness of the polysilicon layer, thereby reducing the possibility of gaps in the trench filling process and effectively improving the filling effect.

[0060] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0061] Reference Figure 2 , Figure 2 1 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present invention. The method for forming a semiconductor structure may include steps S21 to S23:

[0062] Step S21: providing a semiconductor substrate, wherein the semiconductor substrate has one or more grooves;

[0063] Step S22: forming a single silicon seed crystal layer or a stacked structure of multiple silicon seed crystal layers on the inner wall of each groove, wherein each silicon seed crystal layer has its own silicon seed crystal layer surface roughness;

[0064] Step S23: forming a polysilicon layer on the single-layer silicon seed crystal layer or the stacked structure to fill the trench.

[0065] The surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove.

[0066] Combine the following Figures 3 to 7 Each of the above steps is described below.

[0067] Figures 3 to 7 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0068] Reference Figure 3 , a semiconductor substrate 200 is provided, and the semiconductor substrate 200 may have one or more trenches 211.

[0069] In some embodiments, the semiconductor body 200 may include a semiconductor substrate.

[0070] Among them, the semiconductor substrate can be, for example, a silicon substrate. The material of the semiconductor substrate can also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate can also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate with an epitaxial layer (Epi layer) grown on it.

[0071] Furthermore, the semiconductor substrate may have a plurality of fins 201 , wherein the trench 211 may be formed between adjacent fins 201 .

[0072] In a specific embodiment, the step of forming the fin 201 may include: etching the semiconductor substrate to obtain a plurality of sub-fins protruding from the surface of the semiconductor substrate; forming a sacrificial layer covering the surface of the semiconductor substrate, wherein the surface of the sacrificial layer is flush with the top surface of the sub-fin; removing a portion of the thickness of the sub-fin to form a groove, and the remaining sub-fin serves as the fin 201; and then removing the sacrificial layer.

[0073] It is understandable that, in the embodiment of the present invention, the fins 201 may be formed in other appropriate ways, such as etching the semiconductor substrate to obtain a plurality of fins 201 protruding from the surface of the semiconductor substrate.

[0074] It should be noted that in the embodiment of the present invention, it is not limited to using a semiconductor substrate with a fin 201 as a semiconductor base, and a conventional semiconductor substrate can also be used to form a semiconductor structure including other structures, such as forming a complementary metal oxide semiconductor (CMOS) device.

[0075] In an embodiment of the present invention, the semiconductor base 200 may include: a semiconductor substrate having a plurality of fins 201; wherein the grooves 211 are formed between adjacent fins 201. Since the semiconductor structure having the fins 201 often has the characteristics of small size, high device density, and more prone to filling defects, the device effect of the semiconductor structure having the fins 201 can be better improved by improving the filling effect.

[0076] Then, a single silicon seed layer or a stacked structure of multiple silicon seed layers may be formed on the inner wall of each groove 211 , wherein each silicon seed layer may have its own silicon seed layer surface roughness, and each silicon seed layer surface roughness may be smaller than the inner wall surface roughness of the groove 211 .

[0077] In a specific implementation of an embodiment of the present invention, the surface roughness may include one or more of the following: surface average roughness Ra; surface root mean square roughness Rq; the surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove 211, which may include: the surface average roughness of each silicon seed crystal layer is smaller than the surface average roughness Ra_0 of the inner wall of the groove 211; and / or the surface root mean square roughness of each silicon seed crystal layer is smaller than the surface root mean square roughness Rq_0 of the inner wall of the groove 211.

[0078] In the embodiment of the present invention, by selecting appropriate parameters to represent the surface roughness, the surface roughness of the inner wall of the groove 211 and the surface roughness of each silicon seed crystal layer can be accurately compared, which helps to determine appropriate process targets to improve the performance of the formed semiconductor structure.

[0079] In the case of a larger diameter, a thicker bottom silicon seed layer is formed, so that the bottom silicon seed layer with the highest smoothness and density can be used to compensate the trench to a greater extent.

[0080] In some embodiments, a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each trench 211 .

[0081] It can be understood that the inner wall of the groove 211 may include a bottom surface and a side wall surface of the groove 211 .

[0082] Reference Figure 4 , a bottom silicon seed crystal layer 221 is formed on the inner wall of each trench 211 .

[0083] In some embodiments, the silicon source material used to form the bottom silicon seed layer 221 of the stacked structure may include diisopropylaminosilane.

[0084] Among them, diisopropylaminosilane can also be called LTO520, and its chemical formula can be expressed as C6H 17 NSi.

[0085] In a specific implementation, the chemical formula for forming the bottom silicon seed layer 221 using the diisopropylaminosilane as a silicon source can be expressed as follows:

[0086] C6H 17 NSi→Si+3C2H4+NH3+H2;

[0087] Furthermore, the process parameters for forming the bottom silicon seed layer 221 using the diisopropylaminosilane as a silicon source may include one or more of the following:

[0088] The process temperature is selected from: 350°C to 420°C;

[0089] The gas atmosphere is nitrogen atmosphere;

[0090] The chamber pressure of the process chamber is selected from: 0.4 Torr to 0.6 Torr;

[0091] The surface roughness of the bottom silicon seed crystal layer 221 includes one or more of the following: <Ra_1<0.1nm,0<Rq_1<0.1nm。

[0092] Here, Ra_1 is used to represent the Ra of the bottom silicon seed crystal layer 221 , and Rq_1 is used to represent the Rq of the bottom silicon seed crystal layer 221 .

[0093] In a specific embodiment, a vertical furnace polysilicon growth process may be used to form the bottom silicon seed crystal layer 221 in a furnace tube process chamber, thereby increasing the number of wafers accommodated in a single process and effectively improving process efficiency.

[0094] Further, the process temperature in the process chamber may be selected from: 350° C. to 420° C., such as 370° C. to 390° C., for example, 380° C.

[0095] Furthermore, the gas atmosphere in the process chamber may be a nitrogen atmosphere. Since nitrogen is a neutral gas, in an embodiment of the present invention, nitrogen may be used as a protective medium in an inactive state to improve the hardness and wear resistance of the underlying silicon seed crystal layer 221 .

[0096] Furthermore, the chamber pressure of the process chamber may be selected from: 0.4 Torr to 0.6 Torr, for example, 0.45 Torr to 0.55 Torr, for example, 0.5 Torr.

[0097] Furthermore, the surface roughness of the bottom silicon seed crystal layer 221 includes one or more of the following: <Ra_1<0.1nm,0<Rq_1<0.1nm。

[0098] In an embodiment of the present invention, the silicon source material for forming the bottom silicon seed layer 221 of the stacked structure includes diisopropylaminosilane, so that diisopropylaminosilane with a higher production cost (compared with disilane) can be used to form a stacked structure with a smaller bottom surface roughness, a higher bottom smoothness and density, thereby providing a better foundation for the subsequent polycrystalline silicon layer, helping to alleviate the molecular agglomeration problem of the polycrystalline silicon layer and reduce the surface roughness of the polycrystalline silicon layer.

[0099] In some embodiments where the diisopropylaminosilane is used as a silicon source to form the underlying silicon seed crystal layer 221, the thickness of the underlying silicon seed crystal layer 221 can be determined based on the surface average roughness Ra_0 and / or the surface root mean square roughness Rq_0 of the inner wall of the groove 211; the larger the surface average roughness Ra_0 of the inner wall of the groove 211, the larger the thickness of the underlying silicon seed crystal layer 221; and / or, the larger the surface root mean square roughness Rq_0 of the inner wall of the groove 211, the larger the thickness of the underlying silicon seed crystal layer 221.

[0100] like Figure 4 As shown by the dotted ellipse, since the bottom silicon seed crystal layer 221 has less molecular agglomeration, it can be well attached to the inner wall of the groove 211 to form a surface with high smoothness and density.

[0101] In the embodiment of the present invention, the greater the surface average roughness Ra_0 of the inner wall of the groove 211, the greater the thickness of the bottom silicon seed crystal layer 221; and / or, the greater the surface root mean square roughness Rq_0 of the inner wall of the groove 211, the greater the thickness of the bottom silicon seed crystal layer 221. When the surface roughness of the inner wall of the groove 211 is large, a thicker bottom silicon seed crystal layer 221 can be formed, so that the groove 211 can be compensated to a greater extent by using the bottom silicon seed crystal layer 221 with the highest smoothness and density.

[0102] Furthermore, the thickness of the underlying silicon seed crystal layer 221 can be a first preset multiple of the surface average roughness Ra_0 of the inner wall of the groove 211; or, the thickness of the underlying silicon seed crystal layer 221 is a second preset multiple of the surface root mean square roughness Rq_0 of the inner wall of the groove 211; or, the thickness of the underlying silicon seed crystal layer 221 is a third preset multiple of the weighted calculated value of the surface average roughness Ra_0 of the inner wall of the groove 211 and the surface root mean square roughness Rq_0 of the inner wall of the groove 211.

[0103] The weighted operation value may be a weighted average operation or a weighted sum operation, which may be selected according to actual needs.

[0104] In an embodiment of the present invention, the thickness of the bottom silicon seed crystal layer is a first preset multiple of the surface average roughness Ra_0 of the inner wall of the groove; or, the thickness of the bottom silicon seed crystal layer is a second preset multiple of the surface root mean square roughness Rq_0 of the inner wall of the groove; or, the thickness of the bottom silicon seed crystal layer is a third preset multiple of the weighted calculation value of the surface average roughness Ra_0 of the inner wall of the groove and the surface root mean square roughness Rq_0 of the inner wall of the groove. By adopting the above scheme, a more accurate thickness of the bottom silicon seed crystal layer that is more suitable for filling the current groove can be obtained by setting an appropriate ratio.

[0105] Furthermore, one or more of the first preset multiple, the second preset multiple and the third preset multiple can be selected from: [2,100].

[0106] In an embodiment of the present invention, one or more of the first preset multiple, the second preset multiple and the third preset multiple are selected from: [2,100], so that a value between doubling (such as 2 times) and increasing by two orders of magnitude (such as 100 times) can be used as a ratio. When the surface roughness of the inner wall of the groove 211 is greater, a thicker underlying silicon seed crystal layer 221 is formed. On the basis of using the underlying silicon seed crystal layer 221 to compensate for the groove 211 to a greater extent, the process cost of the underlying silicon seed crystal layer 221 is further controlled.

[0107] Reference Figure 5 , forming a middle silicon seed crystal layer 222 of the stacked structure.

[0108] Specifically, the number of silicon seed crystal layers included in the stacked structure is greater than or equal to 3; wherein the silicon source material used to form the middle silicon seed crystal layer 222 of the stacked structure may include bis(diethylamino)silane.

[0109] Among them, bis(diethylaminosilane) can also be called BDEAS, and its chemical formula can be expressed as C8H 22 N2Si.

[0110] In a specific implementation, the chemical formula for forming the intermediate silicon seed layer 222 using the diisopropylaminosilane as a silicon source can be expressed as follows:

[0111] 8H 22 N2Si→Si+4C2H4+2NH3;

[0112] Furthermore, the process parameters for forming the intermediate silicon seed layer 222 using the diisopropylaminosilane as a silicon source may include one or more of the following:

[0113] The process temperature is selected from: 350°C to 420°C;

[0114] The gas atmosphere is nitrogen atmosphere;

[0115] The chamber pressure of the process chamber is selected from: 0.4 Torr to 0.6 Torr;

[0116] The surface roughness of the intermediate silicon seed layer 222 includes one or more of the following: 0.1 nm <Ra_2<0.2nm,0.1nm<Rq_2<0.2nm。

[0117] Here, Ra_2 is used to represent the Ra of the middle silicon seed crystal layer 222 , and Rq_2 is used to represent the Rq of the middle silicon seed crystal layer 222 .

[0118] In a specific embodiment, a vertical furnace polysilicon growth process may be used to form the intermediate silicon seed crystal layer 222 in a furnace tube process chamber, thereby increasing the number of wafers accommodated in a single process and effectively improving process efficiency.

[0119] Further, the process temperature in the process chamber may be selected from: 350° C. to 420° C., such as 370° C. to 390° C., for example, 380° C.

[0120] Furthermore, the gas atmosphere in the process chamber may be a nitrogen atmosphere. Since nitrogen is a neutral gas, in an embodiment of the present invention, nitrogen may be used as a protective medium in an inactive state to improve the hardness and wear resistance of the intermediate silicon seed layer 222 .

[0121] Furthermore, the chamber pressure of the process chamber may be selected from: 0.4 Torr to 0.6 Torr, for example, 0.45 Torr to 0.55 Torr, for example, 0.5 Torr.

[0122] Furthermore, the surface roughness of the intermediate silicon seed layer 222 may include one or more of the following: 0.1 nm <Ra_2<0.2nm,0.1nm<Rq_2<0.2nm。

[0123] In the embodiment of the present invention, the number of silicon seed crystal layers included in the stacked structure is greater than or equal to 3; wherein the silicon source material used to form the middle silicon seed crystal layer 222 of the stacked structure includes bis(diethylamino)silane. Thus, the silicon seed crystal layer formed by using bis(diethylamino)silane as the silicon source can be used as a transition layer, and the stability between the seed crystal layers can be improved in the process of forming a stacked structure with a step-wise decrease in surface roughness and a step-wise increase in smoothness and density.

[0124] Reference Figure 6 , forming a top silicon seed crystal layer 223 of the stacked structure.

[0125] The silicon source material used to form the top silicon seed layer 223 of the stacked structure may include disilane.

[0126] Among them, the chemical formula of disilane can be expressed as Si2H6.

[0127] In a specific implementation, the chemical formula for forming the top silicon seed layer 223 using the silane as a silicon source can be expressed as follows:

[0128] Si2H6→2Si+3H2;

[0129] Furthermore, the process parameters for forming the top silicon seed layer 223 using the disilane as a silicon source may include one or more of the following:

[0130] The process temperature is selected from: 350°C to 420°C;

[0131] The gas atmosphere is nitrogen atmosphere;

[0132] The chamber pressure of the process chamber is selected from: 0.6 Torr to 1.0 Torr;

[0133] The surface roughness of the top silicon seed layer 223 may include one or more of the following: 0.2 nm <Ra_3<0.3nm,0.2nm<Rq_3<0.3nm。

[0134] In a specific embodiment, a vertical furnace polysilicon growth process may be used to form the top silicon seed crystal layer 223 in a furnace tube process chamber, thereby increasing the number of wafers accommodated in a single process and effectively improving process efficiency.

[0135] Further, the process temperature in the process chamber may be selected from: 350° C. to 420° C., such as 370° C. to 390° C., for example, 380° C.

[0136] Furthermore, the gas atmosphere in the process chamber may be a nitrogen atmosphere. Since nitrogen is a neutral gas, in an embodiment of the present invention, nitrogen may be used as a protective medium in an inactive state to improve the hardness and wear resistance of the top silicon seed crystal layer 223 .

[0137] Furthermore, the chamber pressure of the process chamber may be selected from: 0.6 Torr to 1.0 Torr, for example, 0.7 Torr to 0.9 Torr, for example, 0.8 Torr.

[0138] Furthermore, the surface roughness of the top silicon seed layer 223 may include one or more of the following: 0.2 nm <Ra_3<0.3nm,0.2nm<Rq_3<0.3nm。

[0139] Wherein, Ra_3 is used to represent the Ra of the top silicon seed crystal layer 223 , and Rq_3 is used to represent the Rq of the top silicon seed crystal layer 223 .

[0140] In an embodiment of the present invention, the silicon source material for forming the top silicon seed layer 223 of the stacked structure includes disilane, so that disilane with lower production cost (compared with diisopropylaminosilane) can be used to form a stacked structure with larger top surface roughness, smaller top smoothness and density steps, but lower process cost. This provides a better foundation for the subsequent polysilicon layer, further alleviates the molecular agglomeration problem of the polysilicon layer, reduces the surface roughness of the polysilicon layer, and controls the production cost as much as possible.

[0141] Further, in Figures 4 to 6 In the semiconductor structure shown, the surface roughness of each silicon seed crystal layer of the stacked structure may increase layer by layer in a direction from the bottom to the top of the semiconductor substrate.

[0142] In the embodiment of the present invention, by forming each silicon seed crystal layer with a step-by-step change in surface roughness, a step-by-step improvement in density can be achieved, thereby achieving a better balance between production cost and roughness improvement.

[0143] Reference Figure 7 , a polysilicon layer 230 is formed on the stacked structure to fill the trench 211 .

[0144] In some embodiments, the silicon source material used to form the polysilicon layer 230 may include monosilane.

[0145] The chemical formula of monosilane may be SiH4.

[0146] It should be noted that the silicon source material used to form the polysilicon layer 230 is not limited to monosilane. In other specific embodiments, the silicon source material used to form the polysilicon layer 230 may include dichloromethane (SiH2Cl2) or trichloromethane (SiHCl3).

[0147] Further, the process parameters for forming the polysilicon layer 230 using the monosilane as a silicon source may include one or more of the following:

[0148] The process temperature is selected from: 500°C to 680°C;

[0149] The thickness of the polysilicon layer 230 is selected from: 1000A to 8000A;

[0150] The surface roughness of the polysilicon layer 230 includes one or more of the following: 0.3 nm <Ra_p,0.3nm<Rq_p。

[0151] Here, Ra_p is used to represent Ra of the polysilicon layer 230 , and Rq_p is used to represent Rq of the polysilicon layer 230 .

[0152] In a specific embodiment, a vertical furnace polysilicon growth process may be used to form the polysilicon layer 230 in a furnace tube process chamber, thereby increasing the number of wafers accommodated in a single process and effectively improving process efficiency.

[0153] Furthermore, the process temperature in the process chamber may be selected from: 500° C. to 680° C., such as 580° C. to 620° C., for example, 600° C. is used.

[0154] Furthermore, the thickness of the polysilicon layer 230 may be selected from: 1000 Å to 8000 Å, such as 4000 Å to 6000 Å, for example, 5000 Å.

[0155] Furthermore, the surface roughness of the polysilicon layer 230 may include one or more of the following: 0.3 nm <Ra_p,0.3nm<Rq_p。

[0156] In an embodiment of the present invention, a single-layer silicon seed crystal layer or a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each groove 211, and a polysilicon layer 230 is formed on the single-layer silicon seed crystal layer or the stacked structure to fill the groove 211, wherein the surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove 211. Before forming the polysilicon layer 230, a single-layer or multi-layer silicon seed crystal layer with less molecular agglomeration and smaller surface roughness is formed first, and then the polysilicon layer 230 is formed on the single-layer or multi-layer silicon seed crystal layer. This can provide a smoother and denser foundation for the polysilicon layer 230, effectively alleviate the molecular agglomeration problem of the polysilicon layer 230, and reduce the surface roughness of the polysilicon layer 230, thereby reducing the possibility of gaps in the process of filling the groove 211 and effectively improving the filling effect.

[0157] It should be pointed out that when a single-layer silicon seed crystal layer is formed on the inner wall of each groove 211, the silicon source material of the single-layer silicon seed crystal layer can be selected from: the silicon source material of the bottom silicon seed crystal layer 221, the silicon source material of the middle silicon seed crystal layer 222, and the silicon source material of the top silicon seed crystal layer 223 according to the specific situation.

[0158] In a specific embodiment, a single silicon seed layer can be formed based on the silicon source material of the underlying silicon seed layer 221, so that when only a single silicon seed layer is formed, the groove 211 can be compensated to a greater extent based on the silicon source material of the underlying silicon seed layer 221 with the highest smoothness and density.

[0159] In some embodiments, the aspect ratio of part or all of the trench 211 may be greater than 1.5:1.

[0160] In the embodiment of the present invention, the aspect ratio of part or all of the trench 211 is greater than 1.5: 1. Therefore, when part or all of the trench 211 has a high aspect ratio and is more prone to filling gaps, the embodiment of the present invention can provide a smoother and denser foundation for the polysilicon layer 230, effectively alleviate the molecular agglomeration problem of the polysilicon layer 230, and reduce the surface roughness of the polysilicon layer 230, thereby reducing the possibility of gaps in the process of filling the trench 211 and effectively improving the filling effect.

[0161] In some embodiments, the thickness of the single silicon seed layer is 1 / 100 to 1 / 5 of the standard depth of the trench 211 ; or, the thickness of the stacked structure is 1 / 100 to 1 / 5 of the standard depth of the trench 211 .

[0162] In an embodiment of the present invention, the thickness of the single-layer silicon seed crystal layer is 1 / 100 to 1 / 5 of the standard depth of the groove 211; or, the thickness of the stacked structure is 1 / 100 to 1 / 5 of the standard depth of the groove 211. By setting an appropriate total thickness, it is possible to further control production costs while obtaining a better filling effect.

[0163] In some embodiments, the step coverage of each silicon seed crystal layer may be greater than or equal to 90%, for example, greater than or equal to 92%, for example, a step coverage of 95%.

[0164] In the embodiment of the present invention, the step coverage of each silicon seed crystal layer is greater than or equal to 90%, so that during the filling process of the trench 211, the coverage of the top corner of the trench 211 can be improved, further reducing the possibility of gaps and improving the filling effect.

[0165] Reference Figure 8 , Figure 8 1 is a schematic diagram comparing the surface roughness obtained after forming polysilicon layers on various surfaces respectively in an embodiment of the present invention.

[0166] More specifically, in Figure 8 In the experiments shown, the material of the inner wall of the trench is Si or SiO2, the silicon source material of the single-layer silicon seed crystal layer is disilane (Si2H6), and the silicon source material of the multi-layer silicon seed crystal layer is Figure 7 The illustrated situation is described as an example, but the embodiment of the present invention is not limited thereto.

[0167] As shown in the figure, the comparative experiment includes the following three items: forming a polysilicon layer on the surface of the inner wall of the groove, forming a polysilicon layer on the surface of the single-layer silicon seed crystal layer, and forming a polysilicon layer on the surface of the multi-layer silicon seed crystal layer.

[0168] Among them, the surface roughness obtained after forming a polysilicon layer on the inner wall surface of the groove is the highest, and the Ra of the polysilicon layer is about 0.6, and the Rp is about 0.8.

[0169] The surface roughness obtained after a polysilicon layer is formed on the surface of the multi-layer silicon seed crystal layer is the lowest, and the Ra of the polysilicon layer is about 0.2 and the Rp is about 0.3.

[0170] The surface roughness obtained after forming a polysilicon layer on the surface of the single-layer silicon seed crystal layer is between the two.

[0171] From the above, it can be seen that before forming the polysilicon layer, a single-layer or multi-layer silicon seed crystal layer with less molecular agglomeration and smaller surface roughness is first formed, and then a polysilicon layer is formed on the single-layer or multi-layer silicon seed crystal layer. This can provide a smoother and denser foundation for the polysilicon layer and effectively reduce the surface roughness of the polysilicon layer.

[0172] In an embodiment of the present invention, a semiconductor structure is further provided, referring to Figure 7 , may include: a semiconductor substrate 200, wherein the semiconductor substrate 200 has one or more grooves 211; a stacked structure of a single-layer silicon seed crystal layer or multiple layers of silicon seed crystal layers, formed on the inner wall of each groove 211, wherein each silicon seed crystal layer has its own silicon seed crystal layer surface roughness; a polycrystalline silicon layer 230, formed on the silicon seed crystal layer, wherein the polycrystalline silicon layer 230 is used to fill the groove 211; wherein the surface roughness of each silicon seed crystal layer is less than the surface roughness of the inner wall of the groove 211.

[0173] Furthermore, the silicon source material used to form the polysilicon layer 230 includes monosilane.

[0174] Further, the polysilicon layer 230 formed by using the monosilane as the silicon source includes one or more of the following: the thickness of the polysilicon layer 230 is selected from: 1000A to 8000A; the surface roughness of the polysilicon layer 230 includes one or more of the following: 0.3nm <Ra_p,0.3nm<Rq_p。

[0175] Furthermore, a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each groove 211 ; wherein, from the bottom to the top of the semiconductor substrate, the surface roughness of each silicon seed crystal layer of the stacked structure increases layer by layer.

[0176] Further, the silicon source material used to form the bottom silicon seed layer 221 of the stacked structure includes diisopropylaminosilane; and / or the silicon source material used to form the top silicon seed layer 223 of the stacked structure includes disilane.

[0177] Furthermore, the surface roughness of the bottom silicon seed layer 221 formed by using the diisopropylaminosilane as the silicon source includes one or more of the following: <Ra_1<0.1nm,0<Rq_1<0.1nm。

[0178] Furthermore, the surface roughness of the top silicon seed layer 223 formed by using the disilane as the silicon source includes one or more of the following: 0.2 nm <Ra_3<0.3nm,0.2nm<Rq_3<0.3nm。

[0179] Furthermore, the number of silicon seed crystal layers included in the stacked structure is greater than or equal to 3; wherein the silicon source material used to form the middle silicon seed crystal layer 222 of the stacked structure includes bis(diethylamino)silane.

[0180] Furthermore, the surface roughness of the intermediate silicon seed layer 222 formed by using the bis(diethylamino)silane as the silicon source includes one or more of the following: 0.1 nm <Ra_2<0.2nm,0.1nm<Rq_2<0.2nm。

[0181] Furthermore, a depth-to-width ratio of part or all of the trench 211 is greater than 1.5:1.

[0182] Further, the thickness of the single silicon seed crystal layer is 1 / 100 to 1 / 5 of the standard depth of the groove 211 ; or, the thickness of the stacked structure is 1 / 100 to 1 / 5 of the standard depth of the groove 211 .

[0183] Furthermore, the step coverage of each silicon seed crystal layer is greater than or equal to 90%.

[0184] Furthermore, the semiconductor base 200 may include: a semiconductor substrate having a plurality of fins 201 ; wherein the trenches 211 are formed between adjacent fins 201 .

[0185] For more information about the principles, specific implementations and beneficial effects of the semiconductor structure, please refer to the relevant description of the method for forming the semiconductor structure mentioned above, which will not be repeated here.

[0186] It should be understood that the term "and / or" herein is merely an association relationship describing associated objects, indicating that three relationships may exist, for example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " herein indicates that the associated objects before and after are in an "or" relationship. As used herein, unless otherwise expressly stated, the term "or" covers all possible combinations unless not feasible. For example, if a component is stated to include A or B, then unless otherwise expressly stated or not feasible, the component may include A, or B, or A and B. As a second example, if a component is stated to include A, B, or C, then unless otherwise expressly stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0187] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0188] Relational terms appearing in the embodiments of the present application, such as first, second, etc., are only used to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. In addition, the words "include", "have", "include" and other similar forms are intended to be equivalent in meaning and are open-ended, and one or more items following any of these words are not meant to be an exhaustive list of such one or more items, or to be limited to the listed one or more items.

[0189] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0190] In the foregoing description, embodiments have been described with reference to many specific details, which may vary depending on the implementation. Certain changes and modifications may be made to the described embodiments. In view of the description and practice of the present application disclosed herein, other embodiments will be clear to those skilled in the art. The description and examples are intended to be considered as merely exemplary, and the true scope and spirit of the present application are indicated by the following claims. The order of steps shown in the accompanying drawings is also intended to be used for illustrative purposes only and is not intended to be limited to any particular order of steps. Therefore, it will be appreciated by those skilled in the art that these steps may be performed in different orders while implementing the same method.

[0191] In the drawings and the specification, exemplary embodiments have been disclosed. However, many variations and modifications may be made to these embodiments. Therefore, although specific terms are employed, they are used only in a general and descriptive sense and not for the purpose of limitation.

[0192] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method comprises: Providing a semiconductor substrate having one or more trenches; Forming a single silicon seed crystal layer or a stacked structure of multiple silicon seed crystal layers on the inner wall of each groove, wherein each silicon seed crystal layer has its own silicon seed crystal layer surface roughness; forming a polysilicon layer on the single-layer silicon seed crystal layer or the stacked structure to fill the trench; The surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove.

2. The method according to claim 1, characterized in that The surface roughness includes one or more of the following: Average surface roughness Ra; Surface root mean square roughness Rq; The surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove, including: The average surface roughness of each silicon seed crystal layer is smaller than the average surface roughness Ra_0 of the inner wall of the groove; and / or, The root mean square roughness of the surface of each silicon seed crystal layer is smaller than the root mean square roughness Rq_0 of the inner wall surface of the groove.

3. The method according to claim 1, characterized in that The silicon source material used to form the polysilicon layer includes monosilane.

4. The method according to claim 3, characterized in that The process parameters for forming the polysilicon layer using the monosilane as a silicon source include one or more of the following: The process temperature is selected from: 500°C to 680°C; The thickness of the polysilicon layer is selected from: 1000A to 8000A; The surface roughness of the polysilicon layer includes one or more of the following: 0.3 nm <Ra_p,0.3nm<Rq_p。 5. The method according to claim 1, characterized in that A stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each trench; Wherein, from the bottom to the top of the semiconductor substrate, the surface roughness of each silicon seed crystal layer of the stacked structure increases layer by layer.

6. The method according to claim 5, characterized in that The silicon source material for forming the bottom silicon seed layer of the stacked structure includes diisopropylaminosilane; and / or, The silicon source material for forming the top silicon seed layer of the stacked structure includes disilane.

7. The method according to claim 6, characterized in that The process parameters for forming the bottom silicon seed layer using the diisopropylaminosilane as a silicon source include one or more of the following: The process temperature is selected from: 350°C to 420°C; The gas atmosphere is nitrogen atmosphere; The chamber pressure of the process chamber is selected from: 0.4 Torr to 0.6 Torr; The surface roughness of the bottom silicon seed crystal layer includes one or more of the following: <Ra_1<0.1nm,0<Rq_1<0.1nm。 8. The method according to claim 6, characterized in that In the case where the diisopropylaminosilane is used as a silicon source to form the bottom silicon seed crystal layer, the thickness of the bottom silicon seed crystal layer is determined according to the surface average roughness Ra_0 and / or the surface root mean square roughness Rq_0 of the inner wall of the groove; the greater the surface average roughness Ra_0 of the inner wall of the groove, the greater the thickness of the bottom silicon seed crystal layer; and / or, The greater the surface root mean square roughness Rq_0 of the inner wall of the groove, the greater the thickness of the underlying silicon seed crystal layer.

9. The method according to claim 8, characterized in that The thickness of the bottom silicon seed crystal layer is a first preset multiple of the surface average roughness Ra_0 of the inner wall of the groove; or, The thickness of the bottom silicon seed crystal layer is a second preset multiple of the surface root mean square roughness Rq_0 of the inner wall of the groove; or, The thickness of the bottom silicon seed crystal layer is a third preset multiple of a weighted calculation value of a surface average roughness Ra_0 of an inner wall of the groove and a surface root mean square roughness Rq_0 of the inner wall of the groove.

10. The method according to claim 9, characterized in that One or more of the first preset multiple, the second preset multiple and the third preset multiple are selected from: [2,100].

11. The method according to claim 6, characterized in that The process parameters for forming the top silicon seed layer using the disilane as a silicon source include one or more of the following: The process temperature is selected from: 350°C to 420°C; The gas atmosphere is nitrogen atmosphere; The chamber pressure of the process chamber is selected from: 0.6 Torr to 1.0 Torr; The surface roughness of the top silicon seed layer includes one or more of the following: 0.2 nm <Ra_3<0.3nm,0.2nm<Rq_3<0.3nm。 12. The method according to claim 6, characterized in that The number of silicon seed crystal layers included in the stacked structure is greater than or equal to 3; Wherein, the silicon source material used to form the middle silicon seed layer of the stacked structure includes bis(diethylamino)silane.

13. The method according to claim 12, characterized in that The process parameters for forming the intermediate silicon seed layer using the bis(diethylamino)silane as a silicon source include one or more of the following: The process temperature is selected from: 350°C to 420°C; The gas atmosphere is nitrogen atmosphere; The chamber pressure of the process chamber is selected from: 0.4 Torr to 0.6 Torr; The surface roughness of the intermediate silicon seed layer includes one or more of the following: 0.1 nm <Ra_2<0.2nm,0.1nm<Rq_2<0.2nm。 14. The method according to claim 1, characterized in that A depth-to-width ratio of part or all of the grooves is greater than 1.5:

1.

15. The method according to claim 1, characterized in that The thickness of the single silicon seed layer is 1 / 100 to 1 / 5 of the standard depth of the trench; or, The thickness of the laminated structure is 1 / 100 to 1 / 5 of the standard depth of the groove.

16. The method according to claim 1, characterized in that The step coverage of each silicon seed crystal layer is greater than or equal to 90%.

17. The method according to claim 1, characterized in that The semiconductor substrate comprises: a semiconductor substrate having a plurality of fins; Wherein, the groove is formed between adjacent fins.

18. A semiconductor structure, characterized in that: include: A semiconductor substrate having one or more trenches; A single silicon seed crystal layer or a stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each groove, wherein each silicon seed crystal layer has its own silicon seed crystal layer surface roughness; A polysilicon layer is formed on the silicon seed crystal layer, and the polysilicon layer is used to fill the trench; The surface roughness of each silicon seed crystal layer is smaller than the surface roughness of the inner wall of the groove.

19. The semiconductor structure according to claim 18, characterized in that A stacked structure of multiple silicon seed crystal layers is formed on the inner wall of each trench; Wherein, from the bottom to the top of the semiconductor substrate, the surface roughness of each silicon seed crystal layer of the stacked structure increases layer by layer.

20. The semiconductor structure according to claim 19, characterized in that The silicon source material for forming the bottom silicon seed layer of the stacked structure includes diisopropylaminosilane; and / or, The silicon source material for forming the top silicon seed layer of the stacked structure includes disilane.

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