Formation method of semiconductor structure

Abstract

The invention relates to a method for forming a semiconductor structure, which comprises the following steps of: providing a substrate which comprises a substrate, a dielectric layer positioned on the substrate and a mask layer positioned on the surface of the dielectric layer; etching gas is adopted to take the mask layer as a mask, a part of thickness of the dielectric layer is removed through etching, an initial groove is formed, and the number ratio of carbon atoms to fluorine atoms in the etching gas is a first ratio; the etched substrate is washed with washing gas, the number ratio of carbon atoms to fluorine atoms of the washing gas is a second ratio, and the second ratio is smaller than the first ratio; the second ratio is smaller than the first ratio, on one hand, the flushing gas is added, namely, carbon atoms in the etching gas are diluted, so that carbon-containing by-products are reduced, on the other hand, fluorine atoms are increased, the fluorine atoms can decompose the metal by-products from macromolecules to micromolecules, and the metal by-products are decomposed from macromolecules to micromolecules. And in the subsequent air exhaust process, metal by-products can be removed, so that the cleanliness of the surfaces of the etched mask layer and the dielectric layer is improved, and the method has a relatively wide application range.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] The manufacturing of semiconductor wafers must go through some process flows. This process includes all the different semiconductor wafer process steps such as etching and lithography. The traditional manufacturing process includes 300-400 steps, each of which affects the formation of the final circuit structure of the single chip on the semiconductor wafer. In the traditional manufacturing process, two major sub-processes are distinguished. The first major sub-process can be called the front end of line (FEOL), and the second major sub-process can be called the back end of line (BEOL).

[0003] The traditional front-end process starts with laser marking of the wafer, followed by the formation of shallow trench isolation, ion implantation to form P-well and N-well, etching of polysilicon, and ion implantation of various areas such as drain and source of transistor structure. The back-end process may include the formation of metal lines and the formation of via contacts between metal lines on different layers on the wafer. There are usually two or more metal layers including metal interconnect lines. Vias act between two metal layers. The back-end process is the connection between the devices on each layer of the front-end process and other circuits on the chip and devices outside the chip.

[0004] However, the formation quality of the back-end process still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a base, including a substrate, a dielectric layer located on the substrate, and a mask layer located on the surface of the dielectric layer; using an etching gas to use the mask layer as a mask to etch away a portion of the dielectric layer to form an initial groove, wherein the ratio of the number of carbon atoms to the number of fluorine atoms in the etching gas is a first ratio; using a flushing gas to flush the etched substrate, wherein the ratio of the number of carbon atoms to the number of fluorine atoms in the flushing gas is a second ratio, and the second ratio is smaller than the first ratio.

[0007] Optionally, the flushing gas is a mixed gas of carbon fluorine gas and oxygen, wherein the ratio of the number of carbon atoms to the number of fluorine atoms in the carbon fluorine gas is in a range of 1:8 to 1:4.

[0008] Optionally, the carbon fluoride gas includes carbon tetrafluoride gas.

[0009] Optionally, in the process of flushing the substrate after etching with the flushing gas, a high source power ranging from 800W to 1500W and a bias power ranging from 0W to 15W are used.

[0010] Optionally, the method further includes: extracting the etching gas and the flushing gas after the reaction using a gas extraction process.

[0011] Optionally, the process parameters of the exhaust process include a pressure range of 20mT to 60mT.

[0012] Optionally, it also includes: forming a conductive plug in the substrate, forming a first metal layer on the surface of the substrate, the dielectric layer is formed on the surface of the first metal layer, and the bottom surface of the first metal layer contacts the top surface of the conductive plug.

[0013] Optionally, after performing the extraction process, the method further includes: removing the mask layer.

[0014] Optionally, after removing the mask layer, the method further includes: continuing to etch the remaining dielectric layer along the initial groove until the surface of the first metal layer is exposed to form a through hole.

[0015] Optionally, the method further includes: forming a second metal layer in the through hole, wherein the first metal layer and the second metal layer constitute an interconnection structure.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] In the method for forming a semiconductor structure of the present invention, after etching away a portion of the thickness of the dielectric layer using the etching gas and the mask layer as a mask, a large amount of carbon-containing byproducts and a small amount of metal-containing byproducts will accumulate on the surface of the mask layer; the substrate after etching is flushed using a flushing gas, wherein the ratio of the number of carbon atoms and fluorine atoms in the flushing gas is a second ratio, and the ratio of the number of carbon atoms and fluorine atoms in the etching gas is a first ratio. The second ratio is smaller than the first ratio, that is, the flushing gas uses a gas with a low carbon-fluorine ratio. On the one hand, adding the flushing gas is equivalent to diluting the carbon atoms in the etching gas, thereby helping to reduce or lower carbon-containing byproducts. On the other hand, as the number of fluorine atoms increases, the fluorine atoms will decompose the metal byproducts from large molecules to small molecules, which helps to remove the metal byproducts in the subsequent gas extraction process, thereby improving the cleanliness of the surface of the mask layer and the dielectric layer after etching, and helping to improve the quality of the formed semiconductor structure. The method has a wide range of applications.

[0018] Furthermore, in the process of flushing the substrate after etching with the flushing gas, a high source power range of 800W to 1500W and a bias power range of 0W to 15W are used, which can not only ensure the dissociation of carbon and fluorine plasma and improve the lateral etching reaction, but also avoid the generation of more polymers due to bombardment transition, and at the same time create a low-pressure environment for the reaction chamber, which is convenient for accelerating the subsequent vacuum pumping speed and timely extracting the by-products in the reaction chamber. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 5 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0020] As described in the background art, the formation quality of the back-end process still needs to be improved.

[0021] The inventors have discovered that in the currently used back-end process, a large area of ​​the first metal layer at the bottom of the second metal layer will be exposed during the etching of the second metal layer, resulting in more metal reactions, leading to poor etching conditions in the etching reaction chamber, and difficulty in removing metal by-products and carbon-containing by-products. This will also affect other processes, limit production capacity, and affect the formation quality of the semiconductor structure.

[0022] The inventor has found through research that after etching away a portion of the dielectric layer with the mask layer as a mask using an etching gas, a large amount of carbon-containing by-products and a small amount of metal-containing by-products will accumulate on the surface of the mask layer; the substrate after etching is flushed using a flushing gas, wherein the ratio of the number of carbon atoms and fluorine atoms in the flushing gas is a second ratio, and the ratio of the number of carbon atoms and fluorine atoms in the etching gas is a first ratio, and the second ratio is smaller than the first ratio, that is, the flushing gas uses a gas with a low carbon-fluorine ratio as the flushing gas. On the one hand, adding the flushing gas is equivalent to diluting the carbon atoms in the etching gas, thereby helping to reduce or lower carbon-containing by-products. On the other hand, as the number of fluorine atoms increases, the fluorine atoms will decompose the metal by-products from large molecules to small molecules, which helps to remove the metal by-products in the subsequent gas extraction process, thereby improving the cleanliness of the surface of the mask layer and the dielectric layer after etching, and helping to improve the quality of the formed semiconductor structure, and has a wider range of applications.

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] First, please refer to Figure 1 , providing a substrate.

[0025] In this embodiment, the base includes a substrate 100 , a dielectric layer 101 located on the substrate 100 , and a mask layer 102 located on the surface of the dielectric layer 101 .

[0026] In this embodiment, a transistor is also formed on the substrate 100 .

[0027] In other embodiments, no transistor may be formed on the substrate 100 .

[0028] In this embodiment, a conductive plug (not shown in the figure) is formed in the substrate 100 , and the conductive plug is used to form an electrical connection with an interconnection structure formed subsequently.

[0029] In this embodiment, a first metal layer 103 is formed on the surface of the substrate 100 , the dielectric layer 101 is formed on the surface of the first metal layer 103 , and the bottom surface of the first metal layer 103 contacts the top surface of the conductive plug.

[0030] In this embodiment, one end of the conductive plug is connected to the transistor, and the other end of the conductive plug is connected to the first metal layer 103, so as to realize electrical connection between the transistor and the outside.

[0031] In this embodiment, the dielectric layer 101 is a laminated structure.

[0032] In other embodiments, the dielectric layer 101 may also be a single-layer structure.

[0033] In this embodiment, the dielectric layer 101 includes a protection layer 101a formed on the surface of the first metal layer 103; an oxide layer 101b formed on the surface of the protection layer 101a; and a reflective layer 101c formed on the surface of the oxide layer 101b.

[0034] In this embodiment, the material of the protection layer 101 a is silicon carbide nitride (SiCN).

[0035] In other embodiments, the material of the protection layer 101a is silicon nitride or the like.

[0036] In this embodiment, the material of the oxide layer 101b is silicon oxide.

[0037] In other embodiments, the material of the oxide layer 101b may also be silicon oxynitride or the like.

[0038] In this embodiment, the material of the mask layer 102 is photoresist.

[0039] In other embodiments, the mask layer 102 may also be a hard mask layer 102, specifically made of materials such as silicon nitride.

[0040] Please refer to Figure 2 , using the mask layer 102 as a mask, etching gas to remove a portion of the dielectric layer 101 to form an initial trench 104, wherein the ratio of the number of carbon atoms to the number of fluorine atoms in the etching gas is a first ratio.

[0041] In this embodiment, after etching, a large amount of carbon-, fluorine- and oxygen-containing by-products will accumulate on the surface of the mask layer 102, among which the carbon-containing by-products will have a greater impact on the etching morphology in the subsequent process. In addition, a small amount of metal-containing by-products will also accumulate on the surface of the mask layer 102.

[0042] It should be noted that, because the substrate is placed in the reaction chamber for etching, the environment in the reaction chamber itself may contain metal residues, and these metal residues will also react with the etching gas to form by-products containing metal; in addition, there is not only one metal material, the first metal layer 103, on the substrate, but there will be other metal layers in other areas of the substrate, which will be damaged to some extent during the etching process, thereby also producing some of the metal-containing by-products.

[0043] In this embodiment, only the by-products accumulated on the surface of the mask layer 102 are shown (black circles in the figure), but the sidewalls and bottom surfaces of the initial trench 104 may also be enriched with some by-products, which are not shown here.

[0044] In this embodiment, after etching, the surface of the first metal layer 103 still has a partial thickness of the protection layer 101 a .

[0045] Please refer to Figure 3 The etched substrate is flushed with a flushing gas, wherein the ratio of the number of carbon atoms to the number of fluorine atoms in the flushing gas is a second ratio, and the second ratio is smaller than the first ratio.

[0046] In this embodiment, the ratio of the number of carbon atoms and fluorine atoms in the flushing gas is reduced, that is, a gas with a low carbon-fluorine ratio is added to the reaction chamber, so that the carbon content is equivalent to being diluted, and the fluorine content is equivalent to being increased, then the production of by-products mainly containing carbon will be reduced, and the increase of fluorine can make the metal-containing by-products change from large molecules to small molecules, which is helpful to remove the metal by-products in the subsequent gas extraction process, thereby improving the cleanliness of the surface of the mask layer 102 and the dielectric layer 101 after etching, helping to improve the quality of the formed semiconductor structure, and has a wider range of applications.

[0047] In this embodiment, the flushing gas creates a clean etching atmosphere, which does not affect the quality of etching and can also reduce carbon-containing byproducts generated by etching.

[0048] In this embodiment, the process of flushing the substrate after etching with the flushing gas and forming the initial groove 104 with the etching gas are both classified as the etching process of removing a portion of the thickness of the dielectric layer 101 by etching with the mask layer 102 as a mask.

[0049] In this embodiment, the flushing gas is a mixed gas of carbon fluorine gas and oxygen, wherein the ratio of the number of carbon atoms to the number of fluorine atoms in the carbon fluorine gas is in a range of 1:8 to 1:4.

[0050] In this embodiment, the carbon fluorine gas includes carbon tetrafluoride gas.

[0051] In this embodiment, the high source power range of the flushing gas during flushing and etching of the substrate is 800W to 1500W, and the bias power range is 0W to 15W, which can not only ensure the dissociation of carbon and fluorine plasma and improve the lateral etching reaction, but also avoid the generation of more polymers due to bombardment transition, and at the same time create a low-pressure environment for the reaction chamber, which is convenient for accelerating the subsequent vacuum pumping speed and timely extracting the by-products in the reaction chamber.

[0052] Please continue to refer to Figure 3 , a gas extraction process is used to extract the etching gas and the flushing gas after the reaction.

[0053] In this embodiment, the process parameters of the pumping process include a pressure range of 20 mT to 60 mT.

[0054] In this embodiment, low pressure and faster extraction speed are combined in the exhaust process to timely extract the by-products in the reaction chamber during the etching process, which greatly reduces the polymer residues on the surface of the mask layer 102 and improves the cleanliness of the morphology after etching, and has a wider range of applications.

[0055] Please refer to Figure 4 , remove the mask layer 102.

[0056] In this embodiment, the process of removing the mask layer 102 is an ashing process.

[0057] In other embodiments, the mask layer 102 may be removed by an etching process.

[0058] In this embodiment, after flushing with the flushing gas and the pumping process, there are no metal-containing by-products, only a small amount of carbon-containing by-products. These small amounts of carbon-containing by-products are basically concentrated on the mask layer 102. In this way, by removing the mask layer 102, all by-products are basically removed, which greatly improves the environmental cleanliness in the reaction chamber, and at the same time improves the cleanliness of the surface of the initial groove 104, paving the way for forming a higher quality semiconductor structure.

[0059] Please refer to Figure 5 , continue to etch the remaining dielectric layer 101 along the initial groove 104 until the surface of the first metal layer 103 is exposed to form a through hole (not marked in the figure), and form a second metal layer 105 in the through hole. The first metal layer 103 and the second metal layer 105 constitute an interconnection structure.

[0060] In this embodiment, the first metal layer 103 and the second metal layer 105 are in direct contact and subsequently directly form an electrical connection, which replaces the traditional method of forming an electrical connection between the first metal layer 103 and the second metal layer 105 through a contact hole (VIA), thereby reducing costs.

[0061] In this embodiment, the material of the first metal layer 103 is copper.

[0062] In other embodiments, the material of the first metal layer 103 may also be other metal materials such as titanium and aluminum.

[0063] In this embodiment, the material of the second metal layer 105 is copper.

[0064] In other embodiments, the material of the second metal layer 105 may also be other metal materials such as titanium and aluminum.

[0065] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a base, including a substrate, a dielectric layer located on the substrate, and a mask layer located on a surface of the dielectric layer; An etching gas is used with the mask layer as a mask to etch away a portion of the dielectric layer to form an initial groove, and the ratio of the number of carbon atoms to the number of fluorine atoms in the etching gas is a first ratio; a flushing gas is used to flush the etched substrate, and the ratio of the number of carbon atoms to the number of fluorine atoms in the flushing gas is a second ratio, and the second ratio is smaller than the first ratio.

2. The method for forming a semiconductor structure according to claim 1, wherein: The flushing gas is a mixed gas of carbon fluorine gas and oxygen, wherein the ratio of the number of carbon atoms to the number of fluorine atoms in the carbon fluorine gas is in a range of 1:8 to 1:

4.

3. The method for forming a semiconductor structure according to claim 2, wherein: The carbon fluoride gas includes carbon tetrafluoride gas.

4. The method for forming a semiconductor structure according to claim 1, wherein: The flushing gas flushes the substrate after etching with a high source power ranging from 800W to 1500W and a bias power ranging from 0W to 15W.

5. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: The etching gas and the flushing gas after the reaction are extracted by using an exhaust process.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters of the exhaust process include a pressure range of 20mT to 60mT.

7. The method for forming a semiconductor structure according to claim 5, wherein: Also includes: A conductive plug is formed in the substrate, a first metal layer is formed on the surface of the substrate, the dielectric layer is formed on the surface of the first metal layer, and the bottom surface of the first metal layer contacts the top surface of the conductive plug.

8. The method for forming a semiconductor structure according to claim 7, wherein: After performing the extraction process, the method further includes: removing the mask layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: After removing the mask layer, the method further includes: continuing to etch the remaining dielectric layer along the initial groove until the surface of the first metal layer is exposed to form a through hole.

10. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: A second metal layer is formed in the through hole, and the first metal layer and the second metal layer constitute an interconnection structure.

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