High-resistance resistor structure and manufacturing method thereof

Abstract

The invention discloses a high-resistance resistor structure, which is applied to an integrated circuit and comprises a substrate; the first resistance layer is directly arranged in the substrate, the upper surface of the first resistance layer is flush with the upper surface of the substrate, and at least two first metal via holes are formed in the upper surface of the first resistance layer; the second resistance layer is directly arranged in the first resistance layer, the upper surface of the second resistance layer is flush with the upper surface of the first resistance layer, and at least two second metal through holes are formed in the upper portion of the upper surface of the second resistance layer; the metal layer is laid above the upper surface formed by the substrate, the first resistance layer and the second resistance layer and above the at least two second metal through holes; wherein the first resistance layer and the second resistance layer are connected in series through the first metal via hole, the second metal via hole and the metal layer.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a high-resistance resistor structure and a manufacturing method thereof. Background Art

[0002] In the process of integrated circuit design, resistors are very important components. Their main functions are current limiting, current shunting, voltage limiting, voltage dividing, etc. They can also protect circuits, such as against ESD. Commonly used resistors are NWELL resistors, POLY resistors, and AA resistors. Different resistor types and different resistance values ​​can be selected according to different circuit design requirements during circuit design.

[0003] In traditional integrated circuits, such as Figure 1 As shown in FIG. 1 , NWELL, POLY, and AA are usually used to design the resistors of integrated circuits separately, namely NWELL resistors, POLY resistors, and AA resistors. Traditional design schemes use resistors of single-layer materials, and the designed resistors have small resistance values. A large area is required during the layout implementation process, and the cost of chip manufacturing is high. Summary of the invention

[0004] Based on the above situation, the main purpose of the present invention is to provide a new resistor structure produced by stacking, which has a higher resistance value per unit area and saves chip area.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0006] A high resistance resistor structure, used in an integrated circuit, comprising:

[0007] substrate;

[0008] A first resistance layer, wherein the first resistance layer is directly disposed in the substrate, an upper surface of the first resistance layer is flush with an upper surface of the substrate, and at least two first metal vias are disposed on the upper surface of the first resistance layer;

[0009] a second resistor layer, wherein the second resistor layer is directly disposed in the first resistor layer, an upper surface of the second resistor layer is flush with an upper surface of the first resistor layer, and at least two second metal vias are disposed above the upper surface of the second resistor layer;

[0010] A metal layer, the metal layer being laid above the upper surface formed by the substrate, the first resistance layer and the second resistance layer, and above the at least two second metal vias;

[0011] The first resistance layer and the second resistance layer are connected in series through the first metal via, the second metal via and the metal layer.

[0012] Preferably, the at least two first metal vias are respectively arranged at both side ends of the first resistance layer, and the at least two second metal vias are respectively arranged at both side ends of the second resistance layer.

[0013] Among them, a first metal via and a second metal via are connected through the metal layer, and another first metal via and another second metal via are used to be electrically connected to a circuit outside the resistor structure.

[0014] Preferably, the first resistor layer is a NWELL resistor layer, and the second resistor layer is an AA resistor layer.

[0015] Preferably, the third resistance layer is directly arranged on the upper surface of the second resistance layer, and at least two third metal vias are arranged on the upper surface of the third resistance layer;

[0016] The first resistance layer, the second resistance layer, and the third resistance layer are connected in series through the first metal via, the second metal via, the third metal via, and the metal layer.

[0017] Preferably, the third resistor layer is a Poly resistor.

[0018] Preferably, one of the first metal vias is connected to one of the second metal vias through the metal layer, another of the second metal vias is connected to one of the third metal vias through the metal layer, and another of the third metal vias and another of the first metal vias are used to electrically connect to circuits outside the resistor structure.

[0019] Preferably, the area of ​​the third resistance layer is larger than that of the first resistance layer, and the third metal via is provided in a portion of the third resistance layer that is larger than that of the first resistance layer.

[0020] The present invention also provides a resistor structure layout circuit, comprising a plurality of high-resistance resistor structures described in the present invention, wherein the plurality of high-resistance resistor structures are connected through the first metal via, the second metal via, the metal layer and / or the third metal via.

[0021] The present invention also provides an integrated circuit, comprising the resistor structure layout circuit of the present invention.

[0022] The present invention also provides a method for manufacturing a high-resistance resistor, which is applied to an integrated circuit and comprises the steps of:

[0023] S100, performing well implantation in a substrate to form a first resistance layer, wherein an upper surface of the first resistance layer is flush with an upper surface of the substrate, and at least two first metal vias are provided on the upper surface of the first resistance layer;

[0024] S200, forming a second resistance layer in the first resistance layer by deposition and etching, wherein the upper surface of the second resistance layer is flush with the upper surface of the first resistance layer, and at least two second metal vias are provided above the upper surface of the second resistance layer;

[0025] S300, etching and depositing a metal layer above the upper surface formed by the first substrate, the first resistance layer, and the second resistance layer, and above the at least two second metal vias;

[0026] The first resistance layer and the second resistance layer are connected in series through the first metal via, the second metal via and the metal layer.

[0027] Preferably, the at least two first metal vias are respectively arranged at both side ends of the first resistance layer, and the at least two second metal vias are respectively arranged at both side ends of the second resistance layer.

[0028] Wherein, a first metal via is connected to a second metal via through the metal layer.

[0029] Preferably, the first resistor layer is a NWELL resistor layer, and the second resistor layer is an AA resistor layer.

[0030] Preferably, the method further comprises step S400, forming a third resistance layer on the upper surface of the second resistance layer by deposition and etching, and providing at least two third metal vias on the upper surface of the third resistance layer;

[0031] The first resistance layer, the second resistance layer, and the third resistance layer are connected in series through the first metal via, the second metal via, the third metal via, and the metal layer.

[0032] Preferably, the third resistor layer is a Poly resistor.

[0033] Preferably, one of the first metal vias is connected to one of the second metal vias through the metal layer, and another of the second metal vias is connected to one of the third metal vias through the metal layer, wherein another of the third metal vias and another of the first metal vias are used to electrically connect to circuits outside the resistor structure.

[0034] Preferably, the area of ​​the third resistance layer is set to be larger than the area of ​​the first resistance layer, and the third metal via is arranged in a portion of the third resistance layer that is larger than the first resistance layer.

[0035] The present invention uses a stacking method to produce a new resistor structure, in which the first resistor layer is a bottom resistor body, and the second resistor layer is an intermediate resistor body. The first resistor layer and the second resistor layer are connected in series through metal vias and metal layers to obtain a high-resistance structure. Multiple layers of resistive materials are stacked in a unit area, and metal vias are added. High-resistance resistors are formed in series with metal wires, which are suitable for different circuit adaptation scenarios. The new resistor structure provided by this solution has a higher resistance value per unit area, saving chip area.

[0036] Other beneficial effects of the present invention will be explained in the specific implementation manner through the introduction of specific technical features and technical solutions. Through the introduction of these technical features and technical solutions, those skilled in the art should be able to understand the beneficial technical effects brought about by the technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The preferred embodiments of the high resistance resistor structure and the manufacturing method thereof of the present invention will be described below with reference to the accompanying drawings.

[0038] Figure 1 It is a schematic diagram of the structure of NWELL, POLY, and AA forming resistors separately in the prior art;

[0039] Figure 2 A schematic top view of a high-resistance resistor structure according to a preferred embodiment of the present invention;

[0040] Figure 3 A schematic cross-sectional view of a high-resistance resistor structure according to a preferred embodiment of the present invention;

[0041] Figure 4 A schematic top view of a high-resistance resistor structure according to another preferred embodiment of the present invention;

[0042] Figure 5 A schematic cross-sectional view of a high-resistance resistor structure according to another preferred embodiment of the present invention;

[0043] Figure 6 A schematic top view of a high-resistance resistor structure according to another preferred embodiment of the present invention;

[0044] Figure 7 A schematic diagram of a resistor structure layout circuit according to a preferred embodiment of the present invention;

[0045] Figure 8 A schematic diagram of a resistor structure layout circuit according to another preferred embodiment of the present invention;

[0046] Fig. 9 The present invention is a flowchart of a method for manufacturing a high-resistance resistor according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0047] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. In order to avoid confusing the essence of the present invention, known methods, processes, procedures, and components are not described in detail.

[0048] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0049] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprising" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0050] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0051] like Figure 2 and 3 As shown, a high resistance resistor structure according to a preferred embodiment of the present invention is applied in an integrated circuit, comprising:

[0052] Substrate 5;

[0053] The first resistor layer 1 is directly arranged in the substrate 5, the upper surface of the first resistor layer 1 is flush with the upper surface of the substrate 5, and at least two first metal vias 11 are arranged on the upper surface of the first resistor layer 1; the figure shows 6 first metal vias 11, 3 of which are arranged on the right side of the first resistor layer, and the other 3 are arranged on the left side of the first resistor layer, and the 6 first metal vias 11 are connected to other electrical devices through the second resistor layer 2 and the first metal vias 11. Among them, flush means that when the first resistor layer 1 is arranged in the substrate 5, it is not completely wrapped by the substrate 5, but the upper surface of the first resistor layer 1 is exposed outside the substrate 5 and is flush with the upper surface of the substrate 5.

[0054] The second resistor layer 2 is directly arranged in the first resistor layer 1, the upper surface of the second resistor layer 2 is flush with the upper surface of the first resistor layer 1, and at least two second metal vias 21 are arranged above the upper surface of the second resistor layer 2; similarly, flush means that when the second resistor layer 2 is arranged in the first resistor layer 1, it is not completely wrapped by the first resistor layer 1, but the upper surface of the second resistor layer 2 is exposed outside the first resistor layer 1 and is flush with the upper surface of the first resistor layer 1.

[0055] A metal layer 4, the metal layer 4 is laid on the upper surface formed by the substrate 5, the first resistor layer 1 and the second resistor layer 2, and above the at least two second metal vias 21;

[0056] The first resistance layer 1 and the second resistance layer 2 are connected in series through the first metal via 11 , the second metal via 21 and the metal layer 4 .

[0057] The present invention uses a stacking method to produce a new resistor structure, in which the first resistor layer is a bottom resistor body, and the second resistor layer is an intermediate resistor body. The first resistor layer and the second resistor layer are connected in series through metal vias and metal layers to obtain a high-resistance structure. Multiple layers of resistive materials are stacked in a unit area, and metal vias are added. High-resistance resistors are formed in series with metal wires, which are suitable for different circuit adaptation scenarios. The new resistor structure provided by this solution has a higher resistance value per unit area, saving chip area.

[0058] In a preferred embodiment, the at least two first metal vias are respectively arranged at both side ends of the first resistor layer, and the at least two second metal vias are respectively arranged at both side ends of the second resistor layer, wherein a first metal via is connected to a second metal via through the metal layer, and another first metal via and another second metal via are used to electrically connect to a circuit outside the resistor structure. Figure 2 In the figure, the three first metal vias 11 at the right end of the first resistor layer 1 are electrically connected to the three second metal vias 21 at the right end of the second resistor layer 2 through the metal layer 4, and the three first metal vias 11 at the left end of the first resistor layer 1 and the three second metal vias 21 at the left end of the second resistor layer 2 are respectively used to be electrically connected to circuits outside the resistor structure through the metal layer 4.

[0059] In a preferred embodiment, the first resistor layer 1 is a NWELL resistor layer, and the second resistor layer 2 is an AA resistor layer.

[0060] In a preferred embodiment, Figure 4 As shown in FIG. 1 , the high-resistance resistor structure of the present invention further includes a third resistor layer 3, which is directly disposed on the upper surface of the second resistor layer 2, and the upper surface of the third resistor layer 3 is provided with at least two third metal vias 31; the first resistor layer 1, the second resistor layer 2 and the third resistor layer 3 are connected in series through the first metal via 11, the second metal via 21, the third metal via 31 and the metal layer 4. By adding a third resistor layer, the resistance value is further increased, a resistor with a higher resistance value can be obtained, and the chip area can be further saved.

[0061] In a preferred embodiment, the third resistor layer may be a Poly resistor.

[0062] In a preferred embodiment, one of the first metal vias is connected to one of the second metal vias through the metal layer, another of the second metal vias is connected to one of the third metal vias through the metal layer, and another of the third metal vias and another of the first metal vias are used to electrically connect to a circuit other than the resistor structure. Figure 5 As shown, the first metal via 11 on the right side of the first resistor layer 1 is electrically connected to the second metal via 21 on the right side of the second resistor layer 2 through the metal layer 4, the second metal via 21 on the left side of the second resistor layer 2 is electrically connected to the third metal via 31 on the left side of the third resistor layer through the metal layer 4, and the first metal via 11 on the left side of the first resistor layer 1 and the third metal via 31 on the right side of the third resistor layer 3 are used to electrically connect to circuits outside the resistor structure through metal layers.

[0063] In a preferred embodiment, Figure 6 As shown, the area of ​​the third resistor layer 3 is larger than the area of ​​the first resistor layer 1, and the third metal via 31 is arranged in a portion of the third resistor layer 3 that is larger than the first resistor layer 1. In the figure, the third metal vias 31 on the third resistor layer are symmetrically distributed up and down, so that the design will not affect the result of the DRC (Design Rule Check) rule check.

[0064] The present invention further discloses a resistor structure layout circuit, comprising a plurality of high-resistance resistor structures according to any one of the present inventions, wherein the plurality of high-resistance resistor structures are connected through the first metal via, the second metal via, the metal layer and / or the third metal via. Figure 7 and 8 As shown, the high-resistance resistor structures of the present invention are connected in series through a metal layer to obtain a layout structure in which four resistor structures are connected in series.

[0065] The invention also discloses an integrated circuit, comprising the resistor structure layout circuit of the invention.

[0066] The present invention also discloses a method for manufacturing a high-resistance resistor, which is applied to integrated circuits, such as Fig. 9 As shown, the steps include:

[0067] S100, performing well implantation in a substrate to form a first resistance layer, wherein an upper surface of the first resistance layer is flush with an upper surface of the substrate, and at least two first metal vias are provided on the upper surface of the first resistance layer;

[0068] S200, forming a second resistance layer in the first resistance layer by deposition and etching, wherein the upper surface of the second resistance layer is flush with the upper surface of the first resistance layer, and at least two second metal vias are provided above the upper surface of the second resistance layer;

[0069] S300, etching and depositing a metal layer above the upper surface formed by the first substrate, the first resistance layer, and the second resistance layer, and above the at least two second metal vias;

[0070] The first resistance layer and the second resistance layer are connected in series through the first metal via, the second metal via and the metal layer.

[0071] In a preferred embodiment, the at least two first metal vias are respectively arranged at the two side ends of the first resistance layer, and the at least two second metal vias are respectively arranged at the two side ends of the second resistance layer, wherein a first metal via is connected to a second metal via through the metal layer.

[0072] In a preferred embodiment, the first resistor layer is a NWELL resistor layer, and the second resistor layer is an AA resistor layer.

[0073] In a preferred embodiment, the high-resistance resistor manufacturing method of the present invention also includes step S400, forming a third resistance layer on the upper surface of the second resistance layer by deposition and etching, and providing at least two third metal vias on the upper surface of the third resistance layer; the first resistance layer, the second resistance layer and the third resistance layer are connected in series through the first metal via, the second metal via, the third metal via and the metal layer.

[0074] In a preferred embodiment, the third resistor layer is a Poly resistor.

[0075] In a preferred embodiment, one of the first metal vias is connected to one of the second metal vias through the metal layer, and another of the second metal vias is connected to one of the third metal vias through the metal layer, wherein another of the third metal vias and another of the first metal vias are used to electrically connect to circuits outside the resistor structure.

[0076] In a preferred embodiment, the area of ​​the third resistor layer is set to be larger than the area of ​​the first resistor layer, and the third metal via is set in a portion of the third resistor layer that is larger than the first resistor layer.

[0077] It will be appreciated by those skilled in the art that, under the premise of no conflict, the above-mentioned preferred solutions can be freely combined and superimposed. Among them, the flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings, for example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. The numbering of each step in this article is only for the convenience of description and reference, and is not used to limit the order of execution. The specific execution order is determined by the technology itself, and those skilled in the art can determine various allowable and reasonable orders based on the technology itself.

[0078] It should be noted that the use of step numbers (letters or numbers) to refer to certain specific method steps in the present invention is only for the purpose of convenience and brevity of description, and is by no means intended to limit the order of these method steps by letters or numbers. Those skilled in the art will understand that the order of the relevant method steps should be determined by the technology itself and should not be inappropriately limited by the existence of step numbers. Those skilled in the art can determine various permissible and reasonable step orders based on the technology itself.

[0079] Those skilled in the art will appreciate that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0080] It should be understood that the above-mentioned embodiments are merely illustrative and not restrictive. Without departing from the basic principles of the present invention, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will all be included in the scope of the claims of the present invention.

Claims

1. A high resistance resistor structure, used in an integrated circuit, characterized in that: include: substrate; A first resistance layer, wherein the first resistance layer is directly disposed in the substrate, an upper surface of the first resistance layer is flush with an upper surface of the substrate, and at least two first metal vias are disposed on the upper surface of the first resistance layer; a second resistor layer, wherein the second resistor layer is directly disposed in the first resistor layer, an upper surface of the second resistor layer is flush with an upper surface of the first resistor layer, and at least two second metal vias are disposed above the upper surface of the second resistor layer; A metal layer, the metal layer being laid above the upper surface formed by the substrate, the first resistance layer and the second resistance layer, and above the at least two second metal vias; The first resistance layer and the second resistance layer are connected in series through the first metal via, the second metal via and the metal layer.

2. The high resistance resistor structure according to claim 1, characterized in that: The at least two first metal vias are respectively arranged at both side ends of the first resistance layer, and the at least two second metal vias are respectively arranged at both side ends of the second resistance layer. Among them, a first metal via and a second metal via are connected through the metal layer, and another first metal via and another second metal via are used to be electrically connected to a circuit outside the resistor structure.

3. The high resistance resistor structure according to claim 1, characterized in that: The first resistance layer is a NWELL resistance layer, and the second resistance layer is an AA resistance layer.

4. The high resistance resistor structure according to claim 1, characterized in that: Also comprising a third resistance layer, The third resistance layer is directly disposed on the upper surface of the second resistance layer, and at least two third metal vias are disposed on the upper surface of the third resistance layer; The first resistance layer, the second resistance layer, and the third resistance layer are connected in series through the first metal via, the second metal via, the third metal via, and the metal layer.

5. The high resistance resistor structure according to claim 4, characterized in that: The third resistor layer is a Poly resistor.

6. The high resistance resistor structure according to claim 4, characterized in that: A first metal via is connected to a second metal via through the metal layer, another second metal via is connected to a third metal via through the metal layer, and another third metal via and another first metal via are used to electrically connect to circuits outside the resistor structure.

7. The high resistance resistor structure according to claim 4, characterized in that: The area of ​​the third resistance layer is larger than that of the first resistance layer, and the third metal via is disposed in a portion of the third resistance layer that is larger than that of the first resistance layer.

8. A resistor structure layout circuit, characterized in that: It comprises a plurality of high-resistance resistor structures as described in any one of claims 1 to 7, wherein the plurality of high-resistance resistor structures are connected through the first metal via, the second metal via, the metal layer and / or the third metal via.

9. An integrated circuit, characterized in that: Comprising the resistor structure layout circuit as described in claim 8.

10. A method for manufacturing a high-resistance resistor, used in an integrated circuit, characterized in that: Includes steps: S100, performing well implantation in a substrate to form a first resistance layer, wherein an upper surface of the first resistance layer is flush with an upper surface of the substrate, and at least two first metal vias are provided on the upper surface of the first resistance layer; S200, forming a second resistance layer in the first resistance layer by deposition and etching, wherein the upper surface of the second resistance layer is flush with the upper surface of the first resistance layer, and at least two second metal vias are provided above the upper surface of the second resistance layer; S300, etching and depositing a metal layer above the upper surface formed by the first substrate, the first resistance layer, and the second resistance layer, and above the at least two second metal vias; The first resistance layer and the second resistance layer are connected in series through the first metal via, the second metal via and the metal layer.

11. The method for manufacturing a high-resistance resistor according to claim 10, characterized in that: The at least two first metal vias are respectively arranged at the two side ends of the first resistance layer, and the at least two second metal vias are respectively arranged at the two side ends of the second resistance layer, Wherein, a first metal via is connected to a second metal via through the metal layer.

12. The resistor manufacturing method according to claim 10, characterized in that: The first resistance layer is a NWELL resistance layer, and the second resistance layer is an AA resistance layer.

13. The method for manufacturing a high-resistance resistor according to claim 10, characterized in that: The method further comprises step S400 of forming a third resistance layer on the upper surface of the second resistance layer by deposition and etching, and providing at least two third metal vias on the upper surface of the third resistance layer; The first resistance layer, the second resistance layer, and the third resistance layer are connected in series through the first metal via, the second metal via, the third metal via, and the metal layer.

14. The method for manufacturing a high-resistance resistor according to claim 13, characterized in that: The third resistor layer is a Poly resistor.

15. The method for manufacturing a high-resistance resistor according to claim 13, characterized in that: A first metal via is connected to a second metal via through the metal layer, and another second metal via is connected to a third metal via through the metal layer, wherein another third metal via and another first metal via are used to electrically connect to circuits outside the resistor structure.

16. The method for manufacturing a high-resistance resistor according to claim 13, characterized in that: The area of ​​the third resistance layer is set to be larger than the area of ​​the first resistance layer, and the third metal via is set in a portion of the third resistance layer that is larger than the first resistance layer.

Images