Low-groove and high-power MOS (Metal Oxide Semiconductor) device

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a low-groove high-power MOS device which comprises a plurality of MOS cells which are arranged in parallel, and each MOS cell comprises a metal source electrode, a grid electrode, a semiconductor epitaxial layer and a drain electrode; wherein the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and an N well layer; the N-well layer comprises a heavily doped N-well layer I and a lightly doped N-well layer II; the P well layer comprises a heavily doped P well layer I, a heavily doped P well layer II, a heavily doped P well layer III, a lightly doped P well layer I and a lightly doped P well layer II. According to the invention, the lightly-doped P-well layers are arranged at the left and right lower corners of the gate, so that the phenomenon that the lightly-doped P-well layers and the gate oxide layer are punctured together in the background is avoided, and the stable use of the MOS device in high-power equipment is realized.

Description

Technical Field

[0001] The invention relates to the technical field of MOS semiconductors, and more particularly to a low-groove high-power MOS device. Background Art

[0002] Low-trench high-power MOS devices generally refer to a class of specially designed metal oxide semiconductor field effect transistors. The devices are able to handle higher power levels without damage. The MOS devices are very important in many fields, especially in power electronics applications such as power converters, electric vehicles (EVs), industrial drives, and motor control.

[0003] The existing patent discloses a high-frequency, high-power trench MOS field effect transistor (publication number CN206179872U), which makes a hole in the unit cell of the trench MOS field effect transistor so that the source metal is in full contact with the field polysilicon in the trench. In the technology disclosed in the patent, when the potential difference between the gate and the metal source is too large, there will be a transitional accumulation of charges in the P-well layer, resulting in the phenomenon of breaking down the P-well layer together with the gate oxide layer. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a low-trench high-power MOS device, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a low-trench high-power MOS device is provided, comprising a plurality of MOS cells arranged in parallel with each other, wherein the MOS cell comprises a metal source, a gate, a semiconductor epitaxial layer and a drain;

[0006] Wherein, the semiconductor epitaxial layer includes a substrate layer, a diffusion layer, a P-well layer and an N-well layer;

[0007] The N-well layer includes a heavily doped N-well layer 1 and a lightly doped N-well layer 2;

[0008] The P-well layer includes a heavily doped P-well layer 1, a heavily doped P-well layer 2, a heavily doped P-well layer 3, a lightly doped P-well layer 1 and a lightly doped P-well layer 2;

[0009] The lightly doped P-well layer 2 is located below the gate;

[0010] The diffusion layer includes a lightly doped N well layer 1, a lightly doped N well layer 4, a heavily doped N well layer 3 and a heavily doped N well layer 4;

[0011] When the gate is connected to the gate voltage, a potential difference is formed between the lightly doped P-well layer 2 and the gate, and a charge channel is formed inside the lightly doped P-well layer 2 near the gate position, and a conduction current is formed between the diffusion layer and the N-well layer through the charge channel.

[0012] Furthermore, a gate oxide layer is deposited on the surface of the gate.

[0013] Furthermore, the heavily doped N-well layer 1 and the lightly doped N-well layer 2 are both in ohmic contact with the metal source.

[0014] Furthermore, the lightly-doped N-well layer four of the single MOS cell is located on the left and right sides of the heavily-doped N-well layer three, and the cross-sectional profile of the lightly-doped N-well layer four is in the shape of a right-angled triangle.

[0015] Furthermore, the left-right spacing of the cross-sectional profiles of the heavily doped N-well layer 3 and the heavily doped N-well layer 4 is the same, and the top-bottom spacing of the cross-sectional profiles of the heavily doped N-well layer 4 and the lightly doped P-well layer 2 is the same.

[0016] Furthermore, the cross-sectional profile of the heavily doped N-well layer 1 is wide at the top and narrow at the bottom, and the spacing between the narrow ends of the heavily doped N-well layer 1 is the same as the spacing between the lightly doped P-well layer 2.

[0017] Furthermore, a heavily doped N well layer 2 and a lightly doped N well layer 3 are provided at the junction of the substrate layer and the lightly doped N well layer 1;

[0018] The heavily doped N-well layer 2 and the lightly doped N-well layer 3 between adjacent MOS cells are integrated into one, and the cross-sectional profiles of the heavily doped N-well layer 2 and the lightly doped N-well layer 3 are elliptical.

[0019] Furthermore, the heavily-doped N-well layer 2 is located on one side of the lightly-doped N-well layer 1, and the lightly-doped N-well layer 3 is located on one side of the substrate layer.

[0020] The beneficial effects of a low-trench high-power MOS device of the present invention are:

[0021] 1. The present invention arranges the lightly doped P-well layer at the left and right lower corners of the gate, thereby avoiding the phenomenon of breakdown of the lightly doped P-well layer together with the gate oxide layer as described in the background, thereby achieving stable use of MOS devices in high-power equipment.

[0022] 2. The present invention reduces the risk of local cell damage caused by process deviation in the device by forming a light and heavy doping alternating structure as shown in the figure at the interface between the substrate and the epitaxial layer.

[0023] 3. The present invention forms a highly doped heavily doped N well layer 4 by ion implantation between two adjacent lightly doped P well layers 2. This design of forming the heavily doped N well layer 4 by implantation can effectively reduce the on-resistance of the charge channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] Figure 1 It is a structural schematic diagram of a MOS device;

[0026] Figure 2 It is a schematic diagram of conduction near the channel in the present invention;

[0027] Figure 3 Schematic diagram of the double-cell parallel structure.

[0028] In the figure: 1. Metal source; 2. Gate; 3. Drain; 4. Substrate layer; 5. Lightly doped N-well layer 1; 6. Gate oxide layer; 7. Heavily doped N-well layer 1; 8. Lightly doped N-well layer 2; 9. Heavily doped P-well layer 1; 10. Heavily doped P-well layer 2; 11. Heavily doped P-well layer 3; 12. Heavily doped N-well layer 2; 13. Lightly doped N-well layer 3; 14. Lightly doped P-well layer 1; 15. Lightly doped P-well layer 2; 16. Lightly doped N-well layer 4; 17. Heavily doped N-well layer 3; 18. Heavily doped N-well layer 4. DETAILED DESCRIPTION

[0029] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0030] like Figure 1-3 As shown, according to one aspect of the present invention, a low-trench high-power MOS device is provided, comprising a plurality of MOS cells arranged in parallel, the MOS cell comprising a metal source 1, a gate 2, a semiconductor epitaxial layer and a drain 3; a gate oxide layer 6 is deposited on the surface of the gate 2, and the gate oxide layer 6 is used to isolate the gate 2 from contact with the metal source 1, the P-well layer and the N-well layer.

[0031] Among them, the semiconductor epitaxial layer includes a substrate layer 4, a diffusion layer, a P-well layer and an N-well layer; the N-well layer includes a heavily doped N-well layer 1 7 and a lightly doped N-well layer 2 8; the P-well layer includes a heavily doped P-well layer 1 9, a heavily doped P-well layer 2 10, a heavily doped P-well layer 3 11, a lightly doped P-well layer 1 14 and a lightly doped P-well layer 2 15; the lightly doped P-well layer 2 15 is located below the gate 2; the diffusion layer includes a lightly doped N-well layer 1 5, a lightly doped N-well layer 4 16, a heavily doped N-well layer 3 17 and a heavily doped N-well layer 4 18; the lightly doped P-well layer 2 15 is arranged directly below the gate 2, at which time the gate electric field of the charge channel formed will be weakened by the drain voltage, and this weakening can ensure that the lightly doped P-well layer 2 15 will not be broken down after the gate voltage is continuously increased, thereby achieving the stability of the MOS device used in high-power equipment.

[0032] When the gate 2 is connected to the gate voltage, a potential difference is formed between the lightly doped P-well layer 15 and the gate 2. A charge channel is formed inside the lightly doped P-well layer 15 near the gate 2. A conduction current is formed between the diffusion layer and the N-well layer through the charge channel (e.g. Figure 1 As shown), after the gate 2 is connected to the gate voltage and the metal source 1 is connected to the negative voltage, a gate electric field will be formed in the lightly doped P-well layer 15, so that the electrons inside the P-well layer will gather toward the gate 2 to form a charge channel, so that the electron flow of the metal source 1 can enter the N-well layer, and then enter the diffusion layer and the drain 3 through the charge channel.

[0033] In this embodiment, the heavily doped N well layer 1 7 and the lightly doped N well layer 2 8 are both in ohmic contact with the metal source 1, and the lightly doped N well layer 4 16 of a single MOS cell is located on the left and right sides of the heavily doped N well layer 3 17, and the cross-sectional profile of the lightly doped N well layer 4 16 is in the shape of a right triangle (such as Figure 1 As shown), since the doping concentration of the lightly doped N-well layer 16 is lower than that of the heavily doped N-well layer 17 in the middle, it can ensure that the charges in the diffusion layer mainly flow along the heavily doped N-well layer 17, thereby reducing the overall on-resistance of the MOS device.

[0034] In this embodiment, the left-right spacing of the cross-sectional profiles of the heavily doped N well layer three 17 and the heavily doped N well layer four 18 is the same, the top-bottom spacing of the cross-sectional profiles of the heavily doped N well layer four 18 and the lightly doped P well layer two 15 is the same, the cross-sectional profile of the heavily doped N well layer one 7 is wide at the top and narrow at the bottom, and the narrow end spacing of the heavily doped N well layer one 7 is the same as that of the lightly doped P well layer two 15.

[0035] In this embodiment, a heavily doped N-well layer 2 12 and a lightly doped N-well layer 3 13 are provided at the junction of the substrate layer 4 and the lightly doped N-well layer 1 5; wherein the heavily doped N-well layer 2 12 and the lightly doped N-well layer 3 13 between adjacent MOS cells are integrated, and the cross-sectional profiles of the heavily doped N-well layer 2 12 and the lightly doped N-well layer 3 13 are elliptical, the heavily doped N-well layer 2 12 is located on one side of the lightly doped N-well layer 1 5, and the lightly doped N-well layer 3 13 is located on one side of the substrate layer 4 (such as Figure 3 As shown), ions are implanted at the junction of the substrate layer 4 and the diffusion layer to form a heavily doped N well layer 2 12 and a lightly doped N well layer 3 13, and the heavily doped N well layer 2 12 is located at a high position and the lightly doped N well layer 2 13 is located at a low position. This design can constrain the charge to flow mainly along the middle part of the diffusion layer.

[0036] like Figure 3As shown, the present invention arranges a lightly doped P-well (including a lightly doped P-well layer 14 and a lightly doped P-well layer 2 15) at the left and right lower corners of the gate 2, and arranges a P+ region (including a heavily doped P-well layer 9, a heavily doped P-well layer 2 10 and a heavily doped P-well layer 3 11) therebelow. When the device is turned on, the lightly doped P-well is restricted by the source electric field, and the electric field at the channel is restricted by the P-well, thereby weakening the influence of the gate electric field on the gate oxide and the lightly doped P-well, avoiding the phenomenon of the lightly doped P-well layer and the gate oxide layer being broken down together in the background technology; at the same time, due to the existence of the P+ region, the channel will not be completely out of gate voltage control, thereby causing the problem of reduced device gate control capability.

[0037] By forming a lightly and heavily alternating doped structure (heavily doped N-well layer 2 12 and lightly doped N-well layer 3 13) at the interface between the substrate layer 4 and the epitaxial layer as shown in the figure, the movement of charges is constrained so that the charges can flow mainly within their respective cells in different regions, thereby reducing the risk of local cell damage caused by process deviations in the device.

[0038] Injecting a higher concentration current spreading layer into the JFET region can effectively reduce the resistance of the JFET region of the device, thereby reducing the overall on-resistance of the device.

[0039] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A low-trench high-power MOS device, characterized in that: It is composed of a plurality of MOS cells arranged in parallel with each other, wherein the MOS cell comprises a metal source (1), a gate (2), a semiconductor epitaxial layer and a drain (3); Wherein, the semiconductor epitaxial layer comprises a substrate layer (4), a diffusion layer, a P-well layer and an N-well layer; The N-well layer comprises a heavily doped N-well layer 1 (7) and a lightly doped N-well layer 2 (8); The P-well layer includes a heavily doped P-well layer 1 (9), a heavily doped P-well layer 2 (10), a heavily doped P-well layer 3 (11), a lightly doped P-well layer 1 (14) and a lightly doped P-well layer 2 (15); The lightly doped P well layer 2 (15) is located below the gate (2); The diffusion layer includes a lightly doped N well layer 1 (5), a lightly doped N well layer 4 (16), a heavily doped N well layer 3 (17) and a heavily doped N well layer 4 (18); When the gate (2) is connected to the gate voltage, a potential difference is formed between the lightly doped P-well layer 2 (15) and the gate (2), and a charge channel is formed inside the lightly doped P-well layer 2 (15) near the gate (2), and a conduction current is formed between the diffusion layer and the N-well layer through the charge channel.

2. The low-trench high-power MOS device according to claim 1, characterized in that: A gate oxide layer (6) is deposited on the surface of the gate (2).

3. The low-trench high-power MOS device according to claim 1, characterized in that: The heavily doped N-well layer 1 (7) and the lightly doped N-well layer 2 (8) are both in ohmic contact with the metal source electrode (1).

4. The low-trench high-power MOS device according to claim 1, characterized in that: The lightly doped N-well layer four (16) of a single MOS cell is located on the left and right sides of the heavily doped N-well layer three (17), and the cross-sectional profile of the lightly doped N-well layer four (16) is in the shape of a right triangle.

5. The low-trench high-power MOS device according to claim 4, characterized in that: The left-right spacing of the cross-sectional profiles of the heavily doped N-well layer three (17) and the heavily doped N-well layer four (18) is the same, and the top-bottom spacing of the cross-sectional profiles of the heavily doped N-well layer four (18) and the lightly doped P-well layer two (15) is the same.

6. The low-trench high-power MOS device according to claim 5, characterized in that: The cross-sectional profile of the heavily doped N-well layer 1 (7) is wide at the top and narrow at the bottom, and the spacing between the narrow ends of the heavily doped N-well layer 1 (7) is the same as the spacing between the lightly doped P-well layer 2 (15).

7. The low-trench high-power MOS device according to claim 1, characterized in that: A heavily doped N well layer 2 (12) and a lightly doped N well layer 3 (13) are provided at the junction of the substrate layer (4) and the lightly doped N well layer 1 (5); The heavily doped N-well layer 2 (12) and the lightly doped N-well layer 3 (13) between adjacent MOS cells are integrated into one, and the cross-sectional profiles of the heavily doped N-well layer 2 (12) and the lightly doped N-well layer 3 (13) are elliptical.

8. The low-trench high-power MOS device according to claim 7, characterized in that: The heavily doped N well layer 2 (12) is located on one side of the lightly doped N well layer 1 (5), and the lightly doped N well layer 3 (13) is located on one side of the substrate layer (4).

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