High-voltage semiconductor device and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a high-voltage semiconductor device and a manufacturing method thereof. The channel region and the drain region are formed in the semiconductor substrate; the drain electrode and the source region are formed in the drain region; the source electrode is formed in the source region; the grid electrode is formed on the semiconductor substrate and is positioned above the channel region; the first isolation region is formed in the drain region and is positioned between the drain electrode and the grid electrode; the grid electrode is communicated with the grid electrode and is used for connecting the grid electrode with an external control circuit; one end of the virtual gate sinks into the first isolation region, and the other end of the virtual gate is communicated with the gate electrode to form an independent MOS (Metal Oxide Semiconductor); and the work function layer is formed on the surface of the virtual gate. According to the high-voltage semiconductor device provided by the invention, the problem that the consideration optimization of the source-drain breakdown voltage and the on-resistance of the high-voltage semiconductor device in the prior art is limited can be solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-voltage semiconductor device and a manufacturing method thereof. Background Art

[0002] Metal-oxide-semiconductor field-effect transistor (MOS) is the most basic device in semiconductor manufacturing and is widely used in various integrated circuits. It is divided into NMOS transistors and PMOS transistors according to the different carriers and doping types during manufacturing.

[0003] In the process of manufacturing high-voltage semiconductor devices, a shallow trench isolation structure is added between the gate and the drain to increase the length between the drain and the source and improve the source-drain breakdown voltage BVD of the high-voltage semiconductor device. Although such a setting can increase the source-drain breakdown voltage, the presence of the shallow trench isolation structure STI increases the carrier movement trajectory, resulting in an increase in the on-resistance R of the high-voltage semiconductor device when it is turned on. on Increase, reducing device performance. Summary of the invention

[0004] The purpose of the present invention is to provide a high-voltage semiconductor device and a method for manufacturing the same, which is used to solve the problem of limited optimization of both source-drain breakdown voltage and on-resistance of high-voltage semiconductor devices in the prior art.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides a high voltage semiconductor device, comprising: Semiconductor substrate; A channel region, a drain region, and a drain electrode formed in the drain region, a source region, and a source electrode formed in the source region formed in the semiconductor substrate, wherein the drain region and the source region are of a first conductivity type, and the semiconductor substrate and the channel region are of a second conductivity type; a gate formed on the semiconductor substrate and located above the channel region; A first isolation region formed in the drain region and located between the drain electrode and the gate; a gate electrode, connected to the gate and used to connect the gate to an external control circuit; A dummy gate, one end of which is sunken into the first isolation region and the other end of which is connected to the gate electrode to form an independent MOS, and the gate and the dummy gate are connected to form a closed loop structure; A work function layer is formed on the surface of the virtual gate.

[0006] Preferably, the virtual gate is formed by extending the material forming the gate electrode toward the first isolation region and sinking into the first isolation region, and is an integral structure with the gate electrode.

[0007] Preferably, a protective layer covering the source, the gate and the drain is formed on the surface of the semiconductor substrate, an interlayer dielectric layer is formed on the protective layer, and the gate electrode includes a main section formed on the upper part of the interlayer dielectric layer and an extension section penetrating the interlayer dielectric layer and the protective layer; the upper end of the extension section is connected to the main section, and the lower end of the extension section is connected to a virtual gate sunk into the first isolation region; the gate electrode is electrically connected to the gate through a first conductive plug.

[0008] Preferably, the work function layer extends from the virtual gate surface to the gate electrode surface along the overall structure.

[0009] Preferably, it also includes a lightly doped region formed in the semiconductor substrate and a heavily doped region formed on the upper part of the lightly doped region, the lightly doped region and the heavily doped region are of the second conductivity type; the lightly doped region is arranged around the outside of the drain region and the source region, and the heavily doped region is connected to the lead-out electrode through a second conductive plug.

[0010] In a second aspect, the present invention provides a method for manufacturing a high-voltage semiconductor device, comprising: An intermediate semiconductor structure is provided, the intermediate semiconductor structure comprising a semiconductor substrate, a channel region, a drain region, a drain electrode formed in the drain region, a source region, and a source electrode formed in the source region are formed in the semiconductor substrate; a gate electrode is formed on the surface of the channel region; the source region and the drain region are of a first conductivity type, and the semiconductor substrate and the channel region are of a second conductivity type; a first isolation region is formed in the drain region, and the first isolation region is located between the drain electrode and the gate electrode; A protection layer covering the source, the gate and the drain is formed on the intermediate semiconductor structure, an interlayer dielectric layer is formed on the protection layer, the interlayer dielectric layer is etched to form a first groove body accommodating a gate electrode, and an electrode material is deposited in the first groove body to form the gate electrode, the gate electrode is connected to the gate, and is used to connect the gate to an external control circuit; The interlayer dielectric layer is etched and extended into the first isolation region to form a receiving groove, a work function layer is formed on the groove wall of the receiving groove, an electrode material is deposited on the work function layer to form a virtual gate, and the virtual gate is connected to the gate electrode to form an independent MOS, and the gate and the virtual gate are connected to form a closed-loop structure.

[0011] Preferably, the gate electrode and the virtual gate are formed by integral deposition, that is, firstly, a first groove body for accommodating the gate electrode and a receiving groove for accommodating the virtual gate are simultaneously formed by etching, the first groove body includes a main body and an extension portion extending toward the receiving groove to be interconnected, the main body is formed on the upper part of the interlayer dielectric layer by etching, the extension portion passes through the interlayer dielectric layer and the protective layer to the first isolation region by etching, and the receiving groove is sunk into the first isolation region by etching; then, a work function layer is synchronously deposited on the main body, the extension portion and the inner wall of the receiving groove; and then, an electrode material is synchronously deposited on the work function layer to form the gate electrode and the virtual gate.

[0012] Preferably, the method further comprises: a first conductive plug is formed in the interlayer dielectric layer and the protective layer, the lower end of the first conductive plug is connected to the gate, and the upper end of the first conductive plug is electrically connected to the gate electrode.

[0013] Preferably, the method further comprises: performing ion implantation on the outer sides of the drain region and the source region in the semiconductor substrate to form a lightly doped region, and forming a heavily doped region on the upper surface of the lightly doped region by ion implantation, wherein the lightly doped region and the heavily doped region are of the second conductivity type; A second conductive plug is formed in the interlayer dielectric layer and the protective layer, the lower end of the second conductive plug is connected to the heavily doped region, and the upper end of the second conductive plug is electrically connected to the lead-out electrode.

[0014] Preferably, the manufacturing of the intermediate semiconductor structure comprises: Providing a semiconductor substrate; forming a well region on the semiconductor substrate, wherein the well region is of a second conductivity type; Etching the well region to form a shallow trench, and filling the shallow trench to obtain a first isolation region; Performing ion implantation on both sides of the first isolation region to form a source region and a drain region, wherein a channel region not implanted with ions is reserved between the source region and the first isolation region, the source region and the drain region are of the first conductivity type, and the channel region is of the second conductivity type; A gate is formed on the channel region, a source is formed in the source region, and a drain is formed in the drain region.

[0015] The unexpected beneficial effects of the present invention are as follows: The high-voltage semiconductor device of the present invention is designed with a unique virtual gate structure, one end of the virtual gate is sunk into the first isolation region, and the other end is connected to the gate electrode to form an independent MOS, that is, a MOS independent of the gate (i.e., the main gate). At the same time, a work function layer is arranged on the outer surface of the virtual gate to ensure that the gate (i.e., the main gate) and the virtual gate can work synchronously under the same voltage condition. In this way, the virtual gate and the work function layer are arranged at the same time. When a turn-on voltage is applied to the gate, the virtual gate connected to the gate can quickly absorb the electrons in the drain region below the drain electrode to the interface between the first isolation region and the drain region and gather them, shortening the movement trajectory of the electrons and reducing the transmission time of the electrons in the drain region, thereby reducing the on-resistance of the device. And due to the existence of the first isolation region, the source-drain breakdown voltage is increased.

[0016] Based on the unique structure of the high-voltage semiconductor device of the present invention, it is possible to manufacture a metal work function layer having both NMOS and PMOS through a simple process flow, and connect the main gate structure with the metal virtual gate sunk into the STI without adding additional masks for the NMOS and PMOS metal work function layers, and the manufacturing process can be implemented entirely based on existing conditions, saving process costs.

[0017] In summary, the high-voltage semiconductor device provided by the present invention can solve the problem of limited optimization of both source-drain breakdown voltage and on-resistance of high-voltage semiconductor devices in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a high-voltage semiconductor device according to the present invention is shown.

[0019] Figure 2 The working principle diagram of the high-voltage semiconductor device of the present invention is shown.

[0020] Figure 3 A schematic diagram of etching a well region to form a shallow trench according to the present invention is shown.

[0021] Figure 4 FIG. 4 is a schematic diagram showing the present invention after forming an isolation region.

[0022] Figure 5 A schematic diagram is shown after the source region and the drain region are formed according to the present invention.

[0023] Figure 6 FIG. 4 is a schematic diagram showing the present invention after forming a gate.

[0024] Figure 7 The schematic diagram after forming the source and drain of the present invention is shown.

[0025] Figure 8 A schematic diagram showing the etching process for forming a conductive plug channel according to the present invention is shown.

[0026] Fig. 9 The schematic diagram of the present invention after forming the conductive plug is shown.

[0027] Fig.10 A schematic diagram of etching to form a groove body according to the present invention is shown.

[0028] Fig.11 A schematic diagram of the present invention after forming the tank body is shown.

[0029] Fig.12 A schematic diagram of etching to form a receiving groove according to the present invention is shown.

[0030] Fig.13 A schematic diagram showing the present invention after the receiving groove is formed.

[0031] Fig.14 The schematic diagram of the present invention after forming the lead-out electrode is shown.

[0032] In the figure, 1 is a semiconductor substrate, 2 is a channel region, 3 is a drain region, 4 is a drain electrode, 5 is a gate electrode, 6 is a first isolation region, 61 is a receiving groove, 7 is a gate electrode, 71 is a main section, 72 is an extension section, 8 is a virtual gate, 9 is a work function layer, 10 is an interlayer dielectric layer, 11 is a first conductive plug, 12 is a first groove body, 121 is a main section, 122 is an extension section, 13 is a source region, 14 is a source electrode, 15 is a shallow trench, 16 is a protective layer, 17 is a well region, 18 is a first sacrificial layer, 19 is a second sacrificial layer, 20 is a photoresist layer, 21 is a gate dielectric layer, 22 is a sidewall structure, 221 is a First silicon oxide layer, 222—first silicon nitride layer, 223—second silicon oxide layer, 224—second silicon nitride layer, 23—self-aligned metal silicide, 24—drain electrode, 25—source electrode, 26—third sacrificial layer, 27—conductive plug channel, 28—first barrier layer, 29—second barrier layer, 30—fourth sacrificial layer, 31—fifth sacrificial layer, 32—lightly doped region, 33—heavily doped region, 34—access electrode, 35—second conductive plug, 36—third conductive plug, 37—fourth conductive plug, 38—second isolation region, 39—second trough body, 40—third trough body. DETAILED DESCRIPTION

[0033] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0034] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0036] In one embodiment, please refer to Figure 1 As shown, a high voltage semiconductor device is provided, comprising: A semiconductor substrate 1, serving as a carrier base for a high-voltage semiconductor device; A channel region 2, a drain region 3, a drain electrode 4 formed in the drain region 3, a source region 13, and a source electrode 14 formed in the source region 13 are formed in the semiconductor substrate 1, the drain region 3 and the source region 13 are of a first conductivity type, and the semiconductor substrate 1 and the channel region 2 are of a second conductivity type;

[0037] A gate 5 formed on the semiconductor substrate 1 and located above the channel region 2; A first isolation region 6, formed in the drain region 3 and located between the drain electrode 4 and the gate electrode 5; A gate electrode 7, connected to the gate 5, and used to connect the gate 5 to an external control circuit; A virtual gate 8, one end of which is sunken into the first isolation region 6, and the other end of which is connected to the gate electrode 7, to form an independent MOS, and the gate 5 is connected to the virtual gate 8 to form a closed loop structure; The work function layer 9 is formed on the surface of the dummy gate 8 .

[0038] Since one end of the virtual gate 8 is sunk into the first isolation region 6 and the other end is connected to the gate electrode 7 to form an independent MOS, the insulating material of the first isolation region 6 below the virtual gate 8 is actually used as a dielectric layer, and the drain region 3 below the dielectric layer is used as a channel region, thereby forming an independent MOS. At the same time, the present invention sets a work function layer 9 on the outer surface of the virtual gate 8 to ensure that the gate 5 and the virtual gate 8 can work synchronously under the same voltage condition. Figure 2 As shown, due to the coordinated arrangement of the virtual gate 8 and the work function layer 9, when a turn-on voltage is applied to the gate 5, the virtual gate 8 connected to the gate 5 can, under the action of the turn-on voltage, synchronously and quickly absorb the electrons in the drain region 3 below the drain 4 to the interface between the first isolation region 6 and the drain region 3 and gather them, shortening the electron movement trajectory and reducing the transmission time of the electrons in the drain region 3, thereby reducing the on-resistance of the device. And due to the presence of the first isolation region 6 between the drain 4 and the gate 5, the source-drain breakdown voltage is increased. Therefore, the high-voltage semiconductor device provided by the present invention can solve the problem of limited optimization of the source-drain breakdown voltage and on-resistance of the high-voltage semiconductor device in the prior art.

[0039] It should be noted that the gate 5 and the dummy gate 8 are connected to form a closed loop structure, which means: Figure 1 As shown, when a turn-on voltage is applied to the gate 5, the channel region 2 in the semiconductor substrate 1 at the lower end of the gate 5 is turned on, the channel region 2 is turned on with the drain region 3 under the virtual gate 8, and the upper end of the gate 5 and the upper end of the virtual gate 8 are connected through the gate electrode 7, thereby forming a closed-loop structure.

[0040] In one embodiment, the semiconductor substrate 1 is single crystal silicon doped with impurities, and the impurity type in the semiconductor substrate 1 can be set according to the type of semiconductor device, and the semiconductor substrate 1 is doped to reduce the resistance of the semiconductor substrate 1 and prevent latch-up effect. Specifically, boron (B) or gallium (Ga) can be doped in the semiconductor substrate 1 to form a P-type doped substrate, and phosphorus (P) or arsenic (As) can be doped in the semiconductor substrate 1 to form an N-type doped substrate. N-type semiconductor devices can choose to use P-type semiconductor substrates, while P-type semiconductor devices can choose to use N-type semiconductor substrates. In other embodiments, depending on the different semiconductor devices, the semiconductor substrate 1 is selected from, for example, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire or other semiconductor materials formed by III / V compounds, and also includes a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator.

[0041] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. That is, the high-voltage semiconductor device in this embodiment is an N-type semiconductor device, and the semiconductor substrate 1 uses a P-type semiconductor substrate.

[0042] As a preferred embodiment, see Figure 1 As shown, the virtual gate 8 is formed by the material forming the gate electrode 7 extending toward the first isolation region 6 and sinking into the first isolation region 6, that is, the virtual gate 8 is connected to the gate 5 through the gate electrode 7 to form a closed loop structure connected in series, which not only plays a role in regulating the device R on and I DS The closed-loop structure connects the gate 5 and the virtual gate 8 of the semiconductor device together, and cooperates with the setting of the work function layer 9 to ensure that the devices controlled by the gate 5 and the virtual gate 8 can work synchronously without delay. When the start-up voltage is applied to the gate 5, the virtual gate 8 will absorb a large number of electrons to the bottom area of ​​the first isolation region 6 between the drain 4 and the gate 5, which is equivalent to shortening the conduction channel of the gate 5, i.e., the main gate device, making it easier to turn on the high-voltage device, which is equivalent to lowering the threshold voltage V th The saturation current of the device is DS and threshold voltage V th is inversely proportional to the threshold voltage V th When the saturation current I DS will increase. Synchronously, the device’s on-resistance R on =V drain / I DS , V drain is the drain voltage. When the saturation current I DS When increasing, according to the physical formula R on Therefore, this structure and design can not only ensure the high breakdown voltage of the device, but also increase the saturation current of the device and reduce the on-resistance of the device, achieving a win-win effect.

[0043] As a preferred embodiment, see Figure 2 As shown, a protective layer 16 covering the source 14, the gate 5 and the drain 4 is formed on the surface of the semiconductor substrate 1, and an interlayer dielectric layer 10 is formed on the protective layer 16. The gate electrode 7 includes a main section 71 formed on the upper part of the interlayer dielectric layer 10 and an extension section 72 penetrating the interlayer dielectric layer 10 and the protective layer 16. The upper end of the extension section 72 is connected to the main section 71, and the lower end of the extension section 72 is connected to the virtual gate 8 sunk into the first isolation region 6. The gate electrode 7 is electrically connected to the gate 5 through a first conductive plug 11.

[0044] The interlayer dielectric layer 10 is mainly used to provide isolation, allowing different circuit components (such as the gate 5, the source 14, the drain 4, etc.) to work independently on the semiconductor substrate 1 without interfering with each other. The interlayer dielectric layer 10 is usually made of an insulating material, such as silicon dioxide (SiO2) or other dielectric materials.

[0045] In one embodiment, see Figure 2 As shown, the first conductive plug 11 is a vertical conductive channel for establishing electrical connection between different layers of the device. Here, the first conductive plug 11 passes through the interlayer dielectric layer 10 and the protective layer 16 to connect the main segment 71 of the gate electrode 7 with the gate 5 to ensure electrical connection between the two.

[0046] As a preferred embodiment, see Figure 1 As shown, the work function layer 9 extends from the surface of the virtual gate 8 along the overall structure to the surface of the gate electrode 7, that is, the work function layer 9 extends along the overall structure to the surface where the gate electrode 7 contacts the surrounding material, and is used to adjust the work function of the gate electrode 7, thereby ensuring that the gate 5 and the virtual gate 8 can work synchronously under the same voltage conditions.

[0047] As a preferred embodiment, see Fig.14 As shown, the high-voltage semiconductor device further includes a lightly doped region 32 formed in the semiconductor substrate 1 and a heavily doped region 33 formed on the upper portion of the lightly doped region 32, and the lightly doped region 32 and the heavily doped region 33 are of the second conductivity type. The lightly doped region (32) is arranged around the outer side of the drain region 3 and the source region 13, and the heavily doped region 33 is connected to the lead-out electrode 34 through a second conductive plug 35.

[0048] As a preferred embodiment, see Figure 1 As shown, the first isolation region 6 is a shallow trench isolation structure. The formation process is: a shallow trench 15 is formed by silicon etching technology, and then an insulating material, such as oxide, is filled in the shallow trench 15 to achieve the purpose of isolation. By forming the first isolation region 6 between the drain 4 and the gate 5 to increase the length between the drain 4 and the source 14, the source-drain breakdown voltage BVD of the high-voltage semiconductor device is increased, thereby improving the overall performance and reliability of the high-voltage semiconductor device.

[0049] As a preferred embodiment, the material of the work function layer 9 includes at least one of TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TiBN, TaN, TaSiN and TiSiN. The material of the gate electrode 7 and the dummy gate 8 includes at least one of Cu, W, Co, Al, Ag, Au, Pt and Ni.

[0050] Exemplarily, the material of the work function layer 9 is TiAlN, and the materials of the gate electrode 7 and the dummy gate 8 are both Cu.

[0051] In another embodiment, a method for manufacturing a high voltage semiconductor device is provided, comprising: An intermediate semiconductor structure is provided, the intermediate semiconductor structure includes a semiconductor substrate 1, a channel region 2, a drain region 3, a drain 4 formed in the drain region 3, a source region 13, and a source 14 formed in the source region 13 are formed in the semiconductor substrate 1. A gate 5 is formed on the surface of the channel region 2; a first isolation region 6 is formed in the drain region 3, and the first isolation region 6 is located between the drain 4 and the gate 5; the source region 13 and the drain region 3 are of a first conductivity type, and the semiconductor substrate 1 and the channel region 2 are of a second conductivity type.

[0052] A protection layer 16 covering the source 14, the gate 5 and the drain 4 is formed on the intermediate semiconductor structure, an interlayer dielectric layer 10 is formed on the protection layer 16, the interlayer dielectric layer 10 is etched to a set depth to form a first groove body 12 for accommodating the gate electrode 7, and an electrode material is deposited in the first groove body 12 to form the gate electrode 7, the gate electrode 7 is connected to the gate 5, and is used to connect the gate 5 to an external control circuit.

[0053] The interlayer dielectric layer 10 is etched and extended to a set depth in the first isolation region 6 to form a receiving groove 61, a work function layer 9 is formed on the groove wall of the receiving groove 61, an electrode material is deposited on the work function layer 9 to form a virtual gate 8, and the virtual gate 8 is connected to the gate electrode 7 to form an independent MOS. The gate 5 is connected to the virtual gate 8 to form a closed loop structure.

[0054] The specific manufacturing examples are as follows: Fabrication of intermediate semiconductor structures, including: See also Figure 3 As shown, a semiconductor substrate 1 is provided. In this embodiment, the semiconductor substrate 1 is a doped silicon wafer, and the doping type is P type.

[0055] See also Figure 3 As shown, a well region 17 is formed on the semiconductor substrate 1, and the well region 17 is of the second conductivity type, namely, P type.

[0056] See also Figure 3 As shown, the well region 17 is etched to form a shallow trench 15, see Figure 4As shown, an insulating material is filled into the shallow trench 15 to obtain a first isolation region 6, and the insulating material is, for example, silicon oxide. A first sacrificial layer 18 is grown on the surface of the well region 17. In this embodiment, the semiconductor substrate 1 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced into the furnace tube. The upper surface of the well region 17 reacts with the oxygen at high temperature to generate a dense first sacrificial layer 18. After the first sacrificial layer 18 is formed, a second sacrificial layer 19 is formed on the upper surface of the first sacrificial layer 18. The second sacrificial layer 19 is, for example, silicon nitride or a mixed layer of silicon nitride and silicon oxide. In this embodiment, the second sacrificial layer 19 is, for example, silicon nitride. Among them, the first sacrificial layer 18 as a buffer layer can improve the stress between the base well region 17 and the second sacrificial layer 19. In the present invention, for example, the second sacrificial layer 19 can be formed on the first sacrificial layer 18 by methods such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0057] A photoresist layer 20 is formed on the second sacrificial layer 19, and a plurality of openings are formed on the photoresist layer 20 through processes such as exposure and development, and the openings are used to locate the position of the shallow trench isolation structure. The photoresist layer 20 is used as a mask, and the second sacrificial layer 19 located under the photoresist layer 20 is quantitatively removed by etching methods such as dry etching, wet etching, or a combination of dry etching and wet etching. Then, the second sacrificial layer 19 is used as a mask to remove the first sacrificial layer 18 and part of the semiconductor substrate 1 in situ, and obtain a shallow trench 15 with a depth D1 of 330nm, and the cross section of the shallow trench 15 is an inverted trapezoidal structure. In this embodiment, for example, dry etching is used to form the shallow trench 15, and the etching gas is, for example, chlorine, difluoromethane, trifluoromethane, nitrogen trifluoride, sulfur hexafluoride or hydrogen bromide, or a mixture of them and oxygen. After the etching is completed, the photoresist layer 20 is removed, and the photoresist layer 20 is removed, for example, by oxygen plasma removal or wet removal.

[0058] See also Figure 4As shown, after the shallow trench 15 is formed, an insulating material is deposited in the shallow trench 15, for example, by high density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio chemical vapor deposition (HARP-CVD), and the insulating material is, for example, an insulating material such as silicon oxide. After the insulating material is deposited, a planarization process such as chemical mechanical polishing (CMP) is performed to place the insulating material and the top of the second sacrificial layer 19 on the same plane, forming a plurality of shallow trench isolation structures, namely, the first isolation region 6 and the second isolation region 38.

[0059] After forming the shallow trench isolation structure, the second sacrificial layer 19 is removed. For example, the second sacrificial layer 19 is removed by a wet process, and the wet etching solution uses hot phosphoric acid. By setting a plurality of shallow trench isolation structures, wherein the second isolation region 38 is arranged between adjacent semiconductor devices to isolate different semiconductor devices and reduce mutual interference between semiconductor devices. A first isolation region 6 is also formed in the drain region 3 between the gate 5 and the drain 4 to increase the length between the drain 4 and the source 14, thereby increasing the source-drain breakdown voltage BVD of the high-voltage semiconductor device.

[0060] In one embodiment, the material of the first isolation region 6 and the second isolation region 38 is the same as that of the first sacrificial layer 15 , which is silicon oxide.

[0061] Before depositing the insulating material, a lining oxide layer is formed on the inner wall of the shallow trench 15. The lining oxide layer can provide additional isolation to ensure good electrical isolation between the filling insulating material (usually silicon oxide or other dielectric) in the shallow trench 15 and the surrounding silicon substrate. In addition, the lining oxide layer can also improve the interface quality between the sidewall of the shallow trench 15 and the insulating material, thereby improving the reliability of the entire structure. At the same time, the lining oxide layer can also reduce the stress caused by the mismatch of the thermal expansion coefficient between the filling insulating material of the shallow trench 15 and the silicon substrate.

[0062] See also Figure 5As shown, after the first isolation region 6 is formed, ion implantation is performed on both sides of the first isolation region 6 to form a source region 13 and a drain region 3, respectively, and a channel region 2 that is not implanted with ions is retained between the first isolation region 6 and the source region 13. The source region 13 and the drain region 3 are of the first conductivity type, i.e., N-type, and the channel region 2 shown is maintained as the second conductivity type, i.e., P-type. Specifically, after forming the shallow trench isolation structure, i.e., the first isolation region 6 and the second isolation region 38, a photoresist layer 20 is coated on the upper surface of the first sacrificial layer 18 of the semiconductor substrate 1, and an opening is formed on the photoresist layer 20 through processes such as exposure and development, and the source region 13 and the drain region 3 are located by the opening. Then, ion implantation is performed using the photoresist layer 20 as a mask, and the type of the implanted ions is opposite to the type of ions in the well region 17. In this embodiment, the doping ions in the source region 13 and the drain region 3 are N-type impurities such as phosphorus (P) or arsenic (As).

[0063] See also Figure 6 As shown, after the source region 13 and the drain region 3 are formed, the photoresist layer 20 is removed, and a gate 5 is formed on the channel region 2. A gate dielectric layer 21 is provided between the gate 5 and the well region 17, wherein the gate dielectric layer 21 is, for example, silicon dioxide, a high dielectric constant dielectric layer, a low dielectric constant dielectric layer or a combination of multiple dielectric layers, and the gate 5 is, for example, a polysilicon gate or a metal gate. In this embodiment, the gate dielectric layer 21 is the first sacrificial layer 18 located below the gate 5, that is, the gate dielectric layer 21 is formed by etching away a portion of the first sacrificial layer 18, so that the upper surfaces of a portion of the drain region 3, the source region 13, the first isolation region 6 and the second isolation region 38 are flush with the upper surface of the semiconductor device 1, and the remaining first sacrificial layer 18 is used as the gate dielectric layer 21, and a gate and a sidewall structure 22 located on the side of the gate 5 are formed on the gate dielectric layer 21.

[0064] A sidewall structure 22 is provided on the side of the gate 5 structure, and the sidewall structure 22 is, for example, a stacked structure of silicon oxide, silicon nitride, or silicon oxide and silicon nitride. In the present embodiment, the sidewall structure 22 is, for example, a stacked structure of silicon oxide and silicon nitride. Specifically, the stacked structure includes a first silicon oxide layer 221, a first silicon nitride layer 222, a second silicon oxide layer 223, and a second silicon nitride layer 224, which are sequentially arranged from the inside to the outside.

[0065] See also Figure 7As shown, after the gate 5 is formed, a source 14 is formed on the source region 13, and a drain 4 is formed on the drain region 3. Specifically, the source 14 and the drain 4 are formed by an ion implantation process, and the surface of the source region 13 and the surface of the drain region 3 are heavily doped to obtain a heavily doped region. The source region 13 and the drain region 3 have the same heavy doping type, and the doping ions are N-type impurities such as phosphorus (P) or arsenic (As). The edge of the heavily doped region at the source region 13 is aligned with the edge of the sidewall structure 22 away from the gate 5, and the heavily doped region at the source region 13 is used as the source 14 of the high-voltage semiconductor device, and the heavily doped region at the drain region 3 is used as the drain 4 of the high-voltage semiconductor device.

[0066] See also Figure 7 As shown, after the source 14 and the drain 4 are formed, a self-aligned metal silicide 23 is formed on the source 14, the drain 4 and the gate 5 of the semiconductor device. The self-aligned metal silicide 23 is, for example, low-resistance nickel silicide (NiSi), cobalt silicide (CoSi2) or titanium silicide (TiSi2). By forming the self-aligned metal silicide 23, the contact resistance between the subsequently formed metal connection structure and the semiconductor device is reduced, the performance of the semiconductor device is improved, and the source 14 or the drain 4 is prevented from being broken down or leaking electricity, thereby improving the stability of the semiconductor device. The self-aligned metal silicide 23 can also be used as a contact structure of the semiconductor device to lead out the source 14, the drain 4 and the gate 5 of the semiconductor device.

[0067] See also Figure 8 As shown, after the self-aligned metal silicide 23 is formed, a protective layer 16 is formed on the semiconductor substrate 1. The protective layer 16 covers the source 14, the drain 4, the gate 5 and the sidewall structure 22, and the protective layer 16 is, for example, a silicon nitride layer. Exemplarily, the protective layer 16 is prepared by a low-temperature deposition method such as plasma enhanced chemical vapor deposition (PECVD), and the deposition source includes a nitrogen source and a silicon source, wherein the nitrogen source is selected from one or a combination of nitrogen (N2) or ammonia (NH3), and the silicon source is selected from one or a combination of silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4) or hexachlorodisilane (Si2Cl6).

[0068] See also Figure 8As shown, after the protective layer 16 is formed, an interlayer dielectric layer 10 is formed on the protective layer 16. The interlayer dielectric layer 10 is prepared, for example, by silicon dioxide or a low dielectric constant (Low-K) material to improve the reliability of the semiconductor structure. And the interlayer dielectric layer 10 is deposited, for example, by a high aspect ratio process to improve the filling capacity of the interlayer dielectric layer 10. Specifically, a silicon-containing precursor and an oxygen-containing precursor are deposited at a temperature range of 400°C to 500°C and a pressure of 30torr to 760torr. The silicon-containing precursor includes, for example, one of silane or tetraethyl orthosilicate (TEOS), and the oxygen-containing precursor includes, for example, one of O2 or O3. In this embodiment, the silicon-containing precursor is, for example, TEOS, and the oxygen-containing precursor is, for example, O3. The interlayer dielectric layer 10 is deposited at a temperature of 430°C and a pressure of 500torr, and the deposition time is 100s to 150s. After the interlayer dielectric layer 10 is formed, a planarization process is performed on the interlayer dielectric layer 10 , for example, a chemical mechanical polishing (CMP) process is used to remove a portion of the interlayer dielectric layer 10 , to ensure that the upper surface of the interlayer dielectric layer 10 is flat, thereby improving the convenience of the metal connection structure.

[0069] See also Figure 8 As shown, after the interlayer dielectric layer 10 is formed, a third sacrificial layer 26 is formed on the interlayer dielectric layer 10, and a photoresist layer 20 is formed on the third sacrificial layer 26. Through processes such as exposure and development, three openings are formed on the photoresist layer 20, and the three openings are used to locate the positions of the first conductive plug 11, the third conductive plug 36, and the fourth conductive plug 37. With the photoresist layer 20 as a mask, the third sacrificial layer 26, the protective layer 16, and part of the self-aligned metal silicide 23 under the photoresist layer 20 are quantitatively removed by dry etching, wet etching, or a combination of dry etching and wet etching, so as to form three conductive plug channels 27 for depositing the first conductive plug 11, the third conductive plug 36, and the fourth conductive plug 37.

[0070] See also Fig. 9As shown, after the conductive plug channel 27 is formed, a first barrier layer 28 is deposited on the inner wall of the three conductive plug channels 27 to contact the self-aligned silicide 23 on the source 14, the drain 4, and the gate 5. The example materials of the first barrier layer 28 include but are not limited to Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. Exemplarily, the deposition process is physical vapor deposition (PVD), electrochemical plating (ECP) or chemical vapor deposition (CVD). Finally, the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37 are deposited in the first barrier layer 28. Exemplarily, the materials of the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37 are copper (Cu) or tungsten (W). In this embodiment, metal tungsten is selected as the deposition material of the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37. The photoresist layer 20 and the third sacrificial layer 26 are removed, and the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37 are planarized to ensure that the upper surfaces of the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37 are on the same plane as the upper surface of the interlayer dielectric layer 10, so as to obtain an intermediate semiconductor structure.

[0071] After the intermediate semiconductor structure is obtained, the gate electrode 7 and the dummy gate 8 are deposited and formed integrally, that is, firstly, a first groove body 12 for accommodating the gate electrode 7 and an accommodating groove 61 for accommodating the dummy gate 8 are formed synchronously by etching. The first groove body 12 includes a main body 121 and an extension portion 122 extending toward the accommodating groove 61 to be interconnected. The main body 121 is formed on the upper part of the interlayer dielectric layer 10 by etching, and the extension portion 122 is etched through the interlayer dielectric layer 10 and the protective layer 16 to the first isolation region 6, and the accommodating groove 61 is sunk into the first isolation region 6 by etching. Then, a work function layer 9 is deposited synchronously on the inner wall of the main body 121, the extension portion 122 and the accommodating groove 61. Then, an electrode material is deposited synchronously on the work function layer 9 to form the gate electrode 7 and the dummy gate 8.

[0072] Specifically, see Fig.10As shown, after the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37 are formed, a fourth sacrificial layer 30 is formed on the upper surface of the interlayer dielectric layer 10. Exemplarily, the fourth sacrificial layer 30 includes silicon carbon nitride (SiCN), silicon carbon oxygen (SiCO), tetraethoxysilane (TEOS), titanium nitride (TiN), silicon oxynitride (SiON), oxide (OX), and anti-reflective coating (BARC) deposited in sequence from bottom to top. A photoresist layer 20 is coated on the upper surface of the fourth sacrificial layer 30, and an opening corresponding to the source 14, the drain 4, and the gate 5 is formed on the photoresist layer 20 through processes such as exposure and development, and the positions of the first slot body 12, the second slot body 39 and the third slot body 40 are positioned by the opening.

[0073] See also Fig.11 As shown, with the photoresist layer 20 as a mask, a portion of the fourth sacrificial layer 30 located under the photoresist layer 20 is quantitatively removed by dry etching, wet etching, or a combination of dry etching and wet etching to form a main body 121 of the first groove body 12 corresponding to the gate 5, a second groove body 39 corresponding to the source 14, and a third groove body 40 corresponding to the drain 4.

[0074] See also Fig.12 As shown, after forming the first tank body 12, the second tank body 39 and the third tank body 40, a fifth sacrificial layer 31 is formed on the surface of the product, and the fifth sacrificial layer 31 includes an ODL layer and an SHB layer coated from bottom to top. The ODL layer is a polymer organic structure layer with a high carbon content, which mainly plays a flattening role; the SHB layer is a silicon-based hard mask intermediate layer structure, which mainly plays an anti-reflective role. Then, a photoresist layer 20 is coated on the upper surface of the fifth sacrificial layer 31, and an opening corresponding to the first isolation region 6 between the gate 5 and the drain 4 is formed on the photoresist layer 20 through processes such as exposure and development, so as to position the extension portion 122 of the first tank body 12 through the opening.

[0075] See also Fig.13 As shown, the fifth sacrificial layer 31 under the photoresist layer 20 is quantitatively removed by dry etching, wet etching, or a combination of dry etching and wet etching, with the photoresist layer 20 as a mask. Then, the fourth sacrificial layer 30 and part of the interlayer dielectric layer 10 are removed in situ with the fifth sacrificial layer 31 as a mask, and the receiving groove 61 in the first isolation region 6 between the drain 4 and the gate 5, and the first groove body 12, the second groove body 39 and the third groove body 40 respectively connected to the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37 are formed, wherein the second groove body 39 corresponding to the source 14 and the third groove body 40 corresponding to the drain 4 are both U-shaped in cross section, and the first groove body 12 corresponding to the gate 5 is in an inverted L-shaped in cross section.

[0076] The first tank body 12 includes a main body 121 arranged horizontally and an extension 122 connected to the lower right side of the main body 121. The extension 122 extends vertically, and the lower end is connected to the upper opening of the receiving groove 61, that is, the receiving groove 61 and the tank body 12 corresponding to the gate 5 are formed as a reverse L-shaped deposition groove. In this embodiment, the extension 122 is a through hole, the upper end of which is connected to the right end of the main body 121, and the lower end of the through hole is connected to the upper opening of the receiving groove 61. A preset distance is left between the inner wall of the receiving groove 61 and the inner wall of the shallow groove 15, and the two are not in direct contact. For example, see Fig.13 As shown, the distance D2 between the bottom of the receiving groove 61 and the bottom of the shallow groove 15 is 3 nm.

[0077] See also Figure 2 As shown, after the extension of the first slot body 12 and the receiving groove 61 are formed, a work function layer 9 is deposited synchronously in the first slot body 12, the second slot body 39 and the third slot body 40 corresponding to the positions of the gate 5, the source 14 and the drain 4, and the receiving groove 61 located in the first isolation region 6. Exemplarily, the material of the work function layer 9 is TiAlN, and its formation process includes: depositing a titanium nitride layer with a thickness of 1nm and a titanium chloride layer with a thickness of 4.8nm on the inner wall of the slot body 12 or the receiving groove 61 in sequence, and performing diffusion annealing after the deposition is completed. The annealing temperature is set to 400°C, and the annealing time is set to 20-40s, so that the aluminum in the titanium chloride layer diffuses into the titanium nitride layer to form TiAlN, i.e., the work function layer 9. Since the work function layer 9 is deposited synchronously, no additional NMOS and PMOS metal work function layer masks will be added, and the manufacturing process can be achieved completely based on existing conditions, saving process costs.

[0078] See also Figure 2 As shown, after the work function layer 9 is formed, a second barrier layer 29 is deposited on the inner wall of the work function layer 9, and the second barrier layer 29 includes a TaN layer with a thickness of 6 nm and a Ta layer with a thickness of 5 nm. Finally, copper is deposited on the inner wall of the second barrier layer 29 simultaneously to form a source electrode 25 electrically connected to the source 14 through the third conductive plug 36, a drain electrode 24 electrically connected to the drain 4 through the fourth conductive plug 37, and a gate electrode 7 electrically connected to the gate 5 through the first conductive plug 11. The copper layer deposition thickness in the main body 121 of the first groove body 12, the second groove body 39, and the third groove body 40 is 12.5 nm.

[0079] The gate electrode 7 is in an inverted "L" shape, including a main section 71 formed in the main body 121 of the first trench body 1 on the upper part of the interlayer dielectric layer 10, and an extension section 72 penetrating the interlayer dielectric layer 10 and the protective layer 16 and formed in the extension section 122 of the first trench body 1. The upper end of the extension section 72 is connected to the main section 71, and the lower end of the extension section 72 is connected to the dummy gate 8 sunk into the first isolation region 6.

[0080] Among them, the source electrode 25 is electrically connected to the self-aligned silicide 23 on the lower source 14 through the third conductive plug 36, the drain electrode 24 is electrically connected to the self-aligned silicide 23 on the lower drain 4 through the fourth conductive plug 37, and the left end of the main section 71 of the gate electrode 7 is electrically connected to the self-aligned silicide 23 on the lower gate 5 through the first conductive plug 11. When the gate electrode 7 is under the working voltage condition, due to the presence of the special work function layer 9, it is ensured that the gate 5 and the virtual gate 8 can work synchronously under the same voltage condition, and the electrons in the drain region 3 under the drain 4 are quickly sucked into the interface between the first isolation region 6 and the drain region 3 and gathered, shortening the movement trajectory of the electrons, reducing the transmission time of the electrons in the drain region 3, thereby reducing the on-resistance of the device. And due to the presence of the first isolation region 6, it plays a role in increasing the source-drain breakdown voltage. In summary, the high-voltage semiconductor device provided by the present invention can solve the problem of limited optimization of the source-drain breakdown voltage and on-resistance of the high-voltage semiconductor device in the prior art.

[0081] In one embodiment, see Fig.14 As shown, a P-type lightly doped region 32 is formed by ion implantation around the active region, i.e., the source region 13 and the drain region 3, and a P-type heavily doped region 33 is formed by ion implantation on the surface of the P-type lightly doped region 32. A self-aligned metal silicide 23 is formed on the upper surface of the P-type heavily doped region 33, and a lead-out electrode 34 is deposited on the upper part of the interlayer dielectric layer 10. The lead-out electrode 34 is connected to the self-aligned metal silicide 23 on the upper surface of the P-type heavily doped region 33 through a second conductive plug 35 formed in the interlayer dielectric layer 10 and the protective layer 16, which is conducive to achieving grounding of the semiconductor substrate 1.

[0082] The present invention has the following unexpected technical effects: the high-voltage semiconductor device of the present invention is designed with a unique virtual gate structure, one end of the virtual gate 8 is sunk into the first isolation region 6, and the other end is connected to the gate electrode 7, forming an independent MOS, that is, a MOS independent of the gate 5 (i.e., the main gate). At the same time, a work function layer 9 is arranged on the outer surface of the virtual gate 8 to ensure that the gate 5 (i.e., the main gate) and the virtual gate 8 can work synchronously under the same voltage condition. In this way, the virtual gate 8 and the work function layer 9 are arranged at the same time. When a turn-on voltage is given to the gate 5, the virtual gate 8 connected to the gate 5 can quickly absorb the electrons in the drain region 3 below the drain 4 to the interface between the first isolation region 6 and the drain region 3 and gather them, shortening the movement trajectory of the electrons and reducing the transmission time of the electrons in the drain region 3, thereby reducing the on-resistance of the device. And due to the existence of the first isolation region 6, the source-drain breakdown voltage is improved.

[0083] Based on the unique structure of the high-voltage semiconductor device of the present invention, it is possible to manufacture a metal work function layer having both NMOS and PMOS through a simple process flow, and connect the main gate structure with the metal virtual gate sunk into the STI without adding additional masks for the NMOS and PMOS metal work function layers, and the manufacturing process can be implemented entirely based on existing conditions, saving process costs.

[0084] The above embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Any equivalent substitution or change made by a person skilled in the art based on the present invention is within the protection scope of the present invention.

Claims

1. A high voltage semiconductor device, comprising: Semiconductor substrate (1); A channel region (2), a drain region (3), a drain electrode (4) formed in the drain region (3), a source region (13), and a source electrode (14) formed in the source region (13) formed in the semiconductor substrate (1), the drain region (3) and the source region (13) being of a first conductivity type, and the semiconductor substrate (1) and the channel region (2) being of a second conductivity type; A gate (5) formed on the semiconductor substrate (1) and located above the channel region (2); It is characterized by further comprising: A first isolation region (6) formed in the drain region (3) and located between the drain electrode (4) and the gate electrode (5); A gate electrode (7) connected to the gate (5) and used to connect the gate (5) to an external control circuit; A virtual gate (8), one end of which is sunken into the first isolation region (6) and the other end of which is connected to the gate electrode (7) to form an independent MOS, and the gate (5) and the virtual gate (8) are connected to form a closed loop structure; A work function layer (9) is formed on the surface of the virtual gate (8).

2. The high voltage semiconductor device according to claim 1, characterized in that: The virtual gate (8) is formed by extending the material forming the gate electrode (7) toward the first isolation region (6) and sinking into the first isolation region (6), and is an integral structure with the gate electrode (7).

3. The high voltage semiconductor device according to claim 2, characterized in that: A protective layer (16) covering the source electrode (14), the gate electrode (5) and the drain electrode (4) is formed on the surface of the semiconductor substrate (1); an interlayer dielectric layer (10) is formed on the protective layer (16); and the gate electrode (7) comprises a main body section (71) formed on the upper part of the interlayer dielectric layer (10) and an extension section (72) penetrating the interlayer dielectric layer (10) and the protective layer (16); The upper end of the extension section (72) is connected to the main section (71), and the lower end of the extension section (72) is connected to a virtual gate (8) sunk into the first isolation region (6); The gate electrode (7) is electrically connected to the gate (5) via a first conductive plug (11).

4. The high voltage semiconductor device according to claim 2, characterized in that: The work function layer (9) extends from the surface of the virtual gate (8) along the overall structure to the surface of the gate electrode (7).

5. The high voltage semiconductor device according to claim 1, characterized in that: It also includes a lightly doped region (32) formed in the semiconductor substrate (1) and a heavily doped region (33) formed on the upper part of the lightly doped region (32), the lightly doped region (32) and the heavily doped region (33) being of the second conductivity type; The lightly doped region (32) is arranged outside the drain region (3) and the source region (13), and the heavily doped region (33) is connected to the lead-out electrode (34) via a second conductive plug (35).

6. A method for manufacturing a high voltage semiconductor device, characterized in that: include: An intermediate semiconductor structure is provided, the intermediate semiconductor structure comprising a semiconductor substrate (1), wherein a channel region (2), a drain region (3), a drain electrode (4) formed in the drain region (3), a source region (13), and a source electrode (14) formed in the source region (13) are formed in the semiconductor substrate (1); a gate electrode (5) is formed on the surface of the channel region (2); the source region (13) and the drain region (3) are of a first conductivity type, and the semiconductor substrate (1) and the channel region (2) are of a second conductivity type; a first isolation region (6) is formed in the drain region (3), and the first isolation region (6) is located between the drain electrode (4) and the gate electrode (5); A protective layer (16) covering the source electrode (14), the gate electrode (5) and the drain electrode (4) is formed on the intermediate semiconductor structure, an interlayer dielectric layer (10) is formed on the protective layer (16), the interlayer dielectric layer (10) is etched to form a first groove (12) accommodating a gate electrode (7), and an electrode material is deposited in the first groove (12) to form the gate electrode (7), the gate electrode (7) is connected to the gate electrode (5), and is used to connect the gate electrode (5) to an external control circuit; The interlayer dielectric layer (10) is etched and extended into the first isolation region (6) to form a receiving groove (61); a work function layer (9) is formed on the groove wall of the receiving groove (61); an electrode material is deposited on the work function layer (9) to form a virtual gate (8); the virtual gate (8) is connected to the gate electrode (7) to form an independent MOS; the gate (5) is connected to the virtual gate (8) to form a closed loop structure.

7. The method for manufacturing a high voltage semiconductor device according to claim 6, characterized in that: The gate electrode (7) and the dummy gate (8) are formed by integral deposition, that is, firstly, a first groove body (12) for accommodating the gate electrode (7) and an accommodating groove (61) for accommodating the dummy gate (8) are formed synchronously by etching, the first groove body (12) comprising a main body (121) and an extension portion (122) extending toward the accommodating groove (61) to be interconnected, the main body (121) being formed on the upper part of the interlayer dielectric layer (10) by etching, the extension portion (122) passing through the interlayer dielectric layer (10) and the protective layer (16) by etching to the first isolation region (6), and the accommodating groove (61) being sunk into the first isolation region (6) by etching; then, a work function layer (9) is synchronously deposited on the inner wall of the main body (121), the extension portion (122) and the accommodating groove (61); and then, an electrode material is synchronously deposited on the work function layer (9) to form the gate electrode (7) and the dummy gate (8).

8. The method for manufacturing a high voltage semiconductor device according to claim 6, characterized in that: Also includes: A first conductive plug (11) is formed in the interlayer dielectric layer (10) and the protective layer (16), the lower end of the first conductive plug (11) is connected to the gate electrode (5), and the upper end of the first conductive plug (11) is electrically connected to the gate electrode (7).

9. The method for manufacturing a high voltage semiconductor device according to claim 6, characterized in that: Also includes: Ion implantation is performed outside the drain region (3) and the source region (13) in the semiconductor substrate (1) to form a lightly doped region (32), and a heavily doped region (33) is formed on the upper surface of the lightly doped region (32) by ion implantation, wherein the lightly doped region (32) and the heavily doped region (33) are of the second conductivity type; A second conductive plug (35) is formed in the interlayer dielectric layer (10) and the protective layer (16), the lower end of the second conductive plug (35) is connected to the heavily doped region (33), and the upper end of the second conductive plug (35) is electrically connected to the lead-out electrode (34).

10. The method for manufacturing a high voltage semiconductor device according to claim 6, characterized in that: The manufacturing of the intermediate semiconductor structure comprises: Providing a semiconductor substrate (1); forming a well region (17) on the semiconductor substrate (1), wherein the well region (17) is of a second conductivity type; Etching the well region (17) to form a shallow trench (15), and filling the shallow trench (15) to obtain a first isolation region (6); Ion implantation is performed on both sides of the first isolation region (6) to form a source region (13) and a drain region (3), a channel region (2) not implanted with ions is retained between the source region (13) and the first isolation region (6), the source region (13) and the drain region (3) are of the first conductivity type, and the channel region (2) is of the second conductivity type; A gate electrode (5) is formed on the channel region (2), a source electrode (14) is formed in the source region (13), and a drain electrode (4) is formed in the drain region (3).

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