Trench gate super-junction MOS (Metal Oxide Semiconductor) structure and preparation method thereof

Abstract

The invention relates to a trench gate super-junction MOS structure and a preparation method thereof. The trench gate super-junction MOS structure comprises a first conductive type substrate; the first conductive type epitaxial layer is arranged on the front surface of the first conductive type substrate; the second conductive type body region is arranged on the front surface of the first conductive type epitaxial layer and is positioned in the first conductive type epitaxial layer; the number of the second conductive type columns is at least two, and the second conductive type columns extend from the front face of the first conductive type epitaxial layer to the first conductive type epitaxial layer. The trench gate structure is arranged between two adjacent second conductive type columns and extends from the front surface to the back surface of the second conductive type epitaxial layer; the second conductive type doped column is arranged corresponding to the trench gate structure and is arranged on the back surface of the trench gate structure; and the first conductive type source region is arranged on the front surface of the second conductive type body region and is positioned in the second conductive type body region. The semiconductor device has the effects of further reducing the on resistance, reducing the electric field in the gate oxide layer and protecting the gate oxide layer.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronics, and in particular to a trench gate super junction MOS structure and a preparation method thereof. Background Art

[0002] MOS is one of the basic components in integrated circuit technology. Its main advantages include high integrability, fast switching speed, low power consumption, good electrical isolation and stability, which make it widely used in various applications such as digital circuits, analog circuits, microprocessors, memories and power amplifiers. The key innovation of planar MOS lies in the application of metal, oxide and semiconductor structures to transistor design. By forming a layer of oxide (usually silicon dioxide) on the semiconductor surface and using metal as the gate above it, the gate voltage is used to control the resistance of the conductive channel on the semiconductor surface between the source and drain to control the conductivity of the channel, thereby realizing the switching and amplification functions of the device.

[0003] In modern electronic devices, especially in high-frequency and high-power applications, reducing on-resistance is one of the key factors to improve device performance and power efficiency. Superjunction structure and trench gate structure are commonly used technologies. The superjunction structure replaces the N-type drift region by alternating P-type columns and N-type columns to ensure sufficient breakdown voltage while reducing on-resistance. The trench gate structure etches trenches on the semiconductor substrate and forms a gate in the trench, increasing the contact area and improving the gate's ability to control the channel current. This not only enables the device to achieve a larger current under the same gate drive voltage, but also greatly reduces the on-resistance.

[0004] Although the simultaneous application of the superjunction structure and the trench gate structure can further reduce the on-resistance and conduction loss, when the surface of the MOS structure bears a higher electric field, the electric field in the gate oxide layer will still be high, and the electric field in the gate oxide layer will be even higher. At this time, it is necessary to reduce the electric field in the gate oxide layer to avoid the gate oxide layer being broken down and causing the MOS structure to fail. There is currently no public technical solution that can both reduce the electric field in the gate oxide layer and further reduce the on-resistance. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a trench gate super junction MOS structure to solve the technical problem in the prior art of reducing the electric field in the gate oxide layer, protecting the gate oxide layer, and further reducing the on-resistance.

[0006] The present invention provides a trench gate super junction MOS structure, comprising:

[0007] a first conductive type substrate;

[0008] A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate;

[0009] A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer;

[0010] At least two second conductive type columns are provided, extending from the front surface of the first conductive type epitaxial layer to the first conductive type epitaxial layer;

[0011] a trench gate structure, disposed between two adjacent second-conductivity-type pillars and extending from the front surface to the back surface of the first-conductivity-type epitaxial layer;

[0012] a second conductive type doped column, arranged corresponding to the trench gate structure, and arranged on the back side of the trench gate structure and extending toward the back side of the first conductive type epitaxial layer;

[0013] The first conductive type source region is arranged on the front side of the second conductive type body region and is located in the second conductive type body region.

[0014] Optionally, the trench gate structure includes a first trench opened on the front surface of the first conductive type epitaxial layer, a gate is arranged in the first trench, and a gate oxide layer is arranged between the gate and the inner wall of the first trench.

[0015] Optionally, the trench gate further includes a shielding gate disposed in the first trench, and a gate oxide layer is disposed between the shielding gate, the gate electrode, and an inner wall of the first trench.

[0016] Optionally, one or at least two gates may be provided in the first trench.

[0017] Optionally, the first conductive type epitaxial layer includes a first layer and a second layer stacked in sequence on the first conductive type substrate, and the second conductive type column extends from a front surface of the second layer into the first layer.

[0018] Optionally, the resistivity of the first layer is greater than the resistivity of the second layer.

[0019] Optionally, a width of the second conductive type doped column is less than or equal to a width of the first trench.

[0020] Optionally, the second conductivity type ion concentration in the second conductivity type doped column is greater than the second conductivity type ion concentration in the second conductivity type body region.

[0021] Optionally, an insulating dielectric layer is provided on the front side of the second conductive type body region, and a plurality of metal contact holes are opened in the insulating dielectric layer. The plurality of metal contact holes are arranged corresponding to the second conductive type columns and are connected to the second conductive type columns and the first conductive type source region.

[0022] Optionally, it also includes:

[0023] a front metal layer, disposed on the front surface of the insulating dielectric layer, wherein a portion of the front metal layer located at the metal contact through-hole extends into the metal contact through-hole until the metal contact through-hole is completely filled;

[0024] The back metal layer is arranged on the back side of the first conductive type substrate.

[0025] The present invention also provides a method for preparing a trench gate super junction MOS structure, comprising the following steps:

[0026] Selecting a first conductive type substrate and growing a first conductive type epitaxial layer on the front surface of the first conductive type substrate;

[0027] Implanting second conductive type ions into the front surface of the first conductive type epitaxial layer and advancing at high temperature to form a second conductive type body region;

[0028] By photolithography masking, a second trench and a third trench are etched in a partial area of ​​the front surface of the first conductive type epitaxial layer;

[0029] Filling the second trench with a second conductive type column, filling the third trench with a second conductive type doped column, and performing selective etching to etch a first trench on the front side of the second conductive type doped column, and depositing a gate oxide layer, a gate electrode, and a shielding gate in the first trench;

[0030] By photolithography blocking, first conductive type ions are implanted into a partial area on the front surface of the second conductive type body region, and are advanced at high temperature to form a first conductive type source region;

[0031] Depositing an insulating dielectric layer on the surface of the first conductive type epitaxial layer on the side having the second conductive type body region, and etching the insulating dielectric layer to form a metal contact through hole;

[0032] Metal is deposited on the front surface of the insulating dielectric layer and filled with metal contact holes to form a front metal layer, and metal is deposited on the back surface of the first conductive type substrate to form a back metal layer.

[0033] The technical solution of the present invention has the following advantages:

[0034] The trench gate super junction MOS structure provided by the present invention can reduce the on-resistance by providing a trench gate structure compared to a traditional planar gate structure. At the same time, a second conductive type column is provided. Based on the charge balance technology, the thickness of the first conductive type epitaxial layer is reduced under the same withstand voltage, thereby further reducing the on-resistance. On this basis, a second conductive type doped column is provided in the first conductive type epitaxial layer below the trench gate structure, which can provide protection for the gate oxide layer in the trench gate structure, reduce the electric field in the gate oxide layer, avoid the gate oxide layer from being broken down, and cause the MOS structure to fail, thereby improving the device reliability. The entire MOS structure can not only further reduce the on-resistance, but also reduce the electric field in the gate oxide layer and protect the gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 Schematic diagram of the overall structure of the trench gate super junction MOS structure of the present invention;

[0037] Figure 2 is a schematic diagram of another embodiment of the trench gate structure of the present invention;

[0038] Figure 3 1 is a step diagram of the method for preparing a trench gate super junction MOS structure in the present invention.

[0039] Description of reference numerals:

[0040] 1. First conductive type substrate; 2. First conductive type epitaxial layer; 21. First layer; 22. Second layer; 3. Second conductive type body region; 4. First conductive type source region; 5. Second conductive type column; 6. Trench gate structure; 61. Gate; 62. Shielding gate; 63. First trench; 64. Gate oxide layer; 7. Second trench; 8. Insulating dielectric layer; 9. Metal contact via; 10. Front metal layer; 11. Back metal layer; 12. Third trench; 13. Second conductive type doped column. DETAILED DESCRIPTION

[0041] Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, and not all, of the embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the description of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0042] Unless otherwise specified or limited, the terms "disposed," "installed," and "connected" should be interpreted broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; and direct or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of these terms based on the specific circumstances.

[0043] The directions or positional relationships indicated by terms such as "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inside" and "outside" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience and simplification of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, they should not be understood as limiting the present invention.

[0044] The terms "first," "second," "third," etc. are merely used to distinguish elements of similar nature and do not indicate or imply relative importance or a particular order.

[0045] The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0046] Example

[0047] The trench gate super junction MOS structure includes an N-type trench gate super junction MOS structure and a P-type trench gate super junction MOS structure. For the N-type trench gate super junction MOS structure, the first conductivity type is N-type and the second conductivity type is P-type; for the P-type trench gate super junction MOS structure, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, the N-type trench gate super junction MOS structure is taken as an example and the top surface is set as the front surface and the bottom surface is set as the back surface. The direction of the arrow in the figure is the width direction.

[0048] Reference Figure 1As shown, the present invention provides a trench gate super junction MOS structure, including a first conductive type substrate 1, a first conductive type epitaxial layer 2, a second conductive type body region 3, a second conductive type column 5, a trench gate structure 6, a second conductive type doped column 13 and a first conductive type source region 4, wherein the first conductive type substrate 1 selects N-type silicon as a substrate, the first conductive type epitaxial layer 2 is arranged on the front surface of the first conductive type substrate 1, and the first conductive type epitaxial layer 2 is grown using an epitaxial process, the second conductive type body region 3 is arranged on the front surface of the first conductive type epitaxial layer 2 and is located within the first conductive type epitaxial layer 2, the second conductive type body region 3 and the first conductive type epitaxial layer 2 have the same width, at least two second conductive type columns 5 are provided, and the second conductive type columns 5 extend from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2, until extending from the second conductive type body region 3 to the first conductive type epitaxial layer 2 below the second conductive type body region 3;

[0049] At least one trench gate structure 6 is provided correspondingly, and a trench gate structure 6 is provided between each adjacent second conductive type column 5. The trench gate structure 6 also extends from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2, until it extends from the second conductive type body region 3 to the first conductive type epitaxial layer 2 below the second conductive type body region 3. A plurality of second conductive type doped columns 13 are provided, and are arranged corresponding to the plurality of trench gate structures 6. A second conductive type doped column 13 is provided at each trench gate structure 6. The second conductive type doped column 13 is located below the trench gate structure 6 and contacts the trench gate structure 6. The second conductive type doped column 13 extends toward the back surface of the first conductive type epitaxial layer 2.

[0050] The first conductive type source region 4 is arranged on the front side of the second conductive type body region 3 and is located in the second conductive type body region 3. In this embodiment, multiple first conductive type source regions 4 are provided, and each trench gate structure 6 corresponds to two first conductive type source regions 4, which are respectively located on both sides of the trench gate structure 6 toward the second conductive type column 5, and extend toward the second conductive type column 5 and contact the second conductive type column 5.

[0051] By setting up a trench gate structure 6, the on-resistance can be reduced compared to the traditional planar gate structure. At the same time, a second conductive type column 5 is set. Based on the charge balance technology, the thickness of the first conductive type epitaxial layer is reduced under the same withstand voltage, thereby further reducing the on-resistance. On this basis, a second conductive type doped column 13 is set in the first conductive type epitaxial layer 2 below the trench gate structure 6, which can provide protection for the gate oxide layer 64 in the trench gate structure 6, reduce the electric field in the gate oxide layer 64, avoid the gate oxide layer 64 from being broken down, causing the MOS structure to fail, and improve the device reliability. The entire MOS structure can not only further reduce the on-resistance, but also reduce the electric field in the gate oxide layer 64 and protect the gate oxide layer 64.

[0052] Specifically, the trench gate structure 6 includes a first trench 63 opened on the front side of the first conductive type epitaxial layer 2. The first trench 63 extends from the front side of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back side of the first conductive type epitaxial layer 2 until it extends to the first conductive type epitaxial layer 2 on the back side of the second conductive type body region 3. A gate 61 is arranged in the first trench 63. A gate oxide layer 64 is arranged between the gate 61 and the inner wall of the first trench 63. The gate 61 is separated by the gate oxide layer 64 and the inner wall of the first trench 63. The gate 61 is conductive polysilicon. The thickness of the gate oxide layer 64 between the gate 61 and the bottom wall of the first trench 63 is greater than the thickness of the gate oxide layer 64 between the gate 61 and the inner side wall of the first trench 63. The thicker gate oxide layer 64 at the bottom can improve the gate oxygen reliability of the device.

[0053] As another embodiment, the trench gate structure 6 also includes a shielding gate 62 arranged in the first trench 63. The shielding gate 62 is located below the gate 61, and the shielding gate 62 and the inner wall of the first trench 63 are also separated by a gate oxide layer 64. There is a gap between the shielding gate 62 and the gate 61 and they are also separated by the gate oxide layer 64. By setting the shielding gate 62, faster switching speed and lower switching loss can be achieved, further reducing the on-resistance and Miller capacitance, and improving the switching speed; in addition, the second conductive type doped column 13 is located directly below the shielding gate 62. At this time, the shielding gate 62 can disperse the electric field between the bottom of the first trench 63 and the side wall of the second conductive type doped column 13, thereby improving and enhancing the reliability of the gate and ensuring the quality of the super junction MOS structure.

[0054] As another embodiment, referring to Figure 2As shown, two gates 61 are provided in the trench gate structure 6, and a shield gate 62 is located between the two gates 61. Both the gate 61 and the shield gate 62 extend from the notch of the first trench 63 to the interior of the first trench 63. Gaps are left between the gate 61 and the inner wall of the first trench 63 and the shield gate 62. A gate oxide layer 64 is provided between the shield gate 62 and the gate 61, between the gate 61 and the inner wall of the first trench 63, and between the shield gate 62 and the bottom wall of the first trench 63. The gate oxide layer 64 is used to separate them. The depth of the first trench 63 is set to 1.5μm-3μm. The depth of the shield gate 62 in the first trench 63 is greater than the depth of the gate 61 in the first trench 63. In other embodiments, the number of gates 61 is not limited to a single number and can also be set to multiple.

[0055] As a specific embodiment, the second conductive type doped column 13 is set to be columnar, and the width of the second conductive type doped column 13 is less than or equal to the width of the first trench 63. In this embodiment, the width of the second conductive type doped column 13 is less than the width of the first trench 63; the second conductive type ion concentration in the second conductive type doped column 13 is greater than the second conductive type ion concentration in the second conductive type body region 3. The second conductive type doped column 13 with a higher second conductive type ion concentration can effectively reduce the electric field strength in the gate oxide layer 64.

[0056] When the device is turned off, the first conductive type epitaxial layer 2 will be depleted together with the second conductive type doped column 13 and the second conductive type body region 3 to bear the high voltage. Generally speaking, the electric field will be the strongest at the center of the depletion region. If the second conductive type doped column 13 is not set, the position with the strongest electric field will be located at the corner of the first trench 63, which will sharply increase the electric field strength in the gate oxide layer 64. By setting the second conductive type doped column 13 deep into the first conductive type epitaxial layer 2, it will preferentially be depleted with the first conductive type epitaxial layer 2, thereby transferring the depletion center from the corner of the first trench 63 to the corner of the second conductive type doped column 13, so that the position with the strongest electric field strength is far away from the gate oxide layer 64, reducing the electric field strength in the gate oxide layer 64 and improving the reliability of the device.

[0057] As a specific embodiment, the first conductive type epitaxial layer 2 includes a first layer 21 and a second layer 22 stacked in sequence on the first conductive type substrate 1, and the second conductive type column 5 extends from the front of the second layer 22 to the first layer 21, and the depth of the second conductive type column 5 into the first layer 21 does not exceed 5μm. By setting the first layer 21 and the second layer 22, two epitaxy is achieved, which can further reduce the on-resistance of the device. Furthermore, the resistivity of the first layer 21 is greater than the resistivity of the second layer 22 to achieve higher voltage resistance, thereby improving the voltage resistance while keeping the on-resistance low.

[0058] As a specific embodiment, it also includes an insulating dielectric layer 8, a front metal layer 10 and a back metal layer 11, wherein the insulating dielectric layer 8 is arranged on the front side of the second conductive type body region 3 and covers the entire second conductive type body region 3, and a plurality of metal contact holes 9 are opened in the insulating dielectric layer 8, and the metal contact holes 9 are arranged corresponding to the second conductive type columns 5 and penetrate into the second conductive type columns 5 to connect with the second conductive type columns 5 and the first conductive type source region 4; the front metal layer 10 is arranged on the front side of the insulating dielectric layer 8, and the front metal layer 10 is located at the metal contact hole 9 and partially extends into the metal contact hole 9 until the metal contact hole 9 is filled. At this time, the part of the front metal layer 10 in the metal contact hole 9 corresponding to the second conductive type column 5 will contact the second conductive type column 5 and the first conductive type source region 4; the back metal layer 11 is arranged on the back side of the first conductive type substrate 1 and covers the entire back side of the first conductive type substrate 1.

[0059] When a shielding gate 62 is provided and two gates 61 are provided, a metal contact through-hole 9 is also provided in the insulating dielectric layer 8 directly above the shielding gate 62, and the front metal layer 10 will also extend into the metal contact through-hole 9 there to fill the metal contact through-hole 9 there.

[0060] Example 2

[0061] Reference Figure 1 and Figure 3 As shown, this embodiment provides a method for preparing a trench gate super junction MOS structure, comprising the following steps:

[0062] S1, select a first conductive type substrate 1, and continuously grow a first layer 21 and a second layer 22 on the front surface of the first conductive type substrate 1, wherein the first conductive type substrate 1 selects N-type silicon as the substrate, and the first layer 21 and the second layer 22 are grown by an epitaxial process.

[0063] S2, directly perform general injection on the front surface of the first conductive type epitaxial layer 2, inject the second conductive type ions, and advance at high temperature, so as to form a second conductive type body region 3 on the front surface of the first conductive type epitaxial layer 2, and the second conductive type body region 3 covers the entire front surface of the first conductive type epitaxial layer 2.

[0064] S3, through photolithography blocking, a second trench 7 and a third trench 12 are etched in a partial area of ​​the front surface of the first conductive type epitaxial layer 2, the second trench 7 and the third trench 12 are staggered, and the second trench 7 and the third trench 12 both extend from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2, until extending from the second conductive type body region 3 into the first conductive type epitaxial layer 2.

[0065] S4, fill the second trench 7 to form a second conductive type column 5, fill the third trench 12 to form a second conductive type doped column 13, and perform selective etching to etch a first trench 63 on the front of the second conductive type doped column 13, the width of the first trench 63 is greater than the width of the third trench 12, the first trench 63 extends from the front of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back of the first conductive type epitaxial layer 2, until it extends from the second conductive type body region 3 to the first conductive type epitaxial layer 2, and deposits a gate oxide layer 64 and conductive polysilicon in the first trench 63 to form a gate oxide layer 64, a gate 61 and a shielding gate 62; in this embodiment, the gate oxide layer 64 is prepared by deposition, so that the gate can be controlled more accurately. The thickness of the oxide layer 64 is controlled without being limited by the growth rate and events. At the same time, the deposition technology can be carried out on different substrates and manufacturing conditions, so that it is suitable for large-scale production and can be prepared more quickly, thereby improving production efficiency. In addition, the second trench 7 and the third trench 12 can be etched directly at one time through the deep trench technology, and the second conductive type column 5 can be directly filled in the second trench 7 to form the second conductive type doped column 13, and the second conductive type doped column 13 can be filled in the third trench 12 to form the second conductive type doped column. Through the deep trench technology, the preparation of the second conductive type column 5 and the second conductive type doped column 13 can be carried out simultaneously, thereby eliminating the need for multiple steps to form the second conductive type column 5 and the second conductive type doped column 13 respectively, reducing the process steps, optimizing the preparation process, and improving production efficiency.

[0066] S5, through photolithography blocking, first conductive type ions are injected into part of the front area of ​​the second conductive type body region 3, and high temperature is used to advance, so as to form a first conductive type source region 4 in the second conductive type body region 3. Specifically, through the blocking of the photolithography plate, two unblocked areas are formed in the second conductive type body region 3 on both sides of the trench gate structure 6 facing the second conductive type column 5, and the first conductive type ions are injected into the unblocked areas. At this time, two undiffused first conductive type source regions 4 will be formed in the second conductive type body region 3, and then high temperature is used to advance to diffuse and form the first conductive type source region 4. The first conductive type source region 4 is provided on both sides of the trench gate structure 6, and the first conductive type source region 4 will diffuse toward the second conductive type column 5 until it contacts the second conductive type column 5 or extends into the second conductive type column 5.

[0067] S6, an insulating dielectric layer 8 is deposited on the surface of one side of the first conductive type epitaxial layer 2 having the second conductive type body region 3, so that the insulating dielectric layer 8 covers the entire front surface of the first conductive type epitaxial layer 2, and then the insulating dielectric layer 8 is etched to etch a plurality of through holes on the insulating dielectric layer 8, thereby forming a metal contact through hole 9, and the metal contact through hole 9 is located directly above the second conductive type column 5, and during the etching, an additional 0.3 mm to 0.4 mm will be etched into the second conductive type column 5, so as to ensure that the insulating dielectric layer 8 can be completely removed, so that the metal contact point is exposed, and the stability and reliability of the electrical connection are ensured.

[0068] S7 , depositing metal on the front surface of the insulating dielectric layer 8 and filling the metal contact through-holes 9 to form a front metal layer 10 , and depositing metal on the back surface of the first conductive type substrate 11 to form a back metal layer 11 .

[0069] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A trench gate super junction MOS structure, It is characterized in that include: a first conductive type substrate; A first conductive type epitaxial layer, disposed on a front surface of the first conductive type substrate; A second conductive type body region is disposed on the front surface of the first conductive type epitaxial layer and is located in the first conductive type epitaxial layer; At least two second conductive type columns are provided, extending from the front side to the back side of the first conductive type epitaxial layer; A trench gate structure is disposed between two adjacent second conductivity type pillars and extends from the front side to the back side of the first conductivity type epitaxial layer; A second conductive type doped column is arranged corresponding to the trench gate structure and is arranged on the back side of the trench gate structure and extends toward the back side of the first conductive type epitaxial layer; The first conductive type source region is arranged on the front side of the second conductive type body region and is located in the second conductive type body region.

2. The trench gate super junction MOS structure according to claim 1, It is characterized in that The trench gate structure comprises a first trench opened on the front side of the first conductive type epitaxial layer, a gate is arranged in the first trench, and a gate oxide layer is arranged between the gate and the inner wall of the first trench.

3. The trench gate super junction MOS structure according to claim 2, It is characterized in that The trench gate further comprises a shielding gate arranged in the first trench, and a gate oxide layer is arranged between the shielding gate, the gate electrode and the inner wall of the first trench.

4. The trench gate super junction MOS structure according to claim 1, It is characterized in that The first conductive type epitaxial layer includes a first layer and a second layer sequentially stacked on the first conductive type substrate, and the second conductive type column extends from the front side of the second layer into the first layer.

5. The trench gate super junction MOS structure according to claim 4, It is characterized in that The resistivity of the first layer is greater than the resistivity of the second layer.

6. The trench gate super junction MOS structure according to claim 2, It is characterized in that A width of the second conductive type doped column is less than or equal to a width of the first trench.

7. The trench gate super junction MOS structure according to claim 1, It is characterized in that A concentration of second conductivity type ions in the second conductivity type doped pillar is greater than a concentration of second conductivity type ions in the second conductivity type body region.

8. The trench gate super junction MOS structure according to any one of claims 1 to 7, It is characterized in that An insulating dielectric layer is disposed on the front side of the second conductive type body region, and a plurality of metal contact through holes are opened in the insulating dielectric layer. The plurality of metal contact through holes are disposed corresponding to the second conductive type columns and are connected to the second conductive type columns and the first conductive type source region.

9. The trench gate super junction MOS structure according to claim 8, It is characterized in that Also includes: A front metal layer is disposed on the front side of the insulating dielectric layer, and a portion of the front metal layer located at the metal contact through hole extends into the metal contact through hole until the metal contact through hole is completely filled; The back metal layer is arranged on the back side of the first conductive type substrate.

10. A method for preparing a trench gate super junction MOS structure, It is characterized in that The following steps are involved: Selecting a first conductive type substrate, and growing a first conductive type epitaxial layer on the front surface of the first conductive type substrate; Implanting second conductive type ions on the front side of the first conductive type epitaxial layer and advancing at high temperature to form a second conductive type body region; By photolithography masking, a second trench and a third trench are etched in a partial area of ​​the front surface of the first conductive type epitaxial layer; Filling the second trench with a second conductive type column, filling the third trench with a second conductive type doped column, and performing selective etching to etch a first trench on the front side of the second conductive type doped column, and depositing a gate oxide layer, a gate electrode, and a shielding gate in the first trench; By photolithography blocking, first conductive type ions are implanted into a partial area on the front side of the second conductive type body region, and are advanced at high temperature to form a first conductive type source region; Depositing an insulating dielectric layer on the surface of the first conductive type epitaxial layer on the side having the second conductive type body region, and etching the insulating dielectric layer to form a metal contact through hole; Metal is deposited on the front side of the insulating dielectric layer and metal contact holes are filled to form a front side metal layer, and metal is deposited on the back side of the first conductive type substrate to form a back side metal layer.

Images